CN104954061A - High-speed sampling low-speed processing system and high-speed sampling low-speed processing method - Google Patents
High-speed sampling low-speed processing system and high-speed sampling low-speed processing method Download PDFInfo
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- CN104954061A CN104954061A CN201510262293.5A CN201510262293A CN104954061A CN 104954061 A CN104954061 A CN 104954061A CN 201510262293 A CN201510262293 A CN 201510262293A CN 104954061 A CN104954061 A CN 104954061A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/155—Ground-based stations
- H04B7/15507—Relay station based processing for cell extension or control of coverage area
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/403—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
- H04B1/406—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency with more than one transmission mode, e.g. analog and digital modes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/54—Circuits using the same frequency for two directions of communication
- H04B1/58—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
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- Analogue/Digital Conversion (AREA)
Abstract
The invention relates to a high-speed sampling low-speed processing system and a high-speed sampling low-speed processing method in a repeater station. The high-speed sampling low-speed processing system and the high-speed sampling low-speed processing method are typically used in an LTE (long term evolution) repeater station with large bandwidth, high-speed sampling rate is converted into low-speed sampling rate, ultra-wide-band signals can be processed on a low-cost FPGA (field programmable gate array), and cost of equipment is reduced. Intermediate frequency signal frequency in the equipment is set to be 3/4 of the sampling rate, and sampling of analog-to-digital converter is carried out. A sampling outputting end of the analog-to-digital converter (ADC) is connected with an LVDS (low voltage differential signaling) interface of the FPGA, high-speed sampling data can be subjected to signal-to-parallel conversion by the interface and can be converted into two channels of low-speed sampling signals, and the signals are subjected to digital down-conversion. During digital down-conversion, the signals need to be multiplied by an NCO of which the frequency is 1/4 of the sampling frequency of the analog-to-digital converter (ADC); after frequency mixing, half of data of a channel I and half of data of a channel Q are zero; the data, which are not zero, of the channel I and the channel Q are filtered to obtain signals I and signals Q of a base band; and the sampling rate of the signals is halved, so that the purpose of reducing signal rate is achieved.
Description
Technical field
The present invention relates to a kind of high-speed sampling low-speed processing system and method in repeater, reach the object of high-speed sampling low-speed processing.A typical apply of the present invention is exactly in the repeater of LTE 60M bandwidth, and at this moment signal sampling rate is up to more than 200MHz, if do not carried out rate processing, then fpga chip selects middle-end and high-end, greatly increases the manufacturing cost of equipment.
Background technology
Along with the development of radio communication, the bandwidth of signal of communication is increasing, and repeater becomes the important component part of mobile communication signal covering system, and front end analog-to-digital conversion (ADC) sample rate is more and more higher.This makes the clock of signal transacting more and more higher, also comes high at FPGA device speed hierarchical selection, special than be LTE broad frequency band repeater in, this must cause device fabrication cost, and this is unfavorable for manufacture and the popularization of equipment.
Summary of the invention
In order to the repeater of LTE 60M and above bandwidth also can be done in low side FPGA device, the present invention proposes a kind of high-speed sampling low-speed processing system and method.
A kind of high-speed sampling low-speed processing system, it is characterized in that: comprise AD conversion unit (ADC), LVDS parallel serial conversion unit, digital mixing unit, numerically-controlled oscillator (NCO) unit, finite impulse response filter (FIR) unit; Analog to digital converter (ADC) unit, LVDS parallel serial conversion unit, digital mixing unit, finite impulse response filter (FIR) unit connect successively, and numerically-controlled oscillator (NCO) unit is connected with digital mixing unit.The connection of unit and operation principle are: radiofrequency signal mixing is become intermediate-freuqncy signal by repeater radio-frequency front-end, be 3/4 times of AD conversion unit (ADC) sample frequency by the set of frequency of intermediate-freuqncy signal, intermediate-freuqncy signal enters analog to digital converter (ADC), after AD conversion unit (ADC) sampling, first Nat's thinking district frequency of sampled signal is 1/4 times of sample frequency.LVDS parallel serial conversion unit is entered again after analog signal being converted to digital signal, through the LVDS serioparallel exchange interface of FPGA, sampled digital signal is at a high speed converted to the parallel sampling signal of two-way low speed by LVDS parallel serial conversion unit, two-way low speed sampled signal is that the numerically-controlled oscillator (NCO) of AD conversion unit (ADC) sample frequency 1/4 times carries out mixing respectively with frequency, and sampled signal becomes baseband signal.Frequency is numerically-controlled oscillator (NCO) the sinusoidal road of A/D sample frequency 1/4 times is with 0, + 1,0, it is with+1 that cycle of carrying out based on-1 exports cosine road, 0,-1, cycle output is carried out based on 0, after mixing, I road and Q circuit-switched data must have half to be 0, to signal without contribution, filter can not be participated in, and second half non-vanishing data enter finite impulse response filter (FIR) unit, the digit rate of filtered signal reduces half, arrives the object reducing process frequency.
A kind of high-speed sampling low-speed processing method, concrete steps are as follows:
Step one: analog signal is carried out analog frequency mixing to intermediate frequency by receiver rf front-end, the set of frequency of intermediate-freuqncy signal is 3/4 times of AD conversion unit (ADC) sample frequency, enter AD conversion unit (ADC) to sample, after analog to digital converter (ADC) sampling, the frequency of the sampled digital signal of the high speed obtained becomes 1/4 times of analog to digital converter (ADC) sampling rate.
Step 2: the sampled digital signal of high speed step 1 obtained with the LVDS interface of FPGA carries out going here and there and transforming, and high-speed sampling digital signal is changed into the parallel digital signal of two-way low speed, every road signal rate becomes original half.
Step 3: the numerically-controlled oscillator mixing by the parallel digital signal of two-way low speed with frequency being AD conversion unit (ADC) sample frequency 1/4 times respectively, and the sinusoidal road of data that the numerically-controlled oscillator that frequency is AD conversion unit (ADC) sample frequency 1/4 times exports is with 0, + 1, 0, cycle output is carried out based on-1, cosine road is with+1, 0,-1, cycle output is carried out based on 0, NCO data are multiplied with the initial data that ADC samples, the data after being multiplied are made to have half to be 0, to the filtering of data be without contribution, can give up, namely, after mixing, I road and Q road (I and Q represents real part and the imaginary part of quadrature modulation) data have half to be 0.
Step 4: to after mixing be not 0 a semi-digital signal carry out filtering, obtain the I of base band, Q signal, the sampling digit rate of synchronous signal also reduces half, reaches the object reducing processing signals processing speed; Detailed process is: step 3 obtains four road signals, is respectively I
0, I
1, Q
0, Q
1(I
0, I
1, Q
0, Q
1for with the real part of quadrature modulation and imaginary part two paths of data respectively after serioparallel exchange), due to I
1road is 0, to filtering without contribution, so remove I when arranging filter coefficient
1corresponding filter coefficient, leaves I
0corresponding filter coefficient; Q
0the data on road are 0, by Q when arranging filter coefficient
0corresponding filter coefficient removes; Q
1and I
0sampling digit rate only have original A/D to sample the half of digit rate, namely filter exports the half that data rate is ADC sampling rate.
Compared with prior art, advantage of the present invention and beneficial effect:
By the present invention, the digital signal digit rate inputted from AD conversion unit (ADC) is to the output of digital mixer unit, and the digit rate of digital signal reduces half.Even if AD conversion unit (ADC) samples digit rate at more than 200M, after this device will sample digit rate reduction half, signal digit rate only has about 100M, and the FPGA of low side of also can sampling in the LTE repeater in broadband realizes, thus reduces the manufacturing cost of LTE repeater, broadband.
Accompanying drawing explanation
Fig. 1 is principle framework map of the present invention.
Embodiment
With reference to figure 1, the present invention proposes a kind of high-speed sampling low-speed processing system and method, system comprises front end analog to digital converter (ADC), LVDS interface deserializer, frequency mixer, numerically-controlled oscillator (NCO); Analog to digital converter (ADC) unit, LVDS parallel serial conversion unit, digital mixing unit, finite impulse response filter (FIR) unit connect successively, and numerically-controlled oscillator (NCO) unit is connected with digital mixing unit; .Front end analog to digital converter (ADC) sampled signal is through LVDS interface deserializer, sampled data is at a high speed converted to two-way low speed and data, the NCO that process and frequency are sample frequency 1/4 times carries out digital mixing, and the digital signal of sampling is become baseband signal.The sinusoidal road that NCO exports data is with 0 ,+1,0, and carry out cycle output based on-1, cosine road is with+1,0, carry out cycle output based on-1,0, the I of I road signal after mixing
0data are the Q of zero, Q road signal
1road is 0, be the data of 0 to being filtered into contribution, can give up, former like this data only have I
1road and Q
0road is useful, and I
1road and Q
0the speed of circuit-switched data is the half of ADC sampling digit rate, for low side FPGA can process range.
The main flow of the inventive method:
Step 1: the IF-FRE of signal is become 3/4 times of analog to digital converter (ADC) sample frequency by receiver rf front-end.
Step 2: carry out analog to digital converter (ADC) conversion to analog signal, analog signal is converted to digital signal at a high speed, is converted to the parallel signal of two-way low speed by serial digital signal at a high speed through the LVDS interface parallel-serial conversion of FPGA.
Step 3: mixing is carried out to parallel signal, signal times take frequency as the numerically-controlled oscillator (NCO) of sample frequency 1/4 times, the sinusoidal road that NCO exports data is with 0, + 1,0, it is with+1 that the cycle of carrying out based on-1 exports cosine road, cosine road, 0, the I that the cycle exports I circuit-switched data after mixing is carried out based on-1,0
1be the Q of zero, Q circuit-switched data
0be 0, be the data of 0 to being filtered into contribution, can to give up, and I
0road and Q
1the speed of circuit-switched data is the half of ADC sampling digit rate, for low side FPGA can process range.
Step 4: carry out FIR filtering to the data after mixing, due to the I of I circuit-switched data
1be 0, Q circuit-switched data Q
0be 0, to the filtering of signal without contribution, give up.Filtering is I in I circuit-switched data
0enter FIR filter, the coefficient of FIR filter removes I on the basis of a complete filter coefficient
1corresponding coefficient; The Q of Q circuit-switched data
1enter FIR filter, the coefficient of FIR filter gets on the basis of a complete filter coefficient Q
0corresponding coefficient, filtering exports as baseband sampling signal, and the sampling digit rate of the signal simultaneously exported is original half, reaches the object reducing signal sampling digit rate.
Claims (2)
1. a high-speed sampling low-speed processing system, it is characterized in that: comprise analog to digital converter (ADC) unit, LVDS parallel serial conversion unit, digital mixing unit, finite impulse response filter (FIR) unit, numerically-controlled oscillator (NCO) unit; Analog to digital converter (ADC) unit, LVDS parallel serial conversion unit, digital mixing unit, finite impulse response filter (FIR) unit connect successively, and numerically-controlled oscillator (NCO) unit is connected with digital mixing unit;
Intermediate-freuqncy signal enters analog to digital converter (ADC), analog signal is converted to digital signal and enters LVDS parallel serial conversion unit, high-speed sampling digital signal is converted to two-way low speed sampled signal by LVDS parallel serial conversion unit, two-way low speed sampled signal is that the numerically-controlled oscillator (NCO) of analog to digital converter (ADC) sampling rate 1/4 times carries out mixing respectively with frequency, this numerically-controlled oscillator (NCO) exports sinusoidal data with 0, + 1,0, carry out cycle output based on-1; Cosine road is with+1,0,-1, carry out cycle output based on 0, have a half data to be zero after mixing, to signal filtering without contribution, do not carry out filtering, and second half non-vanishing data enter finite impulse response filter (FIR) unit, the digit rate of filtered signal reduces half, thus reduces the speed of processing signals.
2. a high-speed sampling low-speed processing method, is characterized in that: comprise the following steps,
Analog signal is carried out analog frequency mixing to intermediate frequency by step one, receiver rf front-end, the set of frequency of intermediate-freuqncy signal is 3/4 times of analog to digital converter (ADC) sampling rate, enter AD conversion unit (ADC) to sample, after analog to digital converter (ADC) sampling, the frequency of the sampled digital signal of the high speed obtained becomes 1/4 times of analog to digital converter (ADC) sampling rate;
Step 2, the sampled digital signal of high speed step 1 obtained with LVDS interface carry out going here and there and transforming, and every road signal rate becomes original half, is converted to the parallel digital signal of two-way low speed;
Step 3, the numerically-controlled oscillator (NCO) being analog to digital converter (ADC) sampling rate 1/4 times respectively with frequency by the parallel digital signal of two-way low speed carry out mixing, and after mixing, I road and Q circuit-switched data have half to be 0;
Step 4, the half data not being 0 is carried out filtering, obtain the I of base band, Q signal, the sampling digit rate of synchronous signal also reduces half, reaches the object reducing processing signals processing speed.
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Cited By (8)
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|---|---|---|---|---|
| CN106054118A (en) * | 2016-05-24 | 2016-10-26 | 中国民用航空总局第二研究所 | High-speed sampling method and high-speed sampling system for navigation equipment online measurement |
| CN106291501A (en) * | 2016-08-26 | 2017-01-04 | 上海无线电设备研究所 | High-speed Parallel Signal Processing Systems and processing method thereof |
| CN109639277A (en) * | 2018-10-31 | 2019-04-16 | 上海无线电设备研究所 | A kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR |
| CN110460337A (en) * | 2019-08-13 | 2019-11-15 | 刘涛 | A kind of high-speed sampling and reconstructing method |
| CN112083674A (en) * | 2020-09-09 | 2020-12-15 | 中国航空工业集团公司雷华电子技术研究所 | FPGA chip data processing method, chip, computer equipment and storage medium |
| CN113114166A (en) * | 2021-03-12 | 2021-07-13 | 成都辰天信息科技有限公司 | High-speed parallel DDC (direct digital control) and FIR (finite impulse response) filtering processing method based on FPGA (field programmable Gate array) |
| CN114567337A (en) * | 2022-01-14 | 2022-05-31 | 西安电子科技大学重庆集成电路创新研究院 | Ultra-wideband transmitter based on FPGA |
| CN115951105A (en) * | 2023-03-09 | 2023-04-11 | 苏州联讯仪器股份有限公司 | Electric signal sampling channel device and sampling oscilloscope |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106054118A (en) * | 2016-05-24 | 2016-10-26 | 中国民用航空总局第二研究所 | High-speed sampling method and high-speed sampling system for navigation equipment online measurement |
| CN106054118B (en) * | 2016-05-24 | 2018-08-03 | 中国民用航空总局第二研究所 | The high-speed sampling method and system of navigation equipment on-line measurement |
| CN106291501A (en) * | 2016-08-26 | 2017-01-04 | 上海无线电设备研究所 | High-speed Parallel Signal Processing Systems and processing method thereof |
| CN106291501B (en) * | 2016-08-26 | 2019-01-08 | 上海无线电设备研究所 | High-speed Parallel Signal Processing Systems and its processing method |
| CN109639277A (en) * | 2018-10-31 | 2019-04-16 | 上海无线电设备研究所 | A kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR |
| CN110460337A (en) * | 2019-08-13 | 2019-11-15 | 刘涛 | A kind of high-speed sampling and reconstructing method |
| CN112083674A (en) * | 2020-09-09 | 2020-12-15 | 中国航空工业集团公司雷华电子技术研究所 | FPGA chip data processing method, chip, computer equipment and storage medium |
| CN113114166A (en) * | 2021-03-12 | 2021-07-13 | 成都辰天信息科技有限公司 | High-speed parallel DDC (direct digital control) and FIR (finite impulse response) filtering processing method based on FPGA (field programmable Gate array) |
| CN114567337A (en) * | 2022-01-14 | 2022-05-31 | 西安电子科技大学重庆集成电路创新研究院 | Ultra-wideband transmitter based on FPGA |
| CN114567337B (en) * | 2022-01-14 | 2024-07-02 | 西安电子科技大学重庆集成电路创新研究院 | Ultra-wideband transmitter based on FPGA |
| CN115951105A (en) * | 2023-03-09 | 2023-04-11 | 苏州联讯仪器股份有限公司 | Electric signal sampling channel device and sampling oscilloscope |
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Application publication date: 20150930 |