CN203573128U - FPGA-based multi-channel data acquisition system - Google Patents
FPGA-based multi-channel data acquisition system Download PDFInfo
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- CN203573128U CN203573128U CN201320749018.2U CN201320749018U CN203573128U CN 203573128 U CN203573128 U CN 203573128U CN 201320749018 U CN201320749018 U CN 201320749018U CN 203573128 U CN203573128 U CN 203573128U
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Abstract
The utility model discloses an FPGA-based multi-channel data acquisition system comprising a frequency mixer, a data acquisition card, an FPGA and an upper computer. Signals received by antennas sequentially pass through the frequency mixer and the data acquisition card to be connected with the FPGA. The FPGA is connected with the upper computer through a communication unit. The FPGA includes a main controller, a FIFO module, digital filters, down-sampling filters and the communication unit. A digital signal output by the data acquisition card is connected with the main controller sequentially through the FIFO module, the digital filters and the down-sampling filters. The main controller is connected with the upper computer through the communication unit. Multi-channel synchronous sampling and digital down conversion of immediate-frequency signals can be completed, the complexity of the system is reduced, and the cost of the system is reduced; data transmission is carried out through the Ethernet, which can improve the transmission speed of acquired data; and after data is transmitted to the FPGA, the amount of data and the sampling rate can be effectively reduced, and the complexity of subsequent data processing can be reduced.
Description
Technical field
The utility model relates to a kind of multichannel data acquisition system based on FPGA.
Background technology
In radio communications system, traditional data acquisition is by twice analog down change-over circuit, first signal frequency is transformed into the first intermediate frequency of hundreds of megahertzes from radio frequency, through the second frequency conversion, be transformed into again second intermediate frequency of tens of hertz, then analog quadrature demodulation, finally just carries out A/D sampling.This mode is through twice down coversion before AD sampling, and not only system complex, also needs numerous parts, and cost is high.In addition, because the data transfer rate after AD sampling is often very large, concerning the arbitrary signal gathering, too high sampling rate, can cause in data acquisition separately, processes complexity and strengthens.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, a kind of multichannel data acquisition system based on FPGA that can reduce system complexity, minimizing system cost, improve image data transfer rate is provided, it can complete the multi-channel synchronous of intermediate-freuqncy signal and sample and Digital Down Convert, after data are sent in FPGA, can effectively reduce data volume and sampling rate, reduce the complexity of data subsequent treatment.
The purpose of this utility model is achieved through the following technical solutions: based on the multichannel data acquisition system of FPGA, it comprises frequency mixer, data collecting card, FPGA and host computer, the signal of antenna reception is connected with FPGA with data collecting card through frequency mixer successively, and FPGA is connected with host computer by communication unit;
Described FPGA comprises master controller, fifo module, digital filter, desampling fir filter and communication unit, the digital signal of data collecting card output is connected with master controller with desampling fir filter by fifo module, digital filter successively, and master controller is connected with host computer by communication unit.
Described data collecting card comprises matching network circuit, intermediate frequency receiver and sampling clock module, the intermediate-freuqncy signal of frequency mixer output is connected with intermediate frequency receiver by matching network circuit, sampling clock module is connected with the clock signal input terminal of intermediate frequency receiver, and intermediate frequency receiver is connected with FPGA.
Described communication unit comprises ethernet communication control module and Ethernet interface, and Ethernet interface is connected with master controller by ethernet communication control module.
Described digital filter and desampling fir filter are multiple, and individual digit wave filter connects master controller by the desampling fir filter of answering in contrast.
Described intermediate frequency receiver adopts intermediate frequency diversity receiver.
The beneficial effects of the utility model are: data collecting card comprises intermediate frequency diversity receiver, complete multi-channel synchronous sampling and the Digital Down Convert of intermediate-freuqncy signal, reduce the complexity of system, reduce system cost; In FPGA, be provided with multiple digital filters and desampling fir filter, even if the data transfer rate of intermediate frequency diversity receiver output is larger, also can to data, carry out the processing of shunt digital filtering by FPGA, again each circuit-switched data is carried out to down-sampled processing, reduce data volume and sampling rate, reduce the complexity of follow-up data processing; Adopt Ethernet that the data of collection are sent to host computer, can improve the transfer rate of data.
Accompanying drawing explanation
Fig. 1 is structured flowchart of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail, but protection domain of the present utility model is not limited to the following stated.
As shown in Figure 1, based on the multichannel data acquisition system of FPGA, it comprises frequency mixer, data collecting card, FPGA and host computer, and the signal of antenna reception is connected with FPGA with data collecting card through frequency mixer successively, and FPGA is connected with host computer by communication unit.
Described communication unit comprises ethernet communication control module and Ethernet interface, and Ethernet interface is connected with master controller by ethernet communication control module.
Described FPGA comprises master controller, fifo module, digital filter, desampling fir filter and communication unit, the digital signal of data collecting card output is connected with master controller with desampling fir filter by fifo module, digital filter successively, and master controller is connected with host computer by communication unit.
Described data collecting card comprises matching network circuit, intermediate frequency receiver and sampling clock module, the intermediate-freuqncy signal of frequency mixer output is connected with intermediate frequency receiver by matching network circuit, sampling clock module is connected with the clock signal input terminal of intermediate frequency receiver, and intermediate frequency receiver is connected with FPGA.Matching network circuit, for mating the input impedance of intermediate frequency receiver.Intermediate frequency receiver adopts intermediate frequency diversity receiver, as preferably, adopts AD6655 chip as intermediate frequency receiver.AD6655 chip has the advantages such as highly integrated, function is strong, built-in binary channels, 14, analog to digital converter (ADC) and a wideband digital low-converter (DDC) of 80MS/s, 105 MS/s, 125 MS/s, 150 MS/s, once complete multi-channel synchronous sampling and the Digital Down Convert of intermediate-freuqncy signal, the complexity of reduction system, reduces system cost.
Described digital filter and desampling fir filter are multiple, and individual digit wave filter connects master controller by the desampling fir filter of answering in contrast.The frequency band range of each digital filter is different.
The course of work of the present utility model is as follows: the signal of four antenna receptions obtains intermediate-freuqncy signal after mixing, intermediate frequency receiver AD6655 carries out synchronized sampling and Digital Down Convert to the intermediate-freuqncy signal of input, obtain 4 roadbed band i/q signals, by interface, the data of collection are deposited in the fifo module of FPGA, by FPGA, be further processed.Data after treatment are sent to host computer by Ethernet interface.Because the data transfer rate of intermediate frequency receiver output is often larger, therefore in FPGA, add multiple digital filters, leach respectively each frequency band of the rear signal of sampling, according to data transmission capabilities and need to carry out cut position, export to reduce quantization digit with cut position, again each circuit-switched data after cut position is carried out to down-sampled processing, reduce sampling rate, so just reduced the complexity of data subsequent treatment.
Claims (5)
1. the multichannel data acquisition system based on FPGA, it is characterized in that: it comprises frequency mixer, data collecting card, FPGA and host computer, the signal of antenna reception is connected with FPGA with data collecting card through frequency mixer successively, and FPGA is connected with host computer by communication unit;
Described FPGA comprises master controller, fifo module, digital filter, desampling fir filter and communication unit, the digital signal of data collecting card output is connected with master controller with desampling fir filter by fifo module, digital filter successively, and master controller is connected with host computer by communication unit.
2. the multichannel data acquisition system based on FPGA according to claim 1, it is characterized in that: described data collecting card comprises matching network circuit, intermediate frequency receiver and sampling clock module, the intermediate-freuqncy signal of frequency mixer output is connected with intermediate frequency receiver by matching network circuit, sampling clock module is connected with the clock signal input terminal of intermediate frequency receiver, and intermediate frequency receiver is connected with FPGA.
3. the multichannel data acquisition system based on FPGA according to claim 1, is characterized in that: described communication unit comprises ethernet communication control module and Ethernet interface, and Ethernet interface is connected with master controller by ethernet communication control module.
4. the multichannel data acquisition system based on FPGA according to claim 1, is characterized in that: described digital filter and desampling fir filter are multiple, and individual digit wave filter connects master controller by the desampling fir filter of answering in contrast.
5. the multichannel data acquisition system based on FPGA according to claim 1, is characterized in that: described intermediate frequency receiver adopts intermediate frequency diversity receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320749018.2U CN203573128U (en) | 2013-11-25 | 2013-11-25 | FPGA-based multi-channel data acquisition system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320749018.2U CN203573128U (en) | 2013-11-25 | 2013-11-25 | FPGA-based multi-channel data acquisition system |
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| CN203573128U true CN203573128U (en) | 2014-04-30 |
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| CN201320749018.2U Expired - Lifetime CN203573128U (en) | 2013-11-25 | 2013-11-25 | FPGA-based multi-channel data acquisition system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107294552A (en) * | 2017-06-08 | 2017-10-24 | 上海华测导航技术股份有限公司 | A kind of method that utilization limited resources handle multi-channel data |
| CN114296629A (en) * | 2021-12-28 | 2022-04-08 | 五邑大学 | Signal acquisition method and system |
| CN114487894A (en) * | 2021-12-24 | 2022-05-13 | 中铁二院工程集团有限责任公司 | System for carrying out real-time quality monitoring on vehicle-mounted power supply equipment |
-
2013
- 2013-11-25 CN CN201320749018.2U patent/CN203573128U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107294552A (en) * | 2017-06-08 | 2017-10-24 | 上海华测导航技术股份有限公司 | A kind of method that utilization limited resources handle multi-channel data |
| CN114487894A (en) * | 2021-12-24 | 2022-05-13 | 中铁二院工程集团有限责任公司 | System for carrying out real-time quality monitoring on vehicle-mounted power supply equipment |
| CN114296629A (en) * | 2021-12-28 | 2022-04-08 | 五邑大学 | Signal acquisition method and system |
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Legal Events
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| C14 | Grant of patent or utility model | ||
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Granted publication date: 20140430 |