CN104935295B - The rest-set flip-flop of gallium nitride base low-leakage current clamped beam - Google Patents
The rest-set flip-flop of gallium nitride base low-leakage current clamped beam Download PDFInfo
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- CN104935295B CN104935295B CN201510378510.7A CN201510378510A CN104935295B CN 104935295 B CN104935295 B CN 104935295B CN 201510378510 A CN201510378510 A CN 201510378510A CN 104935295 B CN104935295 B CN 104935295B
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Abstract
The rest-set flip-flop of gallium nitride base low-leakage current clamped beam of the invention is produced on semi-insulating type GaN substrate (1), (11) are switched by four N-type MESFET and two resistance R are constituted, two of which switch is connected in series the first NAND gate of composition (1.), another two switch is connected in series the second NAND gate of composition (2.), wherein the output end of the first NAND gate is connected by wire with an input of the second NAND gate, the output end of same second NAND gate is connected also by wire with an input of the first NAND gate, forms full symmetric structure；It is respectively first input end R and the second input S that rest-set flip-flop has two outer signal inputs, and two output ends are respectively the first output end Q and the second output endN-type MESFET switchs (11) with the clamped beam (4) for suspending, and the two ends of the clamped beam (4) are fixed in anchor area (2), and center section is across in grid (10) top.
Description
Technical field
The present invention proposes the rest-set flip-flop of gallium nitride base low-leakage current clamped beam, belongs to the technology of microelectromechanical systems
Field.
Background technology
In the world today, integrated circuit is in booming period, digital integrated electronic circuit important as its
Point also carry out constantly reform with it is perfect, develop early stage in integrated circuit, people are mostly to make each of MOS device
The circuit structure of various kinds is planted, but by permanent development, it has been found that GaN metals-semiconductor field effect transistor
(MESFET) have that electron mobility is high, carrier drift speed is fast, energy gap is big, capability of resistance to radiation is strong, operating temperature model
Many advantages, such as enclosing width, has obvious advantage, therefore GaN metals-semiconductor field effect transistor than traditional MOS device
(MESFET) it is widely applied in large scale integrated circuit of today by people.But with the gradually contracting of integrated circuit dimensions
Small, integrated level continuous improvement, the MESFET devices of traditional structure also show various problems successively, wherein main
Problem be exactly power consumption, typical example is exactly rest-set flip-flop, has four MESFET types to switch in rest-set flip-flop, traditional
There is the leakage current that can not ignore in MESFET switches, the DC power that result in MESFET switches is larger due to its grid, so that
So that the power consumption of whole rest-set flip-flop is also excessive, if by the larger rest-set flip-flop of this DC power be applied to integrated level it is high be
In system, unthinkable consequence can be caused, therefore how to reduce the power consumption of rest-set flip-flop into a great problem.
With continuing to develop for MEMS technology, a kind of MESFET switches with MEMS fixed beam structures can be solved effectively
The certainly problem of grid leakage current, therefore the present invention devises a kind of gate leakage with very little in semi-insulating type GaN substrate
The rest-set flip-flop of the clamped beam type of electric current.
The content of the invention
Technical problem：It is an object of the invention to provide the rest-set flip-flop and system of a kind of gallium nitride base low-leakage current clamped beam
Preparation Method, because the grid of traditional MESFET devices is contacted with raceway groove and produces Schottky barrier, so inevitably
Gate leakage current is produced, so as to the DC power that result in whole rest-set flip-flop is larger, and the present invention is with regard to extremely effective drop
Grid leakage current in low rest-set flip-flop, such that it is able to reduce the DC power of rest-set flip-flop.
Technical scheme：The rest-set flip-flop of gallium nitride base low-leakage current clamped beam of the invention is produced on semi-insulating type GaN linings
On bottom, be made up of four N-type MESFET switch and two resistance R, N-type MESFET switch include source electrode, drain electrode, grid and
Raceway groove is constituted, and two of which N-type MESFET switches are connected in series the first NAND gate of composition, another two N-type MESFET switch series connection
Connection the second NAND gate of composition, wherein the output end of the first NAND gate passes through an input phase of wire and the second NAND gate
Connect, the output end of same second NAND gate is connected also by wire with an input of the first NAND gate, it is completely right to be formed
The structure of title；It is respectively first input end R and the second input S that rest-set flip-flop has two outer signal inputs, and two
Output end is respectively the first output end Q and the second output endN-type MESFET switches have the clamped beam for suspending, the clamped beam
Two ends be fixed in anchor area, across above grid, there is a gap between grid, clamped beam is by Au material systems for center section
Make, two pull-down electrodes are additionally provided with below clamped beam, pull-down electrode is ground connection, and silicon nitride medium is also covered with thereon
Layer, this structure can greatly reduce gate leakage current, so as to reduce the power consumption of device.
The threshold voltage designs of four N-type MESFET switches are equal, and the actuation voltage of clamped beam is designed as and N
The threshold voltage of type MESFET is equal；Only when the voltage between clamped beam and pull-down electrode is more than threshold voltage, suspension
Clamped beam drop-down can be just labelled to and N-channel MESFET conductings are caused on grid, and offset signal is connected on grid by clamped beam, otherwise
N-channel MESFET just ends.
When R ends and S ends are all high level, the clamped beam 4 of the N-type MESFET being connected with this two ends drop-down can lead it
It is logical, but two input signals to output Q andDo not have an impact, by Q andThe N-type MESFET for being controlled is in original shape
State, so flip-flop states keep constant；When R ends be high level, S ends be low level when, the N-type MESFET being connected with R ends leads
The logical N-type MESFET cut-offs being connected with S ends, thereforeIt is high level, withThe connected N-type MESFET conductings in end, then Q is defeated
Go out low level, now flip-flop states stabilize to low level；When R ends be low level, S ends be high level when, the N being connected with R ends
The N-type MESFET conductings that type MESFET cut-offs are connected with S ends, therefore Q is high level, the N-type MESFET conductings being connected with Q ends,
ThenLow level is exported, now flip-flop states stabilize to high level；When R ends and S ends are all low level, with this two ends phase
N-type MESFET all end, therefore Q withAll it is high level, at this moment rest-set flip-flop is in neither 1 non-zero uncertain shape again
State, therefore to make rest-set flip-flop normal work, input signal have to comply with the constraints of R+S=1, i.e., not allow R=S=
0。
Beneficial effect：The rest-set flip-flop of gallium nitride base low-leakage current clamped beam of the invention has the clamped beam knot for suspending
There is one layer of space between structure, with grid, therefore can greatly reduce grid leakage current, so as to reduce whole rest-set flip-flop
DC power, improves the stability of system.
Brief description of the drawings
Fig. 1 is the rest-set flip-flop schematic diagram of gallium nitride base low-leakage current clamped beam of the invention,
Fig. 2 is the inside schematic diagram of the rest-set flip-flop of gallium nitride base low-leakage current clamped beam of the invention,
Fig. 3 is the top view of the rest-set flip-flop of gallium nitride base low-leakage current clamped beam of the invention,
Fig. 4 for Fig. 3 gallium nitride base low-leakage current clamped beams rest-set flip-flop P-P ' to profile,
Fig. 5 for Fig. 3 gallium nitride base low-leakage current clamped beams rest-set flip-flop A-A ' to profile.
Figure includes：Semi-insulating type GaN substrate 1, anchor area 2, N-type MESFET raceway grooves 3, clamped beam 4, pull-down electrode 5, nitridation
Silicon dielectric layer 6, source electrode 7, drain electrode 8, lead 9, grid 10, N-type MESFET switches 11, resistance R.
Specific embodiment
The rest-set flip-flop of gallium nitride base low-leakage current clamped beam of the invention is made based on semi-insulating type GaN substrate 1,
Wherein N-type MESFET switches 11 are made up of source electrode 7, drain electrode 8, anchor area 2, clamped beam 4, pull-down electrode 5 and silicon nitride medium 6,
It possesses the MEMS fixed beam structures of uniqueness, and the clamped beam 4 is across in the top of grid 10, and the clamped beam is by Au material systems
Make, there are two pull-down electrodes below clamped beam, the pull-down electrode is ground connection, and silicon nitride medium is coated with pull-down electrode
Layer, control signal is attached on the clamped beam, and is not to be loaded directly on grid.
The rest-set flip-flop of gallium nitride base low-leakage current clamped beam of the invention is mainly what is be made up of two NAND gates, wherein
First NAND gate output end Q and a second NAND gate 1. input 2. is connected, and the second NAND gate output end 2.
It is connected with the first NAND gate input 1., the first NAND gate another input 1. is R ends (clear terminal), and second
NAND gate another input 2. is S ends (set end).The internal structure of the two NAND gates is the same, be all by
Two N-type MESFET and a pull-up resistor R are connected in series what is constituted, and some work is taken between N-type MESFET and resistance
It is output end, so whole rest-set flip-flop has altogether possesses four N-type MESFET switches.
Whole rest-set flip-flop is made based on semi-insulating type GaN substrate, wherein the most key is exactly four N-types
The structure of MESFET switches, they are made up of source electrode, drain electrode, grid and raceway groove, and the source electrode of MESFET and drain electrode are by gold and N-type weight
The ohmic contact regions that doped region is formed are constituted, and grid is that the Schottky contact region formed by gold and raceway groove is constituted, even more important
It is that N-type MESFET possesses unique MEMS fixed beam structures, by anchor area across on grid, there is one layer between grid
Space, control signal is attached on the clamped beam, and is not to be loaded directly into grid as traditional MESFET devices
On, the clamped beam is made by Au materials, there is two pull-down electrodes below clamped beam, is distributed between anchor area and grid, under this
Pulling electrode is ground connection, and silicon nitride medium layer is coated with pull-down electrode.
From the point of view of single NAND gate, when all high level ' 1 ' is loaded with two clamped beams of N-type MESFET, due under
Pulling electrode is grounded, so that the suspension clamped beam of N-type MESFET is pulled down electrode adsorption and is labelled to the grid above N-type channel
On, now two N-type MESFET are both turned on, and then whole circuit forms path, and output end is caused because the partial pressure of resistance R is acted on
It is low level ' 0 '；When loading consolidating for high level ' 1 ' and another N-type MESFET on the clamped beam of one of N-type MESFET
When loading low level ' 0 ' on strutbeam so that a N-type MESFET conducting, another N-type MESFET cut-offs, whole circuit does not have
Path is formed, so output end is high level ' 1 '；When all low level ' 0 ' is loaded with two clamped beams of N-type MESFET,
Two suspension clamped beams of N-type MESFET are all without being pulled down so that two N-type MESFET are off state, whole circuit
Path is not formed, so output end is high level ' 1 ', this is the operation principle of single NAND gate.Triggered from whole RS again
From the point of view of device, when R ends and S ends all be high level ' 1 ' when, two input signals to output Q andWithout influence, so flip-flop states
Keep constant；When R ends be high level ' 1 ', S ends be low level ' 0 ' when, output end Q be low level ' 0 ',It is high level ' 1 ',
Now flip-flop states are low level ' 0 '；When R ends are low level ' 0 ', and S ends are high level ' 1 ', output end Q is high level
‘1’、It is low level ' 0 ', now flip-flop states are high level ' 1 '；When R ends and S ends are all low level ' 0 ', Q ends are obtained
WithEnd output is all high level ' 1 ', and at this moment trigger is in neither 1 non-zero nondeterministic statement again, therefore to make trigger
Normal work, input signal has to comply with the constraints of R+S=1, i.e., do not allow R=S=0.
The preparation method of the rest-set flip-flop of gallium nitride base low-leakage current clamped beam of the invention is：
1) semi-insulating type GaN substrate 1 is prepared；
2) one layer of silicon nitride, photoetching and etch silicon nitride, the silicon nitride of removal N-type MESFET channel regions 3 are deposited；
3) N-type MESFET Channeling implantations：Injection phosphorus, anneals in a nitrogen environment；After the completion of annealing, carry out at high temperature miscellaneous
Matter is redistributed, and forms the raceway groove 3 of N-type MESFET；
4) silicon nitride layer is removed：Silicon nitride is all removed using dry etching technology；
5) photoetched grid 10, remove the photoresist in grid region；
6) electron beam evaporation titanium/platinum/gold；
7) titanium/platinum/gold on remaining photoresist and photoresist is removed；
8) heat, titanium/platinum/billon is formed Schottky contacts with N-type MESFET raceway grooves 3；
9) photoresist is coated, photoetching simultaneously etches N-type MESFET source electrodes 7 and the photoresist in 8 regions that drain；
10) N-type heavy doping is carried out to the region, in the N-type heavy doping that N-type MESFET source electrodes 7 and 8 regions of drain electrode are formed
Area, carries out short annealing treatment；
11) photoresist of photoetching source electrode 7 and drain electrode 8, removal source electrode 7 and drain electrode 8；
12) it is evaporated in vacuo gold germanium ni au；
13) the gold germanium ni au on photoresist and photoresist is removed；
14) alloying forms Ohmic contact, forms source electrode 7 and drain electrode 8；
15) photoresist, the photoresist of the position of anchor area 2 of removal lead 9, pull-down electrode 5 and clamped beam are coated；
16) evaporation ground floor gold, its thickness is about 0.3 μm；
17) gold on photoresist and photoresist is removed, the anchor area 2 of lead 9, pull-down electrode 5 and clamped beam is formed；
18) one layer is depositedThick silicon nitride；
19) photoetching and etch nitride silicon dielectric layer, are retained in the silicon nitride medium layer 6 in pull-down electrode；
20) deposit and photoetching polyimide sacrificial layer：The polyimide sacrificial layer of 1.6 μ m-thicks is coated in GaN substrate 1,
It is required that filling up pit；Photoetching polyimide sacrificial layer, only retains the sacrifice layer of the lower section of clamped beam 4；
21) titanium/gold/titanium is evaporated, its thickness is
22) photoetching：Removal will electroplate the photoresist in place；
23) gold is electroplated, its thickness is 2 μm；
24) photoresist is removed：Removal need not electroplate the photoresist in place；
25) titanium/gold/titanium is anti-carved, corrodes down payment, form MEMS clamped beams 4；
26) polyimide sacrificial layer is discharged：Developer solution soaks, the polyimide sacrificial layer under removal clamped beam 4, deionization
Water soaks slightly, absolute ethyl alcohol dehydration, is volatilized under normal temperature, dries.
Present invention be distinguished in that：
Four switches for constituting rest-set flip-flop are made up of the N-type MESFET with fixed beam structure, and the clamped beam passes through
Anchor area is provided with two pull-down electrodes across above grid, there is one layer of space between grid below clamped beam, the drop-down electricity
Pole is ground connection, and two threshold voltage designs of N-type MESFET are equal, and the actuation voltage of clamped beam is designed as and N-type
The threshold voltage of MESFET is equal.When the voltage between clamped beam and pull-down electrode is more than threshold voltage, the drop-down patch of clamped beam
To grid, so that N-type MESFET is turned on, otherwise N-type MESFET cut-offs, due to the presence of the clamped beam of N-type MESFET,
So that grid leakage current is substantially reduced, DC power also further reduces.
The structure for meeting conditions above is considered as the rest-set flip-flop of gallium nitride base low-leakage current clamped beam of the invention.
The symbol and truth table of the rest-set flip-flop in Fig. 1 are as follows：
Claims (2)
1. a kind of rest-set flip-flop of gallium nitride base low-leakage current clamped beam, it is characterised in that the rest-set flip-flop is produced on semi-insulating type
GaN substrate（1）On, switched by four N-type MESFET（11）Constituted with two resistance R, N-type MESFET switches（11）Bag
Include source electrode, drain electrode, grid and raceway groove composition, two of which N-type MESFET switches（11）It is connected in series the first NAND gate of composition
（①）, another two N-type MESFET switches（11）It is connected in series the second NAND gate of composition（②）, wherein the first NAND gate（①）'s
Output end passes through wire and the second NAND gate（②）An input connect, same second NAND gate（②）Output end also lead to
Cross wire and the first NAND gate（①）An input be connected, form full symmetric structure；Rest-set flip-flop has outside two
It is respectively first input end R and the second input S to connect signal input part, and two output ends be respectively the first output end Q and
Second output end ；N-type MESFET is switched（11）With the clamped beam for suspending（4）, the clamped beam（4）Two ends be fixed on anchor area
（2）On, center section is across in grid（10）Top, with grid（10）Between have a gap, clamped beam（4）Made by Au materials
, in clamped beam（4）Lower section is additionally provided with two pull-down electrodes（5）, pull-down electrode（5）It is ground connection, pull-down electrode（5）On also cover
It is stamped silicon nitride medium layer（6）, this structure can greatly reduce gate leakage current, so as to reduce the power consumption of device.
2. the rest-set flip-flop of gallium nitride base low-leakage current clamped beam according to claim 1, it is characterised in that described four
N-type MESFET is switched（11）Threshold voltage designs for equal, and clamped beam（4）Actuation voltage be designed as and N-type MESFET
Switch（11）Threshold voltage it is equal；Only work as clamped beam（4）With pull-down electrode（5）Between voltage be more than threshold voltage when,
The clamped beam of suspension（4）Just drop-down can be labelled to grid（10）It is upper to cause N-type MESFET switches（11）Conducting, offset signal is by solid
Strutbeam（4）It is connected to grid（10）On, otherwise N-type MESFET switches（11）Just end.
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| CN1433076A (en) * | 2002-01-15 | 2003-07-30 | 松下电器产业株式会社 | Level shift circuit |
| US6960946B2 (en) * | 2003-10-09 | 2005-11-01 | Texas Instruments Incorporated | Low power, up full swing voltage CMOS bus receiver |
| CN101777907A (en) * | 2009-12-31 | 2010-07-14 | 宁波大学 | Low-power dissipation RS latch unit and low-power dissipation master-slave D flip-flop |
| CN102306924A (en) * | 2011-09-14 | 2012-01-04 | 黄华道 | Leakage detecting protection circuit capable of periodically automatically detecting function integrity |
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2015
- 2015-07-01 CN CN201510378510.7A patent/CN104935295B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433076A (en) * | 2002-01-15 | 2003-07-30 | 松下电器产业株式会社 | Level shift circuit |
| US6960946B2 (en) * | 2003-10-09 | 2005-11-01 | Texas Instruments Incorporated | Low power, up full swing voltage CMOS bus receiver |
| CN101777907A (en) * | 2009-12-31 | 2010-07-14 | 宁波大学 | Low-power dissipation RS latch unit and low-power dissipation master-slave D flip-flop |
| CN102306924A (en) * | 2011-09-14 | 2012-01-04 | 黄华道 | Leakage detecting protection circuit capable of periodically automatically detecting function integrity |
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