CN103811336A - IGBT (Insulated Gate Bipolar Translator) power device applied at low power and manufacturing method thereof - Google Patents

IGBT (Insulated Gate Bipolar Translator) power device applied at low power and manufacturing method thereof Download PDF

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CN103811336A
CN103811336A CN201410059061.5A CN201410059061A CN103811336A CN 103811336 A CN103811336 A CN 103811336A CN 201410059061 A CN201410059061 A CN 201410059061A CN 103811336 A CN103811336 A CN 103811336A
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groove
carried out
igbt
silicon substrate
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CN103811336B (en
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方伟
周仲建
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ARK MICROELECTRONICS Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

The invention discloses an IGBT (Insulated Gate Bipolar Translator) power device applied at low power and a manufacturing method thereof. The method comprises the following steps: performing semiconductor impurity injection or diffusion operation on the front side of a silicon substrate; performing corroding treatment on the front side which is subjected to the semiconductor impurity injection or diffusion operation; performing P type ion injection on the back side of the silicon substrate to form a P region; forming a groove on the back side of the silicon substrate; performing N type ion injection on the surface of the groove to form an N region; performing diffusion operation on the P region and the N region; performing an outer layer encapsulating treatment on the silicon substrate. The method has the advantages that by means of groove formation, P type ion injection and N type ion injection on the surface of the groove under the condition of not influencing the voltage endurance capability of the device, the switch-on/off time of a low-voltage IGBT can be prolonged respectively, extremely low startup voltage drop and rapid reverse switch-off recovery are realized.

Description

IGBT power device and the manufacture method thereof of low power applications
Technical field
The invention belongs to semiconductor power electronic device manufacturing technology field, especially, relate to a kind of manufacture method of IGBT power device of low power applications.
Background technology
IGBT(Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) be the multiple device of bipolar transistor and power MOSFET, its structure can be equivalent to the combination of a MOS and two bipolar transistors, in the time of normal work, and substrate P +connect positive potential, be called the anode of IGBT, surperficial N -contact layer connects negative or zero potential conventionally, is called the negative electrode of IGBT, the grid that the electrode of drawing by gate medium is IGBT.IGBT is because its characteristic is obviously better than bipolar transistor and power MOSFET, therefore, since coming out, being widely used in multiple fields such as Electric Machine Control, industrial speed governing, household electrical appliance, illumination, network service, computer, automotive electronics, Aero-Space and national defense construction, is the basic core devices of modern power electronics technology.
Along with the development of power semiconductor, people have higher requirement to the performance of IGBT, for example, publication number be CN1790737A Patent Application Publication a kind of IGBT and manufacture method thereof, this IGBT is driven the bipolar tube of a NPN or PNP by NMOS pipe, used vertical MOS pipe in the structure of this device; Its manufacture method comprises: N grows on P type silicon chip -extension, trench lithography, etching are to form grid, and quarter is returned in polysilicon deposit, and trap injects diffusion, source region photoetching, diffusion is injected in source, and contact hole forms, metal level deposit, photoetching, etching, and the metallization of silicon chip back side attenuate.In addition, prior art is not only embodied in and will keeps its advantage at the low conduction loss in high-power field the requirement of IGBT, also to improve the application power in IGBT low-power field in low pressure simultaneously, require it under the operating state lower than 600V, also can realize speed-sensitive switch, the ability to work of high reliability and miniaturization low-power consumption.This is the limit of its application in the past for IGBT, because well-known, it is mutual balance that low conduction loss and at a high speed unlatching are turn-offed, and the two can only obtain one or go to realize better compromise.In low power applications, the advantage of power MOSFET is more obvious, its quick channel current having opens and turn-off characteristic can mate low pressure high-frequency circuit preferably, if turn-off feature but IGBT also can possess the quick unlatching of above MOSFET, will cause again a semiconductor device revolution.So the IGBT that realizes low pressure high frequency is a large difficult point, this is also the focus of studying in the world at present.
Summary of the invention
For above-mentioned deficiency, technical problem to be solved by this invention is the manufacture method of the IGBT power device that a kind of low power applications is provided, and it can improve unlatching and the turn-off time of low pressure IGBT.
Technical scheme of the present invention is achieved in that a kind of manufacture method of IGBT power device of low power applications, it is characterized in that, comprising: semiconductor impurities injection or dispersion operation are carried out in the front of silicon substrate; Corrosion treatment is carried out in the front of carrying out after semiconductor impurities injection or dispersion operation; P type Implantation is carried out in the back side of silicon substrate, form P region; The back side to silicon substrate arranges groove; Flute surfaces is carried out to N-type Implantation, form n-quadrant; Dispersion operation is carried out in described P region and n-quadrant; Silicon substrate is carried out to outer encapsulation process.
Can find out by technique scheme, the invention has the beneficial effects as follows:
On the one hand, in the situation that not affecting the voltage endurance capability of device own, pass through to increase groove, P type Implantation and the N-type Implantation only carrying out in flute surfaces, can improve unlatching and the turn-off time of low pressure IGBT, in open stage, due to the filling increasing the groove structure of metal replaced the part P type ion heavily doped region that drains, make the region in IGBT with this slot type structure become MOSFET; After top channel is opened, portions of electronics can arrive rapidly the heavy doping N-type ion region of flute surfaces, generation current, thereby omit the diode cut-in voltage of drain electrode P type ion heavily doped region and the formation of substrate base, the unlatching that makes IGBT has been become to same MOSFET equally quick, had voltage just to have electric current, and, in the time that drain electrode has forward voltage drop, source electrode also can be upwards gone in the hole that bottom produces, with the same conductivity modulation effect that produces in substrate base of common IGBT.
On the other hand, the P type Implantation at the back side and the N-type Implantation only carrying out in flute surfaces, also can improve the turn-off time of low pressure IGBT, in off-phases, its depletion region is expanded in P-region downwards, electrons flows to drain electrode rapidly downwards, and owing to injecting heavy doping N-type ion region in the surface of the trench region increasing, make the hole of substrate base no longer mainly by disappearing with remaining electron recombination, but go to rapidly the heavy doping N-type ion region of the shorter flute surfaces in path to carry out compound disappearance, that is to say, the heavy doping N-type ion region that the flute surfaces at the back side is injected is equivalent to a complex centre in the thin slice IGBT of low pressure applications body, due to be compounded with turn-off time minority carrier, turn-off speed is accelerated greatly.
Accompanying drawing explanation
In order more clearly to describe related art scheme involved in the present invention, the accompanying drawing being related to below gives simple declaration, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the internal structure schematic diagram of the embodiment product of the IGBT power device of low power applications of the present invention;
Fig. 2 is the specific embodiment structural representation of the IGBT power device of low power applications of the present invention;
Fig. 3 is another specific embodiment structural representation of the IGBT power device of low power applications of the present invention;
Fig. 4 is the FB(flow block) of the manufacture method of the IGBT power device of low power applications of the present invention;
Fig. 5 is the process flow diagram of the embodiment of method shown in Fig. 3;
Fig. 6 is the manufacturing process flow diagram of the embodiment of the present invention.
Each Reference numeral signal in figure:
1-back of the body gold layer, 2-heavy doping P+ region, 3-groove
7-N+ region, 5-N-substrate layer, 6-P-region, 4-heavy doping N+ region
8-silicon dioxide gate oxide, 9-polycrystalline silicon grid layer, 10-bpsg layer
13-back side, 11-metal surface, 12-P+ region, 14-photoresist.
Embodiment
For the ease of those skilled in the art's a further understanding of the present invention, clearly be familiar with technical scheme of the present invention, complete, correlation technique content of the present invention disclosed fully, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail, certainly, described embodiment has only been enumerated the present invention's part embodiment, rather than whole embodiment, for helping to understand the present invention and core concept thereof.
Basic ideas of the present invention are to be optimized design by the structure to IGBT, in the situation that not affecting the voltage endurance capability of device own, fill the groove of metal by increase, heavy doping P type, and the N-type region of only injecting in flute surfaces (particularly groove trench bottom), described N-type region also can be set to the arrangement of recurrence interval formula, unlatching and the turn-off time of improving respectively low pressure IGBT, below provide specific description.
In Fig. 1, the IGBT power device of low power applications of the present invention is mainly by N-substrate layer 5, P-region 6, N+ region 7, silicon dioxide gate oxide 8, polycrystalline silicon grid layer 9, bpsg layer 10, metal surface 11 and P+ region 12, and be positioned at back of the body gold layer 1, heavy doping P+ region 2, the groove 3 at the device back side, the heavy doping N+ region 4 that is positioned at flute surfaces forms.Source region, by the P-region 6 that is positioned at deep layer, is positioned at middle P+ region, top layer 12 and forms with the annular N+ region 7 that is positioned at periphery, P+ region.
Preferably, boron-phosphorosilicate glass bpsg layer 10 can be filled the post of grid source separator, and in specific embodiment, bpsg layer 10 also can be combined to form grid source separator with silicon dioxide layer.The doped source of bpsg layer 10 when generating N+ region 7 in source region, waits processing by annealing, and semiconductor impurities is spread in the silicon in the annular region in predetermined N+ region 7, forms annular N+ region 7.
Fig. 2 is the specific embodiment structural representation of the IGBT power device of low power applications of the present invention, as shown in the figure, has the repeated arrangement structure of groove 3 described at least one, has heavy doping N+ region on the surface of each groove.In specific embodiment, repeated arrangement structure example increases the quantity of groove 3 in this way, refers to the Distance Shortened between groove 3, just can have more groove like this in same area situation, and improving frequency effect also can be more obvious.
Fig. 3 is another specific embodiment structural representation of the IGBT power device of low power applications of the present invention, as shown in the figure, has the structure that is spaced of groove 3 described at least one, has heavy doping N+ region on the surface of each groove.In specific embodiment, be spaced structure example as referred in the time increasing the quantity of groove, top that can a groove has N+ to inject, and the top of a groove does not have, and the structure being distributed in distance is less on the impact of number of cavities below.
In addition, by the Distance Shortened between groove, just can have more groove like this in same area situation, improving frequency effect also can be more obvious.Interval shallow slot pattern, reduces the impact of number of cavities below.
Fig. 4 is the FB(flow block) of the manufacture method of the IGBT power device of low power applications of the present invention, as shown in the figure, comprising: semiconductor impurities injection or dispersion operation are carried out in the front of silicon substrate; Corrosion treatment is carried out in the front of carrying out after semiconductor impurities injection or dispersion operation; P type Implantation is carried out in the back side of silicon substrate, form P region; The back side to silicon substrate arranges groove; Flute surfaces is carried out to N-type Implantation, form n-quadrant; Dispersion operation is carried out in described P region and n-quadrant; Silicon substrate is carried out to outer encapsulation process.
With reference to Fig. 5, described carry out corrosion treatment and further comprise carrying out front after semiconductor impurities injection or dispersion operation: carry out successively oxide layer corrosion, gate oxidation, polycrystalline spatters to amass with the diffusion of burn into source, contact hole corrosion and metal and passivation layer and spatters long-pending processing.After processing, form positive metal level, preferably, positive metal level is aluminium lamination.
The described back side to silicon substrate arranges groove and further comprises: the back side of silicon substrate is carried out to the deposit of photoresist, mask exposure and development are to form preparation etching groove region; Dry etching is carried out in described preparation etching groove region, to form described groove.
Known, the side contacting due to molecule or atom be do not stop transport moving, thereby formation diffusion phenomena, diffusion phenomena under normal temperature normally more slowly, at short notice dispersion operation is carried out in described P region and n-quadrant for convenient, may further include: by the degree of depth of P region described in heating operation control and n-quadrant diffusion layer, the degree of depth of described P region and the diffusion layer of n-quadrant is by determining temperature and the heating time of heating operation, and the impurity of doping can be activated in diffusion process.
Described silicon substrate is carried out to outer encapsulation process further comprise substrate layer is ground or polishing successively, and metal level spatters long-pending, alloy operation, form back of the body gold layer.Preferably, back of the body gold layer is titanium, nickel, or silver back of the body gold layer.
Fig. 6 is the manufacturing process flow diagram of the embodiment of the present invention, as shown in the figure, after the Facad structure of IGBT completes, carries out successively:
N-substrate layer 5 attenuates are carried out in the back side, then carry out heavy doping P+ injection, form P district (after this forming heavy doping P+ region 2).Now do not carry out activation heat process, the P+ knot after injection is very shallow.
Carry out the deposit of photoresist 14, mask exposure and development, form preparation etching groove region.
Dry etching is carried out in the back side and form groove 3, then on groove 3 surfaces, (particularly groove 3 bottom land surfaces) carry out heavy doping N+ injection, form N district (after this forming heavy doping N+ region 4).Now thermal process activation technology is not all also carried out in the N+ region 52 of P district and flute surfaces (particularly trench bottom), all belongs to shallow junction.Preferably, described groove 3 is shallow trench structure, and the degree of depth h of described groove 3 and Si-Substrate Thickness D meet relation: 0.05≤h/ d≤ 0.2, preferably, the degree of depth h of described groove 3 is 1/10th left and right of substrate silicon substrate thickness D, and for example, in the time that bulk silicon substrate thickness D is the low pressure IGBT of 100 μ m, the degree of depth h of described groove 3 is 10 μ m left and right.
N district to described P district and flute surfaces carries out heating operation, and the charge carrier injecting is activated, and shallow junction becomes dark knot, forms respectively heavy doping P+ region 2, heavy doping N+ region 4.Preferably, by the degree of depth of P region described in heating operation control and n-quadrant diffusion layer, the degree of depth of described P region and the diffusion layer of n-quadrant is by determining temperature and the heating time of heating operation, and the impurity of doping can be activated in diffusion process.Complete afterwards the deposit of back of the body gold layer 1.
The structure of MOSFET that the manufacture method of the IGBT power device of low power applications of the present invention has made IGBT Binding in vivo, charge carrier complex centre in IGBT body is also provided, improve respectively the time of open stage and off-phases, cut-in voltage is lower than 1V, oppositely the turn-off time can be low to moderate for tens nanoseconds, the high frequency demand while having mated low pressure applications.The present invention can reach extremely low unlatching pressure drop, oppositely turn-offs recovery time fast, realize better forward conduction voltage drop and withstand voltage between compromise.Along with the development of semiconductor technology, adopt the present invention can also make the more low energy-consumption electronic device of multi-series.
In implementation process, can as the case may be, in the situation that basic structure is constant, carry out certain accommodation design.For example: increase the quantity of shallow slot structure thereby reduce live width, change the design of reticle pattern, injection zone in N+ region etc. in the shallow slot of interval, its optimal design all belongs to the scope of the invention.
Operation principle is: in the situation that not affecting the voltage endurance capability of device own, pass through to increase groove, P type Implantation and the N-type Implantation only carrying out in flute surfaces, the covert combined-flow outbound path that a holoe carrier in the time that IGBT turn-offs is provided, and reduced its path, improve turn-off speed.Meanwhile, inject N+ type knot in trench area, make the unlatching of IGBT become quick unlatching, have voltage just to have the open mode of electric current.Thereby can improve unlatching and the turn-off time of low pressure IGBT.
In open stage, due to the filling increasing the groove structure of metal replaced the part P type ion heavily doped region that drains, make the region in IGBT with this slot type structure become MOSFET; After top channel is opened, portions of electronics can arrive rapidly the heavy doping N-type ion region of flute surfaces, generation current, thereby omit the diode cut-in voltage of drain electrode P type ion heavily doped region and the formation of substrate base, the unlatching that makes IGBT has been become to same MOSFET equally quick, had voltage just to have electric current, and, in the time that drain electrode has forward voltage drop, source electrode also can be upwards gone in the hole that bottom produces, with the same conductivity modulation effect that produces in substrate base of common IGBT.
In off-phases, the P type Implantation at the back side and the N-type Implantation only carrying out in flute surfaces, also can improve the turn-off time of low pressure IGBT, its depletion region is expanded in P-region downwards, electrons flows to drain electrode rapidly downwards, and owing to injecting heavy doping N-type ion region in the surface of the trench region increasing, make the hole of substrate base no longer mainly by disappearing with remaining electron recombination, but go to rapidly the heavy doping N-type ion region of the shorter flute surfaces in path to carry out compound disappearance, that is to say, the heavy doping N-type ion region that the flute surfaces at the back side is injected is equivalent to a complex centre in the thin slice IGBT of low pressure applications body, due to be compounded with turn-off time minority carrier, turn-off speed is accelerated greatly.
In sum, the structure that improves IGBT operating frequency in low pressure applications field provided by the invention, because heavy doping P+ injection is carried out at the back side, be provided with groove 3, and heavy doping N+ injection is carried out on the top of groove 3, and make described P district and N district deepen knot by shallow junction by activation, thereby make IGBT Binding in vivo the structure of MOSFET, charge carrier complex centre in IGBT body is provided, improve respectively the time of open stage and off-phases, in specific embodiment, cut-in voltage is lower than 1V, oppositely the turn-off time can be low to moderate for tens nanoseconds, high frequency demand while having mated low pressure applications.Certainly, also can adopt and only offer overleaf groove or only add impurity and realize.
Based on the embodiment in the present invention; those of ordinary skills are not making all other embodiment that obtain under creative work prerequisite; and/or in the situation that not deviating from spirit of the present invention and essence thereof; even if the execution sequence to each step changes; and make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the scope of protection of the invention.

Claims (10)

1. a manufacture method for the IGBT power device of low power applications, is characterized in that, comprising:
Semiconductor impurities injection or dispersion operation are carried out in the front of silicon substrate;
Corrosion treatment is carried out in the front of carrying out after semiconductor impurities injection or dispersion operation;
P type Implantation is carried out in the back side of silicon substrate, form P region;
The back side to silicon substrate arranges groove;
Flute surfaces is carried out to N-type Implantation, form n-quadrant;
Dispersion operation is carried out in described P region and n-quadrant;
Silicon substrate is carried out to outer encapsulation process.
2. the method for claim 1, is characterized in that, described carry out corrosion treatment and further comprises carrying out front after semiconductor impurities injection or dispersion operation:
Carry out successively oxide layer corrosion, gate oxidation, polycrystalline spatters to amass with the diffusion of burn into source, contact hole corrosion and metal and passivation layer and spatters long-pending processing.
3. method as claimed in claim 2, is characterized in that, the described back side to silicon substrate arranges groove and further comprises:
The back side of silicon substrate is carried out to the deposit of photoresist, mask exposure and development are to form preparation etching groove region;
Dry etching is carried out in described preparation etching groove region, to form described groove.
4. method as claimed in claim 3, is characterized in that, dispersion operation is carried out in described P region and n-quadrant and further comprise: by the diffusion layer degree of depth of P region described in heating operation control and n-quadrant.
5. as the method as described in any one in claim 4, it is characterized in that: the degree of depth of described P region and the diffusion layer of n-quadrant is by determining temperature and the heating time of heating operation.
6. method as claimed in claim 5, is characterized in that, described silicon substrate is carried out to outer encapsulation process further comprise substrate layer is ground or polishing successively, and metal level spatters long-pending, alloy operation, forms back of the body gold layer.
7. method as claimed in claim 6, is characterized in that, described back of the body gold layer is titanium, nickel, or silver back of the body gold layer.
8. employing, as an IGBT power device for the low power applications that in claim 1 to 7, the method as described in any one is manufactured, arranges groove at the described device back side; Show to be built with heavy doping N+ region at described groove.
9. the IGBT power device of low power applications as claimed in claim 8, is characterized in that, has the repeated arrangement structure of groove described at least one, or has the structure that is spaced of groove described at least one.
10. the IGBT power device of low power applications as claimed in claim 8, is characterized in that: described groove is shallow trench, and the degree of depth h of described groove 3 and described Si-Substrate Thickness D meet relation: 0.05≤h/ d≤ 0.2.
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CN113903814A (en) * 2021-12-13 2022-01-07 浙江大学杭州国际科创中心 Fast turn-on diode and manufacturing method

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Publication number Priority date Publication date Assignee Title
CN108417545A (en) * 2018-05-14 2018-08-17 深圳市欧科力科技有限公司 A kind of power device and preparation method thereof
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CN113903814A (en) * 2021-12-13 2022-01-07 浙江大学杭州国际科创中心 Fast turn-on diode and manufacturing method

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