CN103618455A - Method for reducing steady state error of output voltage of single-inductor double-output converter and circuit - Google Patents
Method for reducing steady state error of output voltage of single-inductor double-output converter and circuit Download PDFInfo
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Abstract
The invention discloses a method for reducing a steady state error of output voltage of a single-inductor double-output converter. When high-capacitance-free compensation is adopted for a main loop error amplifier, a current sampling and holding circuit is additionally arranged in a main loop, direct current level Vdc output by the current sampling and holding circuit is superimposed and summated with ramp voltage Vramp1 to generate new ramp voltage Vramp2, the ramp voltage Vramp2 is superimposed and summated with a sampled inductive current signal to generate the input voltage Vsense of the in-phase input end of a comparator, direct current level Vdc0 is simultaneously superimposed with the output Vc of the error amplifier to obtain an inverting input signal Ve of the comparator, Ve is another input signal of the current sampling and holding circuit, and sufficient charging time can be provided for an inductor of the converter by a primary switching control signal output by the comparator, so that the steady state error of the output voltage of the converter is reduced.
Description
Technical field
The present invention relates to single inductance dual output (SIDO) adjusting and voltage-reduction switch supply convertor, relate in particular to a kind of method and circuit thereof that reduces single inductance dual-output converter output voltage steady-state error.
Background technology
In SIDO circuit, conventionally wish that circuit, when load changing is made to quick response, reduces the steady-state error of output voltage as far as possible.In the middle of the main control loop of traditional SIDO adjusting and voltage-reduction switch supply convertor, because error amplifier has adopted the PI compensation that contains large electric capacity, as shown in Figure 1, the transient response of circuit is very slow.Adopt the low gain error amplifier without large capacitance compensation, can bring 2 benefits: the one, transient response is fast; The 2nd, reduced by a large electric capacity, chip area can greatly reduce.But consider the stability of system, must reduce the gain of error amplifier.The error amplifier of low gain can make the steady-state error of output voltage become larger, and main cause has following 2 points: the one, and when load current increases, main ring gain is less, to the decline of output voltage, cannot detect delicately; The 2nd, when load current increases, the in-phase input end signal V of main ring comparator
senseincrease, cause primary switches control signal duty ratio to reduce, because error amplifier gain is lower, cannot produce enough output voltages and regulate duty ratio, so just caused larger circuit output voltage steady-state error.
Summary of the invention
The present invention is directed in SIDO main control loop, to have adopted without the low gain error amplifier of large capacitance compensation and cause large this defect of output voltage steady-state error, in order to reduce steady-state error, a kind of method and circuit thereof that reduces single inductance dual-output converter output voltage steady-state error is provided, in main ring, increase the control circuit that reduces steady-state error, greatly improved the precision of output voltage.
The concrete technical scheme that the present invention adopts is as follows: a kind of method that reduces single inductance dual-output converter output voltage steady-state error, in the control circuit of single inductance dual-output converter, main ring adopts peak current ring mode, determine converter two-way load current sum, flow through the total current mean value I of converter inductance L
l, secondary ring adopts voltage mode, determines inductive current I
ldistribution in two-way output, main ring is provided with error amplifier, comparator, trigger and driving and dead band control circuit, error amplifier in-phase end input reference voltage V
rEF1, end of oppisite phase input 0.4 * (V
o1+ V
o2), V
01, V
02respectively the two output voltage of converter, the output V of error amplifier
cthe inverting input that connects comparator, ramp voltage V
ramp1inductive current I with sampling
lr
sthe in-phase input end that connects comparator after signal stack summation, the output of comparator and clock signal be input trigger respectively, the output of trigger connects the input of driving and dead band control circuit, driving and dead band control circuit output signal PG control the break-make of primary switches, it is characterized in that: when main ring error amplifier adopts the low gain error amplifier of the large capacitance compensation of nothing, in main ring, set up a current sample-and-hold circuit, an input signal of this current sample-and-hold circuit is the inductive current I of sampling
lr
ssignal, the DC level V of current sample-and-hold circuit output
dcwith ramp voltage V
ramp1after stack summation, produce new ramp voltage V
ramp2again with the inductive current I sampling
lr
sthe input voltage V of device in-phase input end as a comparison after signal stack summation
sense, simultaneously by the output V of error amplifier
cbe superimposed with a DC level V
dc0obtain the end of oppisite phase input signal V of comparator
e, this signal V
ealso be another input signal of current sample-and-hold circuit, the DC level V that superposes
dc0should meet comparator end of oppisite phase input signal values V
ecomparator in-phase end input signal V while equaling converter full load
sensemaximum V
p, V
pvalue with load variations, during converter full load, reach maximum, V
sense=V
p-V
c, the signal of now comparator output, through the primary switches control signal PG of d type flip flop and driving and the output of dead band control circuit, can be given enough charging intervals of converter inductance, thereby reduce the steady-state error of converter output voltage;
The current sample-and-hold circuit of setting up in said method comprises control signal V
1and V
2produce circuit, d type flip flop enable signal EN generation circuit, inductive current sampling maintenance gating signal S
1and S
2produce circuit, DC level V
dcproduce circuit and at ramp voltage V
ramp1upper stack direct voltage V
dcafter stack summation, produce new ramp voltage V
ramp2circuit;
Control signal V
1and V
2produce circuit and comprise four d type flip flop D0, D1, D2, D3, two NAND gate NAND1, NAND2, input D and the output of trigger D0
short circuit also connects an input of NAND gate NAND1, another input of NAND gate NAND1 connects clock signal clk, the output of NAND gate NAND1 connects the clock end of trigger D0, the output Q of trigger D0 connects respectively the Enable Pin of trigger D1, D2, input D and the output of trigger D1
short circuit also connects the clock end of trigger D2, and the output Q sky of trigger D1 connects, and an input of NAND gate NAND2 connects input D and the output of trigger D2
, another input of NAND gate NAND2 connects clock signal clk, and the output of NAND gate NAND2 connects the clock end of trigger D1, and the output Q of trigger D2 connects the Enable Pin of trigger D3 and as control signal V
2output, the clock end of trigger D3 connects clock signal clk, input D and the output of trigger D3
short circuit, the output Q of trigger D3 is control signal V
1output;
D type flip flop enable signal EN produces circuit and comprises two comparator C OMP1, COMP2 and a same or door, and the in-phase end of comparator C OMP1, COMP2 connects respectively voltage signal V
hand V
l, the end of oppisite phase of comparator C OMP1, COMP2 interconnects and connects the poor V of two output voltage of converter
01-V
02, V
hand V
lall be chosen for (V
o1-V
o2) * (1 ± 2%), the output of comparator C OMP1 and COMP2 is connected respectively two inputs same or door, and output same or door produces enable signal EN and is connected to control signal V
1and V
2produce the Enable Pin of trigger D0 in circuit;
Inductive current sampling keeps gating signal S
1and S
2produce circuit and comprise two or an OR1, OR2, with door AND, not gate NOT, or two inputs of door OR1 connect respectively primary switches control signal PG and control signal V
2, or the output of door OR1 connects and an input of door AND, with another input connection control signal V of door AND
1, be connected with the output of door AND or an input of door OR2, or another input of door OR2 connects enable signal EN, or the output of door OR2 connects the input of not gate NOT and as gating signal S
1output, the output of not gate NOT is gating signal S
2output;
DC level V
dcproduce circuit and comprise control switch K
1, K
2, K
3, capacitor C
1, C
2, operational amplifier, buffer, control switch K
1one end connect inductive current I
lr
ssignal, control switch K
1the other end connect capacitor C
1one end and by control switch K
2ground connection, capacitor C
1the other end and end of oppisite phase, the capacitor C of operational amplifier
2one end and control switch K
3one end connect, capacitor C
2with control switch K
3the other end and the output of operational amplifier and the input of buffer link together, the in-phase end ground connection of operational amplifier, control switch K
1, K
2, K
3control end reelect respectively messenger S
1, S
2, S
1, meet output and the signal V of buffer
eand ramp voltage V
ramp1three produces DC level V after superposeing and suing for peace
dcoutput;
At ramp voltage V
ramp1upper stack direct voltage V
dcafter stack summation, produce new ramp voltage V
ramp2circuit comprise current source I, NMOS pipe M
n1, M
n2, PMOS manages M
p1, M
p2, control switch K4, K5 and capacitor C 3, the anode of current source I connects power supply V
dd, the negative terminal of current source I and NMOS pipe M
n1drain and gate and NMOS pipe M
n2grid connect, NMOS manages M
n1, M
n2source ground, NMOS manages M
n2drain electrode and PMOS pipe M
p1drain and gate and PMOS pipe M
p2grid connect, PMOS manages M
p1, M
p2source electrode connect power supply V
dd, PMOS manages M
p2one end of drain electrode connecting valve K4, the other end of K switch 4 and one end of K switch 5 and one end of capacitor C 3 is connected and as new ramp voltage signal V
ramp2output, the other end of the other end of K switch 5 and capacitor C 3 is connected and connects DC level V
dc, the control end of K switch 5, K4 connects respectively the inverted signal of clock control signal CLK and CLK
Advantage of the present invention and remarkable result:
The present invention is directed in SIDO main control loop, to have adopted without the low gain error amplifier of large capacitance compensation and cause large this defect of output voltage steady-state error, set up inductive current sampling hold circuit, compensated the DC deviation of output voltage, reduce the steady-state error of output voltage, improved the precision of output voltage.
Accompanying drawing explanation
Fig. 1 is traditional SIDO circuit theory diagrams;
Fig. 2 is the whole SIDO circuit theory diagrams after improving;
Fig. 3 a is the direct voltage V that do not superpose
dcramp voltage V
ramp1waveform and stack V
dcramp voltage V afterwards
ramp2waveform;
In Fig. 3 b, defined comparator end of oppisite phase input signal V
ecomparator in-phase input end signal V when value is full load
sensepeak value V
p;
Fig. 4 is current sample-and-hold circuit inside modules physical circuit and ramp signal V
ramp2generation circuit;
Fig. 5 is the oscillogram of each signal in current sample-and-hold circuit module.
Embodiment
Fig. 1 is traditional SIDO circuit theory diagrams.The control loop of circuit is divided into main ring and secondary ring.Main ring adopts peak-current mode, determines two-way load current sum (flowing through the total current of inductance), and secondary ring adopts voltage mode, determines the distribution of inductive current in two-way.For fear of the subharmonic oscillation phenomenon occurring when duty ratio is greater than 50%, voltage corresponding to the inductive current that detects need to a ramp voltage V
ramp1superimposed.Main ring adopts the error amplifier that has large capacitance compensation, and circuit transient response speed is slow, and simultaneously large electric capacity takies larger chip area.If error amplifier adopts the low gain error amplifier of the large capacitance compensation of nothing (by the dotted line frame capacitor C of error amplifier output in Fig. 1
p1, R
p1remove), although can bring 2 benefits: the one, transient response is fast; The 2nd, reduced by a large electric capacity, chip area can greatly reduce.But consider the stability of system, must reduce the gain of error amplifier.And the error amplifier of low gain can make the steady-state error of output voltage become larger.
Fig. 2 is the theory diagram that the present invention improves rear whole SIDO circuit working.The present invention is at ramp voltage V
ramp1dC level V who changes with load of upper stack
dc, obtain new ramp voltage V
ramp2, V
ramp2obtain V with the output voltage summation of current detector
sense, the in-phase input end signal of device as a comparison.Output signal V at error amplifier
csuitable DC level V of upper stack
dc0, make comparator end of oppisite phase input signal values V
ecomparator in-phase end input signal V while equaling full load
sensemaximum V
p, V
pvalue with load variations, during full load, reach maximum.By comparator, produce primary switches control signal, through overdrive and dead band control circuit regulating circuit to charging interval of inductance, thereby reduce the steady-state error of output voltage.The operation principle of main ring: main ring error amplifier in-phase end input signal is reference voltage V
rEF1, end of oppisite phase input signal is 0.4 * (V
o1+ V
o2), output voltage V
cbe superimposed with a direct voltage V
dc0obtain the end of oppisite phase input signal V of comparator
e, this DC level V
dc0comparator in-phase end input signal V during for circuit full load
sensepeak value V
pand V
cdifference.By comparator, produce primary switches control signal, through overdriving, control the break-make of primary switches with dead band control circuit, thereby regulating circuit is to the time that discharges and recharges of inductance.
When load is undergone mutation, might as well suppose increases when first via load, and now, first via output voltage there will be a downward overshoot, and inductive current mean value increases.Therefore, comparator in-phase end input signal V
sensealso increase V
sensemaximum V
pwith V
edifference diminish.By inductive current sampling hold circuit, inductive current peak is now sampled out and ramp voltage V
ramp1peak value is added rear and V
edo subtraction, draw V
dc.Finally, at ramp voltage V
ramp1on be superimposed with V
dc, obtain V
ramp2signal.
Fig. 3 a is the direct voltage V that do not superpose
dcramp voltage V
ramp1waveform and stack V
dcramp voltage V afterwards
ramp2waveform.In Fig. 3 b, defined main ring comparator end of oppisite phase input signal V
ecomparator in-phase input end signal V when value is full load
sensepeak value V
p, V
dc0for main ring output voltage error amplifier V
cand V
edifference.
The internal circuit configuration of Fig. 4 current sample-and-hold circuit, comprises control signal V
1and V
2produce circuit, d type flip flop enable signal EN generation circuit, inductive current sampling maintenance gating signal S
1and S
2produce circuit, DC level V
dcproduce circuit and at ramp voltage V
ramp1upper stack direct voltage V
dcafter stack summation, produce new ramp voltage V
ramp2circuit.
D type flip flop enable signal EN produces circuit: the homophase termination V of comparator 1
h, comparator 2 homophase termination V
l, both end of oppisite phase all meet V
o1-V
o2, because output voltage overshoot is generally less than 5%, so V
hand V
lcan be chosen for (V
o1-V
o2) * (1 ± 2%), the output logic level of establishing two comparators is respectively A and B.When circuit is stablized, output level A and the B of comparator is respectively " 1 " and " 0 ", when load changes, in the middle of two signals of A and B, has a signal that saltus step will occur,
wherein,
be respectively the inverted signal of A, B.Now EN can become " 1 " from " 0 ", becomes effective enable signal, d type flip flop work.
Control signal V
1and V
2generation circuit: the enable signal of d type flip flop 0 connects EN signal, output
receive input D, while handle and CLK receive clock signal terminal CLK with signal, and output Q receives the Enable Pin of d type flip flop 1,2, the output of d type flip flop 1
receive input D, and as the CLK signal of d type flip flop 2, the output of d type flip flop 2
be connected to input D, receive the CLK input of d type flip flop 1 simultaneously with after upper CLK, the output Q of d type flip flop 2 links the Enable Pin of d type flip flop 3, and as output signal V
1output, the output of d type flip flop 3
receive input D, output Q is as output signal V
2output.The function that d type flip flop 0-3 mainly realizes is as follows: as shown in Figure 4, d type flip flop 0 is mainly realized the latch function of EN, and d type flip flop 1,2 is mainly realized tally function, after counting the PG signal in 2 cycles, and output high level.D type flip flop 3 is at V
1basis on count again a PG cycle, output V
2signal.Wherein, PG signal is primary switches control signal.
Inductive current sampling keeps gating signal S
1and S
2produce circuit: PG and V
2ask or, and then and V
1, afterwards with EN phase or, obtain S
1signal, through not gate, obtains S
2signal.
Inductive current sampling hold circuit as shown in Figure 4, amplifier in-phase end ground connection, anti-phase termination capacitor C
1, then pass through K switch
1meet inductance sample rate current I
lr
s, pass through K switch
2ground connection, amplifier output passes through capacitor C
2and K switch
3article two, path is received the end of oppisite phase of amplifier.Amplifier output is through buffer, with V
eand V
ramp1summation, obtains d. c. voltage signal V
dc.Its groundwork principle is as follows: first, and K
1and K
3connect K
2disconnect, amplifier output end voltage is 0, so C
1both end voltage is just approximately equal to I
lr
s; Then, K
1and K
3disconnect K
2connect, output voltage just becomes from 0
we get C
1=C
2, amplifier output end voltage is finally stabilized in I
lr
smaximum I
lr
s-MAX.Wherein, K
1, K
2and K
3be switch of the same type, when control signal high level, switch is closed.
At ramp voltage V
ramp1upper stack direct voltage V
dcthe circuit diagram of realizing comprise current source I, NMOS current mirror, PMOS current mirror, capacitor C
3, clock switch K
4and K
5and reference voltage V
dc.Electric current I makes M by NMOS current mirror and PMOS current mirror mirror image
p2drain terminal electric current is I, K switch
4closure, K
5disconnect, electric current I is to capacitor C
3charging, the voltage on electric capacity is from V
dcwith
slope rise, reach setting voltage, now clock switch K
4disconnection, K
5closure, output voltage V
ramp2drop at once V
dc, the next clock cycle repeats above process.Wherein, K
4and K
5be switch of the same type, when control signal high level, switch is closed.
Fig. 5 is the oscillogram of a signal in current sample-and-hold circuit module, comprising the enable signal EN of d type flip flop 1 and 2, V
1and V
2signal, primary switches control signal PG, PG and V
2or signal, V
1with PG, V
2or signal phase with and inductive current I
l.
Feature and the content of this patent disclose as above, yet those skilled in the art may make all replacement and modifications that does not deviate from invention spirit based on explanation of the present invention.Therefore, protection scope of the present invention should be not limited to above-mentioned embodiment, and should comprise the various substitutions and modifications of the present invention that do not deviate from, and is contained by claims.
Claims (2)
1. a method that reduces single inductance dual-output converter output voltage steady-state error, in the control circuit of single inductance dual-output converter, main ring adopts peak current ring mode, determines converter two-way load current sum, flows through the total current mean value I of converter inductance L
l, secondary ring adopts voltage mode, determines inductive current I
ldistribution in two-way output, main ring is provided with error amplifier, comparator, trigger and driving and dead band control circuit, error amplifier in-phase end input reference voltage V
rEF1, end of oppisite phase input 0.4 * (V
o1+ V
o2), V
01, V
02respectively the two output voltage of converter, the output V of error amplifier
cthe inverting input that connects comparator, ramp voltage V
ramp1inductive current I with sampling
lr
sthe in-phase input end that connects comparator after signal stack summation, the output of comparator and clock signal be input trigger respectively, the output of trigger connects the input of driving and dead band control circuit, driving and dead band control circuit output signal PG control the break-make of primary switches, it is characterized in that: when main ring error amplifier adopts the low gain error amplifier of the large capacitance compensation of nothing, in main ring, set up a current sample-and-hold circuit, an input signal of this current sample-and-hold circuit is the inductive current I of sampling
lr
ssignal, the DC level V of current sample-and-hold circuit output
dcwith ramp voltage V
ramp1after stack summation, produce new ramp voltage V
ramp2again with the inductive current I sampling
lr
sthe input voltage V of device in-phase input end as a comparison after signal stack summation
sense, simultaneously by the output V of error amplifier
cbe superimposed with a DC level V
dc0obtain the end of oppisite phase input signal V of comparator
e, this signal V
ealso be another input signal of current sample-and-hold circuit, the DC level V that superposes
dc0should meet comparator end of oppisite phase input signal values V
ecomparator in-phase end input signal V while equaling converter full load
sensemaximum V
p, V
pvalue with load variations, during converter full load, reach maximum, V
sense=V
p-V
c, the signal of now comparator output, through the primary switches control signal PG of d type flip flop and driving and the output of dead band control circuit, can be given enough charging intervals of converter inductance, thereby reduce the steady-state error of converter output voltage.
2. the current sample-and-hold circuit of setting up in method according to claim 1, is characterized in that: comprise control signal V
1and V
2produce circuit, d type flip flop enable signal EN generation circuit, inductive current sampling maintenance gating signal S
1and S
2produce circuit, DC level V
dcproduce circuit and at ramp voltage V
ramp1upper stack direct voltage V
dcafter stack summation, produce new ramp voltage V
ramp2circuit;
Control signal V
1and V
2produce circuit and comprise four d type flip flop D0, D1, D2, D3, two NAND gate NAND1, NAND2, input D and the output of trigger D0
short circuit also connects an input of NAND gate NAND1, another input of NAND gate NAND1 connects clock signal clk, the output of NAND gate NAND1 connects the clock end of trigger D0, the output Q of trigger D0 connects respectively the Enable Pin of trigger D1, D2, input D and the output of trigger D1
short circuit also connects the clock end of trigger D2, and the output Q sky of trigger D1 connects, and an input of NAND gate NAND2 connects input D and the output of trigger D2
, another input of NAND gate NAND2 connects clock signal clk, and the output of NAND gate NAND2 connects the clock end of trigger D1, and the output Q of trigger D2 connects the Enable Pin of trigger D3 and as control signal V
2output, the clock end of trigger D3 connects clock signal clk, input D and the output of trigger D3
short circuit, the output Q of trigger D3 is control signal V
1output;
D type flip flop enable signal EN produces circuit and comprises two comparator C OMP1, COMP2 and a same or door, and the in-phase end of comparator C OMP1, COMP2 connects respectively voltage signal V
hand V
l, the end of oppisite phase of comparator C OMP1, COMP2 interconnects and connects the poor V of two output voltage of converter
01-V
02, V
hand V
lall be chosen for (V
o1-V
o2) * (1 ± 2%), the output of comparator C OMP1 and COMP2 is connected respectively two inputs same or door, and output same or door produces enable signal EN and is connected to control signal V
1and V
2produce the Enable Pin of trigger D0 in circuit;
Inductive current sampling keeps gating signal S
1and S
2produce circuit and comprise two or an OR1, OR2, with door AND, not gate NOT, or two inputs of door OR1 connect respectively primary switches control signal PG and control signal V
2, or the output of door OR1 connects and an input of door AND, with another input connection control signal V of door AND
1, be connected with the output of door AND or an input of door OR2, or another input of door OR2 connects enable signal EN, or the output of door OR2 connects the input of not gate NOT and as gating signal S
1output, the output of not gate NOT is gating signal S
2output;
DC level V
dcproduce circuit and comprise control switch K
1, K
2, K
3, capacitor C
1, C
2, operational amplifier, buffer, control switch K
1one end connect inductive current I
lr
ssignal, control switch K
1the other end connect capacitor C
1one end and by control switch K
2ground connection, capacitor C
1the other end and end of oppisite phase, the capacitor C of operational amplifier
2one end and control switch K
3one end connect, capacitor C
2with control switch K
3the other end and the output of operational amplifier and the input of buffer link together, the in-phase end ground connection of operational amplifier, control switch K
1, K
2, K
3control end reelect respectively messenger S
1, S
2, S
1, meet output and the signal V of buffer
eand ramp voltage V
ramp1three produces DC level V after superposeing and suing for peace
dcoutput;
At ramp voltage V
ramp1upper stack direct voltage V
dcthe ramp voltage V that rear generation is new
ramp2circuit comprise current source I, NMOS pipe M
n1, M
n2, PMOS manages M
p1, M
p2, control switch K4, K5 and capacitor C 3, the anode of current source I connects power supply V
dd, the negative terminal of current source I and NMOS pipe M
n1drain and gate and NMOS pipe M
n2grid connect, NMOS manages M
n1, M
n2source ground, NMOS manages M
n2drain electrode and PMOS pipe M
p1drain and gate and PMOS pipe M
p2grid connect, PMOS manages M
p1, M
p2source electrode connect power supply V
dd, PMOS manages M
p2one end of drain electrode connecting valve K4, the other end of K switch 4 and one end of K switch 5 and one end of capacitor C 3 is connected and as new ramp voltage signal V
ramp2output, the other end of the other end of K switch 5 and capacitor C 3 is connected and connects DC level V
dc, the control end of K switch 5, K4 connects respectively the inverted signal of clock control signal CLK and CLK
.
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| CN201310666465.6A CN103618455B (en) | 2013-12-10 | 2013-12-10 | Reduce method and circuit thereof that single inductance dual-output converter exports steady-state error |
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| CN106208684A (en) * | 2016-08-24 | 2016-12-07 | 西南交通大学 | The pseudo-combined dynamic afterflow control method of continuous conduction mode single-inductance double-output switch converters and device thereof |
| CN107086777A (en) * | 2016-02-12 | 2017-08-22 | 德克萨斯仪器股份有限公司 | Single input and multi-output (SIMO) DC DC converters and SIMO DC DC converter control circuits |
| CN107769532A (en) * | 2017-11-28 | 2018-03-06 | 西南民族大学 | Single-inductance double-output switch converters capacitance current ripple control method and device |
| CN110277915A (en) * | 2019-07-29 | 2019-09-24 | 电子科技大学 | Adaptive transient response suitable for Peak Current Mode DC-DC converter optimizes circuit |
| CN111585426A (en) * | 2020-05-12 | 2020-08-25 | 西安爱科赛博电气股份有限公司 | Switch-cycle-by-switch-cycle peak current limiting system and method for DC-AC converter |
| CN112383725A (en) * | 2020-11-13 | 2021-02-19 | 成都微光集电科技有限公司 | Ramp signal generating circuit and method, CMOS image sensor and readout circuit thereof |
| CN112398342A (en) * | 2021-01-21 | 2021-02-23 | 四川大学 | Frequency conversion control device and method for combined single-inductor dual-output switch converter |
| CN114696606A (en) * | 2020-12-31 | 2022-07-01 | 圣邦微电子（北京）股份有限公司 | Ramp voltage generation circuit of buck-boost converter |
| CN117155070A (en) * | 2023-10-30 | 2023-12-01 | 湃晟芯(苏州)科技有限公司 | Detection circuit of high-frequency DCDC switching power supply |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2437556A (en) * | 2006-04-26 | 2007-10-31 | Wolfson Microelectronics Plc | Current mode switching regulator |
| CN101795070A (en) * | 2010-04-02 | 2010-08-04 | 日银Imp微电子有限公司 | System for linearly adjusting slope compensation voltage slope |
| CN102324845A (en) * | 2011-09-23 | 2012-01-18 | 东南大学 | Control method for single-inductance double-output DC-DC (direct current) switching power supply and circuit thereof |
-
2013
- 2013-12-10 CN CN201310666465.6A patent/CN103618455B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2437556A (en) * | 2006-04-26 | 2007-10-31 | Wolfson Microelectronics Plc | Current mode switching regulator |
| CN101795070A (en) * | 2010-04-02 | 2010-08-04 | 日银Imp微电子有限公司 | System for linearly adjusting slope compensation voltage slope |
| CN102324845A (en) * | 2011-09-23 | 2012-01-18 | 东南大学 | Control method for single-inductance double-output DC-DC (direct current) switching power supply and circuit thereof |
Non-Patent Citations (1)
| Title |
|---|
| 刘松: "电源变换器中电流模式和电压模式相互转化", 《电焊机》, vol. 41, no. 3, 31 March 2011 (2011-03-31), pages 28 - 31 * |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107086777A (en) * | 2016-02-12 | 2017-08-22 | 德克萨斯仪器股份有限公司 | Single input and multi-output (SIMO) DC DC converters and SIMO DC DC converter control circuits |
| CN107086777B (en) * | 2016-02-12 | 2020-07-31 | 德克萨斯仪器股份有限公司 | Single Input Multiple Output (SIMO) DC-DC converter and SIMO DC-DC converter control circuit |
| CN106208684B (en) * | 2016-08-24 | 2018-07-31 | 西南交通大学 | A kind of combined control method of single-inductance double-output switch converters and its device |
| CN106208684A (en) * | 2016-08-24 | 2016-12-07 | 西南交通大学 | The pseudo-combined dynamic afterflow control method of continuous conduction mode single-inductance double-output switch converters and device thereof |
| CN107769532A (en) * | 2017-11-28 | 2018-03-06 | 西南民族大学 | Single-inductance double-output switch converters capacitance current ripple control method and device |
| CN110277915B (en) * | 2019-07-29 | 2020-11-13 | 电子科技大学 | Adaptive transient response optimization circuit suitable for peak current mode DC-DC converter |
| CN110277915A (en) * | 2019-07-29 | 2019-09-24 | 电子科技大学 | Adaptive transient response suitable for Peak Current Mode DC-DC converter optimizes circuit |
| CN111585426A (en) * | 2020-05-12 | 2020-08-25 | 西安爱科赛博电气股份有限公司 | Switch-cycle-by-switch-cycle peak current limiting system and method for DC-AC converter |
| CN111585426B (en) * | 2020-05-12 | 2021-07-27 | 西安爱科赛博电气股份有限公司 | Switch-cycle-by-switch-cycle peak current limiting system and method for DC-AC converter |
| CN112383725A (en) * | 2020-11-13 | 2021-02-19 | 成都微光集电科技有限公司 | Ramp signal generating circuit and method, CMOS image sensor and readout circuit thereof |
| CN112383725B (en) * | 2020-11-13 | 2023-05-05 | 成都微光集电科技有限公司 | Ramp signal generating circuit and method, CMOS image sensor and readout circuit thereof |
| CN114696606A (en) * | 2020-12-31 | 2022-07-01 | 圣邦微电子（北京）股份有限公司 | Ramp voltage generation circuit of buck-boost converter |
| CN112398342A (en) * | 2021-01-21 | 2021-02-23 | 四川大学 | Frequency conversion control device and method for combined single-inductor dual-output switch converter |
| CN117155070A (en) * | 2023-10-30 | 2023-12-01 | 湃晟芯(苏州)科技有限公司 | Detection circuit of high-frequency DCDC switching power supply |
| CN117155070B (en) * | 2023-10-30 | 2023-12-29 | 湃晟芯(苏州)科技有限公司 | Detection circuit of high-frequency DCDC switching power supply |
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