CN104900636A - 半导体组件的制造方法 - Google Patents

半导体组件的制造方法 Download PDF

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Publication number
CN104900636A
CN104900636A CN201510315302.2A CN201510315302A CN104900636A CN 104900636 A CN104900636 A CN 104900636A CN 201510315302 A CN201510315302 A CN 201510315302A CN 104900636 A CN104900636 A CN 104900636A
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CN
China
Prior art keywords
semiconductor component
jockey
substrate
liquid
encapsulate
Prior art date
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CN201510315302.2A
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English (en)
Inventor
T·斯托克梅尔
H·海尔布伦尔
C·戈布尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semikron GmbH and Co KG
Semikron Elektronik GmbH and Co KG
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Semikron Elektronik GmbH and Co KG
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Application filed by Semikron Elektronik GmbH and Co KG filed Critical Semikron Elektronik GmbH and Co KG
Publication of CN104900636A publication Critical patent/CN104900636A/zh
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Abstract

本发明涉及一种用于制造半导体组件的方法，具有以下主要步骤：形成一个结构，该结构具有至少一个半导体构件、至少一个连接装置和至少一种设置在它们之间的结合剂；整个地或部分地封装此结构，形成至少一个半导体构件单元与至少一个连接装置的材料一体的连接。

Description

半导体组件的制造方法
本申请是基于申请号为200810176175.2，申请日为2008年11月14日，发明名称为“半导体组件的制造方法”的中国专利申请提出的分案申请。
技术领域
本发明涉及半导体组件的制造方法，所述半导体组件例如是功率半导体模块的组成部件。这种功率半导体模块按照现有技术具有外壳，带有功率半导体构件的基片，以及负载和辅助连接单元。以下所述半导体构件例如是指作为功率半导体模块的组成部件的组件，所述模块包括基片和与基片材料一体地相连的半导体构件，或者包括半导体构件和材料一体相连的连接单元，或者包括它们的组合。这里不仅仅包括基片，而且也包括连接装置意义下的连接单元。
背景技术
为了制造这种半导体组件，现有技术已公开了焊接和烧结方法。DE19911887C1公开了一种软熔焊接方法，其特点是增设了真空装置。这里在本来的气相焊接过程之后焊接件被送入所述真空装置。这样有效地避免了收缩凹孔的形成，因为可能形成的收缩凹孔借助于真空从焊剂中被排除。
已知的这种焊接方法的缺点例如是：接在半导体组件的焊接之后通常必须跟着一个清洗工序，以借助于清洗液去除焊剂残留物。
DE102004019567B3公开了压力烧结方法的最新改进，其特点是借助于承载薄膜上的雾状涂层设置烧结膏的专用方法。在进一步的工序中预干燥的烧结膏从承载薄膜被去除并且设置在要被结合的表面上。已知的银粉和诸如环己醇的焊剂的混合物被用作该烧结方法的烧结膏。
这种借助于机械压力的已知烧结方法的缺点在于，它们通常只能同时形成一个烧结连接，并且/或者特别是在半导体构件的结合时存在构件破损的危险。
用于半导体组件的连接装置的新型实现方式例如在DE102006015198A1中被公开。在此这种连接装置被设计成特殊的有柔韧性的印刷电路板的结构。此结构具有由导电层和绝缘层交替排列构成的薄膜型层结构。
发明内容
本发明的目的在于改进已知的在至少一个半导体构件与至少一个连接装置之间采用材料一体连接的半导体组件制造方法，其中结合双方至少部分地没有与施加压力和/或温度的介质形成直接接触。
上述任务按照本发明由具有权利要求1所述特征的方法完成。从属权利要求给出本发明的优选实施方式。
本发明所述的用于制造半导体组件的方法的出发点是上面所述的功率半导体模块。用于这种功率半导体模块的半导体组件应满足多个要求，这些要求在现有技术中至少部分地相互排斥。这些要求中包括在半导体构件与连接装置之间形成在功率半导体模块正常加载时也能持久地保持和承载材料一体的连接。另一方面也要求半导体组件的制造成本低廉且较为省时。
按照本发明，用于形成这种半导体组件的制造方法具有以下主要步骤：
A)构造一种结构，该结构具有至少一个半导体构件，至少一个连接装置和至少一种设置在它们之间的结合剂；这里最好是将多个功率半导体构件同时排列在一个基片上。其中结合剂，最好是焊接或烧结膏例如借助于丝网印刷被设置到基板上，更确切地说，设置到基片的相应连接面上，并且在连接面上设置分别材料一体连接的功率半导体构件。
B)在下一步骤中按照A)构造的结构被可逆地且整个地、最好是用塑料薄膜封装起来；这里特别具有优点的是此结构被放入一个软管形构造的塑料薄膜中，然后它被抽真空和封闭。这样形成了对此结构的保护而不受其它制造工序影响。另一个优选的封装实现方式是用少量的粘胶材料，例如硅橡胶，它不是整个地包住此结构。
C)形成至少一个半导体构件单元与至少一个连接装置的材料一体连接；这种材料一体连接最好实现为焊接或烧结结合。这里特别优选的是借助于液体介质在所述结构上施加温度和/或压力。其中封装起到了相对液体介质的保护层的作用。这样不仅避免了结合剂的污染，而且也避免了结合剂被冲刷掉的可能性。同时封装只轻微影响温度和/或压力的施加。
D)在设计成可逆封装的情况下封装接着被去除。从而使半导体组件、例如功率半导体模块的后续处理可以不进行其它的工序，例如在焊接方法中经常进行的清洗工序。
所建议的制造半导体组件的方法避免了原理上已知的材料一体连接方法的缺点，并可以采用液体介质。这样，特别是在烧结结合时可以利用流体静力学的压力导入相对于机械加压的优点。此优点首先在于各向均匀的压力导入，它特别避免了施压时半导体构件的破损危险，或者至少明显降低了这种危险。
附图说明
在对实施例的相应描述中列举了这种制造方法的特别优选的改进。下面借助图1至6所示实施例进一步说明根据本发明的技术方案。
图1至3示出了本发明所述的半导体组件制造方法的第一实施例的三个主要的相继步骤。
图4示出了本发明所述的制造方法的第二实施例的一个方法步骤。
图5示出了本发明所述的制造方法的第三实施例的一个方法步骤。
图6示出了本发明所述的制造方法的第四实施例的一个方法步骤。
具体实施方式
图1示出了本发明所述的半导体组件制造方法的第一个步骤。在此连接装置被设计为电绝缘的基片10，它按照现有技术具有绝缘基体12和设置在至少一个主表面上的多个导体线路14以及在其上形成的接触面16。在烧结结合情况下按照现有技术接触面16具有贵金属表面是具有优点的。基片10最好设计为常用的印刷电路板，IMS(隔离金属基片)或DBC(直接的铜连线)基片。作为基片10的连接装置的示例性实施例不限制以上说明的普遍性。同样也可设想连接单元(参见图4至6)用于结合一个基片或者一个或多个半导体构件，以实现内部和/或外部的接触。
在基片10主表面上的接触面16上按照现有技术设置结合剂20，这里是烧结膏。对于焊接结合，其上设置的当然是焊膏或者一个或多个焊接片。这些焊接片由焊接材料构成，此焊接片的形状适配于待焊接的半导体构件30的大小，并且它被设计成平面状的金属体。
设置膏20的优点还在于，它一方面贴在基片10上，另一方面也贴在其上放置的半导体构件30上。这样通常不需要其它介质来将结合双方10，30相互固定。特别具有优点的是采用丝网印刷方法将相应的膏20设置到基片10主表面的接触面16上。这样在加工过程中结合剂20被涂覆到所有需要的各个结合位置上。在半导体构件单元30适当的主表面上设置结合剂在某些应用情况下同样是优选的。
相应的半导体构件30以根据现有技术的拣选或放置方法直接从芯片复合体中被取出，在将其切割分开后放置到结合剂、即烧结膏30上。
图2示出了跟在图1所示方法步骤之后的步骤。其中结构1由多个半导体构件单元30、基片10和分别适当涂覆在它们之间的烧结膏20组成，此结构用薄膜40形式的塑料封装。对于烧结方法中后继的施压来说薄膜40必须整个封装所述结构1。
为外还可以应用设计成皱缩软管的塑料。此时结构1被放入皱缩软管40中，接近完全地被封闭并接着如此加温，使得皱缩软管40适配于此结构的轮廓(参见图3)。接着皱缩软管40被完全封闭。
另一个不受局限的可能性是应用软管形构造的弹性塑料薄膜，在其中放入所述结构。软管被接近完全地封闭并抽真空。在软管接着被完全封闭后所述结构可以提供给下一方法步骤继续处理。
图3示出了形成材料一体连接的后续方法步骤，这里结合是烧结结合。为此被塑料薄膜40封装的结构1被施加数量级为100MPa的压力46和数量级为100℃的温度44。这里特别具有优点的是，被封装的结构40被置于用稳压硅油42填充的压力池48中并在那里施加压力46一段适当的时间。这种液体静力学方式的压力导入46导致对结合双方10，30的施压特别节省材料。
为了形成焊接结合，类似的已预先用塑料薄膜封装的结构被放入加热到焊接温度的液体中。特别适用的是已知应用于汽相焊接设备中的液体。
图4示出了本发明所述制造方法的第二实施例的一个方法步骤。这里此步骤与图2所示方法步骤相当。与图2所示步骤的区别在于，这里是为一个功率半导体构件30与基片10的导体线路14、并同时与金属形体50的轮廓中的负载连接单元进行焊接结合而准备的。
负载连接单元50具有与焊膏20的接触面52，焊膏被设置在半导体构件30上。此外它还具有作为弯曲边缘的铸坑54和用于外部接触的孔56。为了位置固定和位置控制，在孔的区域内，在负载连接单元50与基片10之间设置了定位辅助体60。在结构被封装40后接着可借助于合适的液体完成焊接结合。
图5示出了本发明所述制造方法的第三实施例的一个方法步骤。这里此步骤与图2所示步骤相当。与图2所示步骤的区别在于，连接装置被构造成具有柔韧性的印刷电路板70。按照现有技术已知的，此印刷电路板例如被构造成多层的，它分别由导电层72，76和绝缘层74组成，图中所示为三层结构。同样像已知的那样在导电层72，76之间设置了电路所需的穿孔接触。
应用具有柔韧性的印刷电路板70的主要优点在于，在一个方法步骤中半导体构件30不仅可以与基片10的第一导体线路14相连接，而且也可以与具有柔韧性的印刷电路板70相连接，同样，具有柔韧性的印刷电路板70可以与基片10的其它导体线路14相连接。对于这种半导体组件实现方式特别有利的是，烧结膏20作为相应的结合剂，并且借助于上面已说明的加压烧结方法实现结合。这里基片10的导体线路14的表面16、半导体构件30的接触面以及具有柔韧性的印刷电路板70的待结合的导电层72的接触面78当然应附着合适的金属，最好是贵金属。
图6示出了本发明所述制造方法的第四实施例的一个方法步骤。这里此步骤与图2所示步骤相当。与图5相比，连接装置也被构造成作为一个变体的具有柔韧性的印刷电路板70，它具有用于与功率半导体构件30或与基片的连接面14电气连接的接触突点。
本发明所述方法的这个实施例的特别的优点在于，硅胶软管作为封装40，它在现有技术中常期以来作为功率半导体模块中的绝缘材料。此硅橡胶软管40一方面用作后续制造的功率半导体模块的绝缘，另一方面在加压烧结方法中作为结构1的保护封装40，在此它仅构成部分封装。通过在压力池48中施加压力实现液体静力学方式的压力导入到硅胶软管40上，软管继续传导压力到结构1的待结合的部分上，而其本身位置没有明显的改变。

Claims (15)

1.用于制造半导体组件的方法，具有以下主要步骤：
A)形成结构(1)，该结构具有至少一个半导体构件(30)、至少一个连接装置(10，50，70)和至少一种设置在它们之间的结合剂(20)；
B)整个地或部分地封装(40)所述结构(1)，所述结构被封闭；
C)形成所述至少一个半导体构件(30)与所述至少一个连接装置(10，50)的材料一体的连接，其中，封装(40)起到了相对液体介质(42)的保护层的作用，所述液体介质用于形成材料一体的连接，并且其中封装(40)只轻微地影响温度和/或压力的施加。
2.如权利要求1所述的方法，其中，结合剂(20)被实现为焊接片或焊膏，并且它借助于丝网印刷工艺被涂覆到半导体构件(30)或连接装置(10，50)的主表面(16，32)上。
3.如权利要求1所述的方法，其中，结合剂(20)被实现为烧结膏，并且它借助于丝网印刷工艺被涂覆到半导体构件(30)或连接装置(10，50，70)的主表面(16，32)上。
4.如权利要求1所述的方法，其中，在形成结合之后接着再将封装(40)从所述结构(1)去除。
5.如权利要求1所述的方法，其中，连接装置是基片(10)和/或以功率半导体模块(30)的金属形体(50)的形式实现的连接单元。
6.如权利要求1所述的方法，其中，连接装置是具有柔韧性的印刷电路板(70)，所述印刷电路板具有由导电层(72，76)和绝缘层(74)构成的层结构。
7.如权利要求6所述的方法，其中，所述印刷电路板(70)具有用于与功率半导体构件(30)或与基片的连接面(14)电气连接的接触突点。
8.如权利要求1所述的方法，其中，封装(40)被实现为软管形薄膜，它在封装后被封闭，接着被抽真空，或者通过加温被皱缩，从而贴靠在所述结构上。
9.如权利要求1所述的方法，其中，封装(40)借助于少量粘胶材料实现。
10.如权利要求1或2所述的方法，其中，材料一体连接的形成借助于加热到焊接温度的液体(42)来实现，并且为此将所述结构(1)放入该液体(42)一段时间。
11.如权利要求1或3所述的方法，其中，材料一体连接的形成借助于位于压力池(48)中的液体(42)，即一种稳压硅油来实现，并且为此将所述结构(1)放入该液体(42)一段时间，而且接着从外部对该液体(42)施加压力(46)。
12.如权利要求1至3及5至9中的任一项所述的方法，其中，硅橡胶设置为封装(40)，所述硅橡胶一方面用作后续制造的功率半导体模块的绝缘，另一方面在加压烧结方法中作为结构(1)的保护封装(40)。
13.如权利要求12所述的方法，其中，所述封装(40)是仅部分构成的封装。
14.如权利要求1至9之一所述的方法，其中，所述方法用于功率半导体构件(30)与基片(10)的导体线路(14)、并同时与构造成金属形体(50)的负载连接单元进行焊接结合。
15.如权利要求14所述的方法，其中，在负载连接单元(50)与基片(10)之间设置有定位辅助体(60)，以用于位置固定和位置控制。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008033410B4 (de) * 2008-07-16 2011-06-30 SEMIKRON Elektronik GmbH & Co. KG, 90431 Leistungselektronische Verbindungseinrichtung mit einem Leistungshalbleiterbauelement und Herstellungsverfahren hierzu
DE102009024385B4 (de) * 2009-06-09 2011-03-17 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung eines Leistungshalbleitermoduls und Leistungshalbleitermodul mit einer Verbindungseinrichtung
DE102009050178B3 (de) * 2009-10-21 2011-05-26 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit einem eine dreidimensionale Oberflächenkontur aufweisenden Substrat sowie Herstellungsverfahren hierzu
DE102011080929B4 (de) 2011-08-12 2014-07-17 Infineon Technologies Ag Verfahren zur Herstellung eines Verbundes und eines Leistungshalbleitermoduls
DE102012201172B4 (de) * 2012-01-27 2019-08-29 Infineon Technologies Ag Verfahren zur Herstellung eines Leistungshalbleitermoduls mit geprägter Bodenplatte
DE102012206407B4 (de) * 2012-04-18 2017-05-04 Infineon Technologies Ag Druckkontaktanordnung und verfahren zur herstellung und zum betrieb einer druckkontaktanordnung
DE102012211952B4 (de) * 2012-07-09 2019-04-25 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit mindestens einem stressreduzierenden Anpasselement
DE102014203309A1 (de) * 2014-02-25 2015-08-27 Siemens Aktiengesellschaft Elektronikmodul mit zwei elektrisch leitfähigen Strukturierungen
US9691637B2 (en) * 2015-10-07 2017-06-27 Nxp Usa, Inc. Method for packaging an integrated circuit device with stress buffer
DE102019204683A1 (de) * 2019-04-02 2020-10-08 Volkswagen Aktiengesellschaft Verfahren und Vorrichtung zum stoffschlüssigen Verbinden mindestens eines Halbleitermoduls mit mindestens einem Gehäuseteil eines Kühlmoduls

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5352629A (en) * 1993-01-19 1994-10-04 General Electric Company Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules
CN1206934A (zh) * 1997-07-22 1999-02-03 日本电气株式会社 芯片封装装置
US20030016510A1 (en) * 2001-07-18 2003-01-23 Wolfgang Knapp Method for mounting electronic components on substrates
US20060096946A1 (en) * 2004-11-10 2006-05-11 General Electric Company Encapsulated wafer processing device and process for making thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5956745A (ja) * 1982-09-24 1984-04-02 Sharp Corp 電子部品
US4715686A (en) * 1984-11-16 1987-12-29 Seiko Epson Corporation Light-passive display device and method of manufacturing same
JPS6264475A (ja) * 1985-09-17 1987-03-23 Kenji Kondo 物品の融着接合装置
US5331513A (en) * 1991-07-12 1994-07-19 Rohm Co., Ltd. Method of mounting electronic part on circuit substrate and circuit substrate including electronic parts mounted thereon
US5403671A (en) * 1992-05-12 1995-04-04 Mask Technology, Inc. Product for surface mount solder joints
DE19911887C1 (de) * 1999-03-17 2000-12-21 Asscon Systech Elektronik Gmbh Verfahren zum Reflow-Löten in einer Dampfphasenvakuumlötanlage
JP2002184908A (ja) * 2000-12-19 2002-06-28 Sony Corp 電子回路装置
DE102004019567B3 (de) * 2004-04-22 2006-01-12 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Befestigung von elektronischen Bauelementen auf einem Substrat
DE102004030383A1 (de) * 2004-06-23 2006-01-12 Infineon Technologies Ag Bondfolie und Halbleiterbauteil mit Bondfolie sowie Verfahren zu deren Herstellung
JP4524454B2 (ja) * 2004-11-19 2010-08-18 ルネサスエレクトロニクス株式会社 電子装置およびその製造方法
DE102006015198A1 (de) * 2006-04-01 2007-10-11 Semikron Elektronik Gmbh & Co. Kg Verbindungseinrichtung für elektronische Bauelemente

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5352629A (en) * 1993-01-19 1994-10-04 General Electric Company Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules
CN1206934A (zh) * 1997-07-22 1999-02-03 日本电气株式会社 芯片封装装置
US20030016510A1 (en) * 2001-07-18 2003-01-23 Wolfgang Knapp Method for mounting electronic components on substrates
US20060096946A1 (en) * 2004-11-10 2006-05-11 General Electric Company Encapsulated wafer processing device and process for making thereof

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