CN104849651A - Online detection logic unit of hardware circuit - Google Patents
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Abstract
The invention provides an online detection logic unit of a hardware circuit, and relates to the field of logic unit online detection. The online detection logic unit solves problems that an existing basic logic element structure of a look up-table adding a trigger is lack of determination of faults of the basic logic element and a fault response mechanism, once faults occur, a whole circuit including other basic logic elements in normal operation are abandoned to use, so as to cause resource wastes and low hardware utilization rate. An either-or multipath selector is used to determine output of a logic unit according to input configuration bits. A check bit generation circuit converts four paths of information bits to three paths of Berger code check bits. A compartor is combined to determine whether a combinatorial logic function has faults. An XOR gate is used to determine whether a sequential logic function has faults. An OR gate is used to receive sequential logic function fault detection results and combinatorial logic function fault detection results, and performs OR logic on the results, so as to determine whether a logic unit has faults. The online detection logic unit is used for online detection of a logic unit.
Description
Technical field
The present invention relates to and a kind of to be completed the on-line checkingi of the combinational logic of basic logic unit (Basic Logic Element, BLE) and the novel basic logic unit structure of on-line checkingi being completed the sequential logic to basic logic unit (BLE) by the two mode field of d type flip flop by coding circuit.Belong to logical block on-line checkingi field.
Background technology
The on-line checkingi of hardware circuit refers to when hardware circuit normally works, the working condition of monitoring hardware circuit that can be real-time, and whether inspection hardware circuit breaks down, and need not affect the normal work of hardware circuit.Along with programmable logic device (PLD) developing rapidly as a kind of universal device, change traditional employing fixed function device, conventional digital design method from bottom to top, user can be no longer dependent on the specialized chip manufactured and designed by chip manufacturer, but realizes required combination and sequential function by the mode of programming.And the realization of logic function be unable to do without basic logic unit.The look-up table (Look Up-Table, LUT) that traditional basic logic unit is inputted by a N and a trigger realize.Look-up table (LUT) is for the configuration information of stored logic function, thus be used for realizing the combination logic function that user needs to realize, trigger is then used for storing the signal of current state, in conjunction with look-up table (LUT), the two can realize the sequential logic function needed for user jointly.Whether the output according to look-up table (LUT) passes through trigger, and basic logic unit can be selected to realize combinational logic or sequential logic.Can be connected by the basic logic unit of this spline structure multiple, jointly can realize the large-scale circuit of a function complexity.
But traditional look-up table adds that the structure of the basic logic unit of trigger (BLE) is not for the coping mechanism of fault.User is difficult to judge whether corresponding basic logic unit (BLE) normally works, especially when circuit scale is larger, the basic logic unit (BLE) having quantity extremely many comes into operation, once break down, want to determine fault and fault is positioned and will become extremely difficult, even if single basic logic unit (BLE) breaks down, whole circuit comprises other basic logic units normally worked all will be abandoned using, thus causing the wasting of resources, hardware utilization rate is low.Therefore, the demand can carrying out the novel basic logic unit of on-line checkingi to fault is just created.
Summary of the invention
The present invention adds that the structure of the basic logic unit of trigger lacks judge basic logic unit fault and the coping mechanism to fault to solve existing look-up table, once break down, cause whole circuit to comprise other basic logic units normally worked all will be abandoned using, thus cause the wasting of resources, the problem that hardware utilization rate is low.A kind of on-line checkingi logical block of hardware circuit is now provided.
An on-line checkingi logical block for hardware circuit, it comprise 4 input look-up table unit, four groups of d type flip flops, check bit generative circuit, four 2 select 1 MUX, comparer, four XOR gate and one or,
4 input look-up table unit, for storage logical units want the configuration information of practical function, realize the combination logic function of required configuration circuit, and export corresponding 4 tunnel information bits and 3 correct coding information checking positions, road according to 4 addresses, tunnel of input, export four road configuration bits, described configuration information comprises the information bit that the configuration bit for selecting to realize combination logic function, the correct coding information checking position corresponding with configuration bit and combination sequential function are selected simultaneously;
Four groups of d type flip flops receive four tunnel information bits respectively, and described d type flip flop of often organizing comprises two d type flip flops;
D type flip flop, for the road information bit according to reception, the duty of stored configuration circuit, realizes the sequential logic function of required configuration circuit, and exports to an XOR gate;
Four groups of d type flip flops export to four XOR gate respectively;
Each XOR gate, whether consistent for judging the output of two d type flip flops inputted, determine whether sequential logic function breaks down, if the output of two d type flip flops is identical, export high level, sequential logic function breaks down, if the output of two d type flip flops is different, output low level, sequential logic function does not have fault;
Described four road configuration bits input to the configuration end that four 2 are selected the MUX of 1 respectively;
2 select 1 MUX, for the configuration bit according to input, determine the output of logical block, if configuration bit selects Combinational logic output, then export a road information bit corresponding in look-up table; If configuration bit selects Sequential logic output, then export the output of a d type flip flop corresponding with a described road information bit, a described d type flip flop is one in one group of d type flip flop corresponding with a described road information bit;
Check digit generative circuit, for being transformed to 3 road Berger codes check bit by 4 tunnel information bits;
Comparer, for comparing correct coding information checking position and Berger codes check bit to judge whether combination logic function produces fault, if identical, output low level, combination logic function does not have fault, if different, what export is high level, and sequential logic function breaks down;
Or door, for the combination logic function syndrome check result that the sequential logic functional fault assay and comparer that receive four XOR gate outputs export, and it is carried out or logic, whether decision logic unit breaks down, if one in four XOR gate sequential logic function exported breaks down, or the combination logic function that comparer exports breaks down, export high level, logical block breaks down; If the combination logic function that the sequential logic function of four XOR gate outputs does not all have fault and comparer to export does not have fault, output low level, logical block does not have fault.
Beneficial effect of the present invention is: 4 addresses, tunnel are input in 4 input look-up table unit by the present invention, according to the logical block of 4 input look-up table element memories storages want the configuration bit of practical function, the correct coding information checking position corresponding to configuration bit and combine the information bit that sequential function selects to export 4 corresponding tunnel information bits, 3 correct coding information checking positions, road and 4 road configuration bits
4 information bits that 4 input look-up tables export generate the check bit corresponding with output information position by Berger codes check bit generative circuit; By comparer, the check bit produced by Berger codes check bit generative circuit and the correct coded message check bit be stored in 4 input look-up table unit are compared, judge whether 4 input look-up table unit break down according to both comparative results: if both come to the same thing, then the combination logic function of 4 input look-up table unit is correct, and 4 input look-up table cell failure signals of output are high level; If both results are different, then the combination logic function of 4 input look-up table unit is incorrect, and 4 input look-up table cell failure signals of output are high level.Comparative result is exported to or door.
The output of each road information of the 4 tunnel information bits that 4 input look-up table unit export all is connected with two identical d type flip flops, and two d type flip flops have output; Compared by the result of XOR gate to the output of two identical d type flip flops; Judge whether d type flip flop breaks down according to both comparative results: if the result of two d type flip flop outputs is inconsistent, then there is d type flip flop and break down, the d type flip flop fault-signal of output is high level; If coming to the same thing of two d type flip flop outputs, then d type flip flop all normally works, and the d type flip flop fault-signal of output is low level, and comparative result is exported to or door,
Finally by or door according to the combination logic function of input and sequential logic function, whether decision logic unit breaks down.
Adopt the arrangement achieves to combination logic function and sequential logic function at X-ray inspection X, inspection structure is simple, and hardware resource utilization is high.
Accompanying drawing explanation
Fig. 1 is the principle schematic of the on-line checkingi logical block of a kind of hardware circuit described in embodiment one,
The principle schematic of check digit generative circuit in the on-line checkingi logical block that Fig. 2 is a kind of hardware circuit described in embodiment five.
Embodiment
Embodiment one: illustrate present embodiment with reference to Fig. 1, the on-line checkingi logical block of a kind of hardware circuit described in present embodiment, it comprises 4 input look-up table unit, 1, four groups of d type flip flops 3, check bit generative circuit 4, four 2 select 1 MUX 9, comparer 6, four XOR gate 8 and one or 7
4 input look-up table unit 1, for storage logical units 10 want the configuration information of practical function, realize the combination logic function of required configuration circuit, and export corresponding 4 tunnel information bits and 3 correct coding information checking positions, road according to 4 addresses, tunnel of input, export four road configuration bits, described configuration information comprises the information bit that the configuration bit for selecting to realize combination logic function, the correct coding information checking position corresponding with configuration bit and combination sequential function are selected simultaneously;
Four groups of d type flip flops 3 receive four tunnel information bits respectively, and described d type flip flop 3 of often organizing comprises two d type flip flops 3;
D type flip flop 3, for the road information bit according to reception, the duty of stored configuration circuit, realizes the sequential logic function of required configuration circuit, and exports to an XOR gate 8;
Four groups of d type flip flops 3 export to four XOR gate 8 respectively;
Each XOR gate 8, whether consistent for judging the output of two d type flip flops 3 inputted, determine whether sequential logic function breaks down, if the output of two d type flip flops 3 is identical, export high level, sequential logic function breaks down, if the output of two d type flip flops 3 is different, output low level, sequential logic function does not have fault;
Described four road configuration bits input to the configuration end that four 2 are selected the MUX 9 of 1 respectively;
2 select 1 MUX 9, for the configuration bit according to input, determine the output of logical block 10, if configuration bit selects Combinational logic output, then export a road information bit corresponding in 4 input look-up table unit 1; If configuration bit selects Sequential logic output, then export the output of a d type flip flop 3 corresponding with a described road information bit, a described d type flip flop 3 is one in one group of d type flip flop 3 corresponding with a described road information bit;
Check digit generative circuit 4, for being transformed to 3 road Berger codes check bit by 4 tunnel information bits;
Comparer 6, for comparing correct coding information checking position and Berger codes check bit to judge whether combination logic function produces fault, if identical, output low level, combination logic function does not have fault, if different, what export is high level, and sequential logic function breaks down;
Or door 7, for the combination logic function syndrome check result that the sequential logic functional fault assay and comparer 6 that receive four XOR gate 8 outputs export, and it is carried out or logic, whether decision logic unit 10 breaks down, if one in four XOR gate 8 sequential logic function exported breaks down, or the combination logic function that comparer 6 exports breaks down, export high level, logical block 10 breaks down; If the sequential logic function of four XOR gate 8 outputs does not all have fault, the combination logic function that comparer 6 exports simultaneously does not have fault, output low level yet, and logical block 10 does not have fault.
In present embodiment, the address location of stored configuration position stores 4 bit pattern sequential logic option and installment positions and 30.
The process of combinational logic part being carried out to online code detection is:
(1) 4 information bits that 4 input look-up tables export generate the check bit corresponding with output information position by Berger codes check bit generative circuit;
(2) by comparer, the check bit produced by Berger codes check bit generative circuit and the correct coded message check bit be stored in 4 input look-up table unit are compared;
(3) judge whether 4 input look-up table unit break down according to both comparative results: if both coming to the same thing, then 4 input the combination logic function of look-up table unit correctly, 4 input look-up table cell failure signals of output are high level; If both results are different, then the combination logic function of 4 input look-up table unit is incorrect, and 4 input look-up table cell failure signals of output are high level.
The process of sequential logic part being carried out to online bimodulus detection is:
(1) the output of each road information of 4 tunnel information bits of 4 input look-up table unit outputs is all connected with two identical d type flip flops, and two d type flip flops have output;
(2) compared by XOR gate (XOR) result to the output of two identical d type flip flops;
(3) judge whether d type flip flop breaks down according to both comparative results: if the result of two d type flip flop outputs is inconsistent, then there is d type flip flop and break down, the d type flip flop fault-signal of output is high level; If coming to the same thing of two d type flip flop outputs, then d type flip flop all normally works, and the d type flip flop fault-signal of output is low level.
The process that the fault-signal with the basic logic unit structure output of on-line checkingi function produces is:
Using the fault-signal of 4 of combinational logic part input look-up table unit and multiple d type flip flop fault-signal results of sequential logic part as or the input of door;
Using or door Output rusults as have on-line checkingi function logical unit structure export fault-signal, if multiple d type flip flop fault-signals of the look-up table fault-signal of combinational logic part and sequential logic part are low level, namely whole basic logic unit does not have mistake, then this fault-signal with the basic logic unit structure output of on-line checkingi function is low level; If it is high level that multiple d type flip flop fault-signals of the look-up table fault-signal of combinational logic part and sequential logic part exist any one or more signal, namely there is one or more mistake in whole basic logic unit, then this fault-signal with the basic logic unit structure output of on-line checkingi function is high level.
Embodiment two: present embodiment is described further the on-line checkingi logical block of a kind of hardware circuit described in embodiment one, in present embodiment, the figure place formula of Berger codes check bit is k=[log
2(i+1)], wherein, i is the way of input information bit, and k is the way of the Berger codes check bit exported.
In present embodiment, the on-line checkingi part of combination logic function selects Berger codes (Berger Codes) as coding check mode, reason is that the check bit of Berger codes needed in all separable code systems is minimum, code efficiency is the highest, coding circuit is also more simple, and reliability is higher.Berger codes check bit figure place k can calculate according to formula (1).
k＝[log
2(i+1)] (1)
Wherein, i is the figure place of input information bit,
4 volume information bits that 4 input look-up table unit 1 export being brought into the figure place that formula (1) calculates Berger codes check bit is 3.
The cataloged procedure of described Berger codes is:
(1) produce one with in information bit 1 the corresponding binary code of number;
(2) check bit is formed to the binary code step-by-step negate produced;
(3) check bit is attached to after original information bits.
The Berger codes of 4 information codes is as following table:
The Berger codes of table 14 information codes
| Raw information | Berger codes | Raw information | Berger codes |
| 0000 | 0000 111 | 1000 | 1000 110 |
| 0001 | 0001 110 | 1001 | 1001 101 |
| 0010 | 0010 110 | 1010 | 1010 101 |
| 0011 | 0011 101 | 1011 | 1011 100 |
| 0100 | 0100 110 | 1100 | 1100 101 |
| 0101 | 0101 101 | 1101 | 1101 100 |
| 0110 | 0110 101 | 1110 | 1110 100 |
| 0111 | 0111 100 | 1111 | 1111 011 |
。
Embodiment three: present embodiment is described further the on-line checkingi logical block of a kind of hardware circuit described in embodiment one, in present embodiment, often organize d type flip flop 3 and adopt two mode field, namely the input of two d type flip flops 3 is identical.
Embodiment four: illustrate present embodiment with reference to Fig. 2, present embodiment is described further the on-line checkingi logical block of a kind of hardware circuit described in embodiment one, in present embodiment, check digit generative circuit 4 comprises full adder 4-1, a half adder 4-2 No. bis-half adder 4-3, phase inverter 4-4, No. two phase inverter 4-5 and No. three phase inverter 4-6
3 input ends of full adder 4-1 are respectively as 3 tunnel information bit input ends of check digit generative circuit 4, the low order carry end C1 of full adder 4-1 connects an input end of a half adder 4-2, one's own department or unit of full adder 4-1 adds the input end being connected No. two half adder 4-3 with S1 entirely, another input end of a half adder 4-2 connects the carry digit C2 of No. two half adder 4-3, another input end of No. two half adder 4-3 is as the 4th tunnel information bit input end of check digit generative circuit 4
The carry digit C2 of a half adder 4-2 connects the input end of a phase inverter 4-4, and the false add of a half adder 4-2 and number S2 hold the input end of connection No. two phase inverter 4-5, and the false add of No. two half adder 4-3 is connected the input end of No. three phase inverter 4-6 with number S2,
The output terminal of the output terminal of a phase inverter 4-4, the output terminal of No. two phase inverter 4-5 and No. three phase inverter 4-6 is all as 3 Berger codes check bit output terminals of check digit generative circuit 4.
Claims (4)
1. the on-line checkingi logical block of a hardware circuit, it is characterized in that, it comprise 4 input look-up table unit (1), four groups of d type flip flops (3), check bit generative circuit (4), four 2 select 1 MUX (9), comparer (6), four XOR gate (8) and one or (7)
4 inputs look-up table unit (1), for storage logical units (10) want the configuration information of practical function, realize the combination logic function of required configuration circuit, and export corresponding 4 tunnel information bits and 3 correct coding information checking positions, road according to 4 addresses, tunnel of input, export four road configuration bits, described configuration information comprises the information bit that the configuration bit for selecting to realize combination logic function, the correct coding information checking position corresponding with configuration bit and combination sequential function are selected simultaneously;
Four groups of d type flip flops (3) receive four tunnel information bits respectively, and described d type flip flop (3) of often organizing comprises two d type flip flops (3);
D type flip flop (3), for the road information bit according to reception, the duty of stored configuration circuit, realizes the sequential logic function of required configuration circuit, and exports to an XOR gate (8);
Four groups of d type flip flops (3) export to four XOR gate (8) respectively;
Each XOR gate (8), whether consistent for judging the output of two d type flip flops (3) inputted, determine whether sequential logic function breaks down, if the output of two d type flip flops (3) is identical, export high level, sequential logic function breaks down, if the output of two d type flip flops (3) is different, output low level, sequential logic function does not have fault;
Described four road configuration bits input to the configuration end that four 2 are selected the MUX (9) of 1 respectively;
2 select 1 MUX (9), for the configuration bit according to input, determine the output of logical block (10), if configuration bit selects Combinational logic output, then export a road information bit corresponding in 4 inputs look-up table unit (1); If configuration bit selects Sequential logic output, then export the output of a d type flip flop (3) corresponding with a described road information bit, a described d type flip flop (3) is one in one group of d type flip flop (3) corresponding with a described road information bit;
Check digit generative circuit (4), for being transformed to 3 road Berger codes check bit by 4 tunnel information bits;
Comparer (6), for comparing correct coding information checking position and Berger codes check bit to judge whether combination logic function produces fault, if identical, output low level, combination logic function does not have fault, if different, what export is high level, and sequential logic function breaks down;
Or door (7), for receiving sequential logic functional fault assay that four XOR gate (8) export and the combination logic function syndrome check result that comparer (6) exports, and it is carried out or logic, whether decision logic unit (10) breaks down, if one in four XOR gate (8) the sequential logic function exported breaks down, or the combination logic function that comparer (6) exports breaks down, export high level, logical block (10) breaks down; If the sequential logic function that four XOR gate (8) export all does not have fault, the combination logic function that comparer (6) exports simultaneously does not have fault, output low level yet, and logical block (10) does not have fault.
2. the on-line checkingi logical block of a kind of hardware circuit according to claim 1, is characterized in that, the figure place formula of Berger codes check bit is k=[log
2(i+1)], wherein, i is the figure place of input information bit, and k is the way of the Berger codes check bit exported.
3. the on-line checkingi logical block of a kind of hardware circuit according to claim 1 and 2, is characterized in that, often organize d type flip flop (3) and adopt two mode field, namely the input of two d type flip flops (3) is identical.
4. the on-line checkingi logical block of a kind of hardware circuit according to claim 1, it is characterized in that, check digit generative circuit (4) comprises full adder (4-1), a half adder (4-2), No. two half adders (4-3), phase inverter (4-4), No. two phase inverters (4-5) and No. three phase inverters (4-6)
3 input ends of full adder (4-1) are respectively as 3 tunnel information bit input ends of check digit generative circuit (4), the low order carry end C1 of full adder (4-1) connects an input end of a half adder (4-2), one's own department or unit of full adder (4-1) adds the input end being connected No. two half adders (4-3) with S1 entirely, another input end of a half adder (4-2) connects the carry digit C2 of No. two half adders (4-3), another input ends of No. two half adders (4-3) is as the 4th tunnel information bit input end of check digit generative circuit 4
The carry digit C2 of a half adder (4-2) connects the input end of a phase inverter (4-4), the false add of a half adder (4-2) and number S2 hold the input end of connection No. two phase inverters (4-5), the false add of No. two half adders (4-3) is connected the input end of No. three phase inverters (4-6) with number S2
The output terminal of the output terminal of a phase inverter (4-4), the output terminal of No. two phase inverters (4-5) and No. three phase inverters (4-6) is all as 3 Berger codes check bit output terminals of check digit generative circuit (4).
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