CN101674089B - High-speed 8B/10B coder, decoder and processing method thereof for error input - Google Patents
High-speed 8B/10B coder, decoder and processing method thereof for error input Download PDFInfo
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Abstract
The invention provides a high-speed 8B/10B coder, a decoder and a processing method thereof for error input. The coder comprises a data character precoding module, a RD calculating module and a data character precoding correction module, and the coder adopts a pipeline structure and a parallel processing method; the data character precoding module, the data character precoding correction module and the RD calculating module are respectively precoded and then post collected; the data character precoding module precodes input data in first-stage flow water, and calculates whether the current input code word can cause RD to turn by a RD_turn module; the RD calculating module calculates a RD value passing through the code word in second-stage flow water, and calculates the obtained RD value by using the former clock period to correct the precoded result of the current code word. The invention respectively adopts the pipeline structure and the parallel processing method when being applied in a high-speed serial interface, thus simplifying the circuit design, shortening the key path and improving speed.
Description
Technical field
The present invention relates to the transfer encoding technical field of digital communication, particularly a kind of high speed 8B/10B encoder and to the processing method of mistake input, i.e. (〉 1Gbps at a high speed) 8B/10B encoder and logic realization method thereof.
Background technology
The 8B/10B transfer encoding be by Albert X.Widmer and Peter A.Franaszek nineteen eighty-three be to propose in 4486739 the United States Patent (USP) " Byte Oriented DC Balanced(0,4) 8B/10B Partition Block Transmission Code " at publication number.This transfer encoding transmission bandwidth is little, transition density is high, the characteristics such as edge transition are arranged repeatedly in the code word run length, each code word, thereby is easy to the Fast synchronization alignment, dc balance.Dc balance refer to encode " 0 " and " 1 " quantity of rear data is consistent substantially, can avoid the input of receiver that dc shift is arranged, and like this driving of AC coupled load, long cable and optical-electric module is become possibility.So the dc balance technology is widely used in the high-speed serial bus.
Along with more and more higher to the requirement of serial line interface volume of transmitted data and speed, the speed of the Code And Decode of 8B/10B also there has been higher requirement.Publication number is that the patent " based on the 16B/20B encoder logic implementation method of two 8B/10B encoders " of CN1300971C and United States Patent (USP) " 8B/10B Encoder System And Method " that publication number is 6295010B1 all are to come raising speed by a plurality of encoder of Parallel Implementation, can increase like this area of chip.Publication number is that 6977599 United States Patent (USP) " 8B/10B Encoding And Decoding for High Speed Applications " and publication number are that 6911921 United States Patent (USP) " 5B/6B-T; 3B/4B-T and Partitioned 8B/10B-T and 10B/12B Transmission Codes; and Their Implementation for High Operating Rates " then is the speed that improves single 8B/10B encoder by improving circuit structure, but it mainly adopts combinational logic to realize Code And Decode, has very dark logical depth, cause critical path oversize, thereby affected to a certain extent the speed of 8B/10B encoder, and the DC equilibrium problem of data flow when paying attention to all in the implementation of 8B/10B encoder that the coding of data character and the control of DC balance ignored control character and the transmission of data character interval.
Summary of the invention
The object of the invention is to, overcome the problems referred to above that the 8B/10B encoder exists in the prior art, thus the processing method that a kind of high speed 8B/10B encoder is provided and mistake is inputted, to adapt to the demand of high-speed interconnect.
In order to solve the problems of the technologies described above, the invention provides a kind of 8B/10B encoder based on pipeline organization and parallel processing technique.At first, during this 8B/10B encoder transfer encoding, with coding module and RD(running disparity) computing module is separately, in first order flowing water, the input data are carried out precoding, and calculate current enter code word and whether can cause RD to overturn, in the streamline of the second level, calculate through the RD value behind the current enter code word, and the RD value of utilizing a clock cycle to calculate gained is come the precoding result of current enter code word is revised; Then, when this 8B/10B encoder is encoded to 8B/10B, do not need to judge first that the input data are control character or data character, but simultaneously it is encoded according to the coding rule of data character and control character respectively, the control character flag bit K according to input selects output to two kinds of codings again.Thereby, when input is control character, also can guarantee the dc balance of the data character coding of itself and front and back, then only it is carried out the data character coding in the implementation method of present 8B/10B encoder, do not consider simultaneously the problem to the control character coding; At last, during this 8B/10B decoder is decoded to 8B/10B, be divided into decoding, error detection (the unbalanced detection and the code word error detection that comprise code stream) and character types are judged (data character or control character) several parts, in the first order streamline 10 bits input data are carried out 6B/5B decoding and 4B/3B decoding, and the lack of uniformity of calculating 6B and 4B data, carry out the code word error detection in the streamline of the second level, character types are judged and RD calculates and lack of uniformity is judged and decoded result is selected, and in the implementation method of present 8B/10B decoder, only detected the lack of uniformity mistake of code stream, and ignored judgement to the code word type, and the vicious situation of enter code word, just in some open papers, mention error character is sorted out, then with the method for independent combinational logic realization to the differentiation of wrong numeral.The present invention adopts in respectively to 6B and 4B codeword decoding 6B code and the 4B code to this input to put the error flag position, then the decision logic 10B code word code word mistake whether of judging input by simple combinational logic again according to the value of its error flag position.
Specifically, in order to solve the problems of the technologies described above, the invention provides a kind of high speed 8B/10B encoder, comprise: data character precoding module 10a, control character precoding module 10b, RD_turn computing module 20a, RD computing module 20b and data character precoding correcting module 30a and control character precoding correcting module 30b is characterized in that: this high speed 8B/10B encoder adopts pipeline organization and method for parallel processing;
Described data character precoding module 10a and data character precoding correcting module 30a, RD computing module 20b carry out respectively precoding and rear correction, whether described data character precoding module 10a carries out precoding to current enter code word in first order flowing water, and calculate current enter code word by RD_turn computing module 20a and can cause RD to overturn; Described RD computing module 20b calculates input traffic through the RD value behind the current enter code word in the streamline of the second level, and the RD value of utilizing a clock cycle to calculate gained is come the precoding result of current enter code word is revised;
Described data character precoding module 10a is connected to data character precoding correcting module 30a and output by first order register; Described RD_turn computing module 20a is connected to RD computing module 20b and output by first order register; Described RD computing module 20b Output rusults is connected to data character precoding correcting module 30a and control character precoding correcting module 30b and RD computing module 20b as their input signal by second level register.
A kind of improvement as technique scheme, described encoder is encoded simultaneously according to the coding rule of data character and control character respectively, and described encoder also comprises control character precoding module 10b, control character precoding correcting module 30b and data/control character selection module 40; Described data character precoding correcting module 30a and control character precoding correcting module 30b connection data/control character is selected module 40, and described data/control character selects module 40 according to the control character flag bit K that inputs two kinds of codings to be selected output.
When this 8B/10B encoder carries out the 8B/10B coding, do not need to judge first that the input data are control character or data character, but simultaneously it is encoded according to the coding rule of data character and control character respectively, control character flag bit K according to input selects output to two kinds of codings again, thereby, when input is control character, also can guarantee the dc balance of the data character coding of itself and front and back.
As another improvement of technique scheme, during precoding, give tacit consent to current RD value for negative, described data character precoding module 10a carries out 5B/6B coding and 3B/4B coding with current enter code word as data character; Described control character precoding module 10b encodes current enter code word as control character, and calculates input traffic through the change information of RD behind the current enter code word.
As another improvement of technique scheme, described data character precoding correcting module 30a and control character precoding correcting module 30b are used for coming according to the RD value that upper one-period calculates gained and deposits second level register in the rear correction of control coding.
In order to solve the problems of the technologies described above, the present invention also provides a kind of high speed 8B/10B decoder, comprise flag bit computing module 60 and lack of uniformity calculating and the unbalanced error detection module 80 such as data decode module 50, lack of uniformity, it is characterized in that: this high speed 8B/10B decoder adopts the structure of streamline and parallel processing, can decode simultaneously and detect the unbalanced mistake of code stream; The flag bit computing modules 60 such as described data decode module 50 and lack of uniformity, lack of uniformity calculate and unbalanced error detection module 80 is used for respectively enter code word is decoded and unbalanced error detection;
Described data decode module 50 is decoded to enter code word in first order streamline, if be input as the efficient coding code word, it is decoded according to coding rule, if be input as the invalid code code word, then it is decoded as a fixing error flag code word, and obtains calculating and the needed flag bit of unbalanced error detection module 80 calculating for lack of uniformity by flag bit computing modules 60 such as lacks of uniformity;
Described lack of uniformity is calculated and unbalanced error detection module 80 carries out in the streamline of the second level that lack of uniformity is judged and the result's of decoding RD is calculated, and utilizes the RD value of a clock cycle calculating gained to judge whether to occur unbalanced mistake;
The input data communication device is crossed first order register and is connected to the flag bit computing modules 60 such as described data decode module 50 and lack of uniformity, in first order streamline, 10 bits input data are carried out 6B/5B decoding and 4B/3B decoding, and the lack of uniformity of calculating 6B and 4B data, the output of the flag bit computing modules 60 such as described lack of uniformity is connected to by second level register that lack of uniformity is calculated and unbalanced error detection module 80, and is re-used as the input signal of lack of uniformity calculating and unbalanced error detection module 80 after latching by the value that third level register calculated the RD of gained with a upper clock cycle.
As a kind of improvement of technique scheme, described 8B/10B decoder also comprises code word error detection and character types judge module 70 and output data selection module 90;
In the 8B/10B coding rule, the efficient coding of data character has 440 kinds of combinations, and the efficient coding of control character has 24 kinds of combinations, i.e. 464 kinds of combinations of efficient coding result, and the 10B code word then has 2
10Plant combination, totally 1024 kinds of combinations namely have as a result code word of 560 kinds of invalid code;
Described code word error detection and character types judge module 70, whether the enter code word for detection of encoder is as a result code word of invalid code, carry out the code word error detection, and be used for judging that enter code word is data character or control character before encoding, carry out the code word type and judge;
Described output data selection module is used for according to the unbalanced error flag of the output position of lack of uniformity calculating and unbalanced error detection module 80 code word or the fixing error flag code word of decoding being selected output;
Described code word error detection and character types judge module 70 carry out the code word error detection in the streamline of the second level, detect whether wrong enter code word of 6B in the enter code word that a upper cycle first order streamline receives and 4B code word, and according to testing result to error flag position 0 or 1, the 10B enter code word code word mistake whether of judging the input that a upper cycle first order streamline receives by the simple combinational logics in code word error detection and the character types judge module 70 again according to the value of its error flag position of the decision logic in code word error detection and the character types judge module 70 then.
In the implementation method of described 8B/10B decoder, not only detected the lack of uniformity mistake of code stream, but also the code word type has been judged, and the vicious situation of identification enter code word; During the decoding of described 8B/10B decoder, described lack of uniformity judgement and RD computing module can not only detect the lack of uniformity mistake of code stream, but also the code word type is judged, and the vicious situation of identification enter code word, but the RD of current enter code word calculates only relevant with the input of current enter code word, and is irrelevant with the RD of a upper code word, do not affect the RD calculating of back code word and the unbalanced detection of back code word, embodied wrong indiffusion function.This function is that present 8B/10B decoder is unexistent.
As another improvement of technique scheme, described data decode module 50 is also for generation of 5 flag bits; Described code word error detection and character types judge module 70 are judged code word mistake and code word type by these flag bits;
Described 5 flag bits comprise: 4B code error flag position code_err4 is to represent that the 4B code word of inputting made a mistake at 1 o'clock; 6B code error flag position code_err6 is to represent that the 6B code word of inputting made a mistake at 1 o'clock; P_28 represents that the code word of inputting is " 001111 " or " 110000 "; P1 represents that the 6B code word of inputting is " 111010 " or " 000101 " or " 110110 " or " 001001 " or " 101110 " or " 010001 " or " 011110 " or " 100001 "; P2 represents that the 4B code word of inputting is " 1000 " or " 0001 ";
By 6B code error flag position code_err6 and 4B code error flag position code_err4 signal mutually or obtain code word error flag position code_err, namely code_err=code_err6|code_err4 if the code_err signal is 1, then judges the code word mistake;
By flag bit p_28, flag bit p1, flag bit p2 is according to formula K=p_28| (p1﹠amp; P2) obtain code word type code position K, if the K signal is 1, then former code word is control character; Be 0, then former code word is data character.
A kind of preferred as technique scheme, described lack of uniformity calculate and unbalanced error detection module 80 in, signal E_Dx3 and p4 as or the input of door OR1, its output is inputted as the selection signal of the MUX MUX1 of alternative; The input of E_D7 and p6 conduct or door OR2, its output is as the selection signal input of the MUX MUX2 of alternative; Disp6 and RD are as the two paths of signals input of MUX MUX2 and the XOR gate XOR2 of alternative; The output signal rd of alternative MUX MUX2 and disp4 signal are as two signal inputs of XOR gate XOR1; The output signal rd of alternative MUX MUX2 and disp4 are as the two paths of signals input of alternative MUX MUX1; P4 and p6 signal are inputted as the signal of inverter N1 and inverter N2 respectively; The output signal of alternative MUX MUX1 is as the D signal input part of d type flip flop D1, and its output Q end is the signal input of alternative MUX MUX2 and XOR gate XOR2 as the RD signal; The clk termination clock signal of d type flip flop D1; The output conduct of inverter N1 and XOR gate XOR1 and two input signals of door AND1; The output conduct of XOR gate XOR2 and inverter N2 and two input signals of door AND2; With door AND1 and with the output signal of door AND2 as or the input signal of door OR3, it is output as the RD_err signal.
Preferred as another of technique scheme, the flag bit that the flag bit computing modules 60 such as described lack of uniformity produce comprises:
The E_D7 flag bit represents to input the 6B code word and is " 000111 " or " 111000 ";
The E_Dx3 flag bit represents to input the 4B code word and is " 0011 " " 1100 ";
Whether the number of " 0 " and " 1 " of p4 sign note bit representation input 4B code word equates that equal then p4 is 1, otherwise is 0;
Whether the number that the p6 flag bit represents to input " 0 " and " 1 " of 6B code word equates that equal then p6 is 1, otherwise is 0;
Disp4 is that 1 flag bit represents the quantity of " 1 " in the mark input 4B code stream greater than the quantity of " 0 ", is that the quantity of " 0 " in 0 expression 4B code stream is greater than the quantity of " 1 ";
Disp6 is that 1 flag bit represents the quantity of " 1 " in the mark input 6B code stream greater than the quantity of " 0 ", is that the quantity of " 0 " in 0 expression 6B code stream is greater than the quantity of " 1 "; But, when input 6B code word is " 111000 " or " 000111 ", put p6=0, wherein, when being " 111000 ", input 6B code word puts disp6=1, when being " 000111 ", input 6B code word puts disp6=0; When input 4B code word is " 1100 " or " 0011 ", put p4=0, wherein, when being " 1100 ", input 4B code word puts disp4=1, when being " 0011 ", input 4B code word puts disp4=0.
In order to solve the problems of the technologies described above, it is a kind of based on the processing method of high speed 8B/10B encoder to the Code And Decode of mistake input that the present invention also provides, and the method may further comprise the steps:
(1) when control character flag bit K is 1, and enter code word is not when being 12 control characters stipulating in the 8B/10B coding rule, the enter code word signal that encoder is described is wrong, this moment, data character precoding module 10a encoded the enter code word unification according to the 10B code of a direct current equilibrium, and described direct current equilibrium refers to through the quantity of " 0 " and " 1 " in the serial data bit stream behind the coding balanced.And through passing to control character precoding correcting module 30b behind the one-level register, select module 40 through passing to data/control character after revising, and finally select coding result output by the K signal.
When (2) the current enter code word input signal of decoder was wrong, if current enter code word does not belong to the coding result scope of 8B/10B coding schedule, then data decode module 50 fixedly was decoded as a balanced code word of fixing direct current with current enter code word; A described specific character can option table 3 in control character source code arbitrarily.If the enter code word direct current of current enter code word and a upper clock cycle is unbalanced, all be that " 0 " is Duoed than " 1 " or all is that " 1 " is more than " 0 " in the current enter code word of the unbalanced finger of described direct current and the enter code word of a upper clock cycle.Then exporting the unbalanced error flag position that data selection module 90 is calculated according to lack of uniformity and unbalanced error detection module 80 produces selects same specific character as output.
Regular coding when adopting dc balance code word of the present invention as the encoder input error, and the fixedly decoding during as the decoder input error with the corresponding true form of the fixed codeword of this dc balance are so that the enter code word of upper-layer protocol identification error.
The present invention has stipulated that the coding " 0011110010 " of K28.4 or " 1100001101 " (low level in a front high position rear) are the error flag of encoder; The source code of K28.4 " 10011100 " (high-order at front low level rear) is the error flag code of decoder.During the 8B/10B coding, be that 1 explanation input is control character if control character flag bit K occurs, but enter code word is not when being 12 control characters in the coding rule, illustrates that then input code makes mistakes, just be fixed this moment encodes according to K28.4; During the 8B/10B decoding, if input code detects mistake, then be fixed and be decoded as K28.4, so just can guarantee to have when the encoder input code dc balance of the transmission code stream of staggering the time, and can make coder-decoder simple in structure, also being convenient to the mistake of upper-layer protocol identification and processing enter code word, and being not limited to K28.4 for the code word of error identification, can also be other code words that possess non-data characters coding of direct current equilibrium.Innovation of the present invention is to come coding and decoding enter code word mistake with a balanced code word of fixing direct current, and this is that existing 8B/10B encoder does not have.
The present invention adopts streamline and technology parallel processing, and Code And Decode was finished within two cycles, has improved the speed of encoder; Adopt the RD value after first cycle is carried out current enter code word precoding and the current enter code word of calculating process in the cataloged procedure, RD result after the upper code word of process that second period obtains according to upper one-period again revises precoding, and calculates the RD of next cycle.Shorten critical path, accelerated the speed of encoder; In the decode procedure, in the unbalanced testing process of code stream the time, run into the code word of unbalanced mistake after, with wrong code word Unified coding, give upper-layer protocol and process, transmission just need not be interrupted like this, and the RD of correct calculated for subsequent code word, realized wrong indiffusible function.
The invention has the advantages that encoder of the present invention is applied in the HSSI High-Speed Serial Interface, all adopt pipeline organization and method for parallel processing, thereby simplified circuit design, shortened critical path, and improved speed.
Encoder among the present invention, adopt the method for precoding and rear correction to raise the efficiency, avoided the process that just can encode after obtaining current RD value, and input character is used as data character and control character is encoded simultaneously, last according to the K signal of input two kinds of codings are selected output again, can guarantee that like this output code flow accomplishes that fully direct current is balanced; Decoder among the present invention has adopted particular electrical circuit, energy error detecting code character error and unbalanced mistake, thus realize wrong indiffusion; Regular coding when adopting the dc balance code word as the encoder input error, and the fixedly decoding during as the decoder input error with the corresponding true form of the fixed codeword of this dc balance are so that the enter code word of upper-layer protocol identification error.In a word, the present invention is simpler, saves logical resource, helps to reduce chip area, and the present invention also has correct code word is carried out the function that the code word type is judged output, and this also is the existing not available function of 8B/10B decoder.Code word error-detecting method among the present invention also is different from the method that existing open paper proposes.In addition, the present invention has also gone out its character types to the correct codeword decoding of input.
Description of drawings
Fig. 1 is existing 8B/10B coding and decoding signal flow graph;
Fig. 2 is 8B/10B coding and decoding signal flow graph of the present invention;
Fig. 3 is the structured flowchart of the exemplary coder that adopts the 8B/10B transfer encoding and encode;
Fig. 4 is the signal flow graph of the exemplary coder that adopts the 8B/10B transfer encoding and encode;
Fig. 5 is the structured flowchart of the exemplary decoder that adopts the 8B/10B transfer encoding and decode;
Fig. 6 is the signal flow graph of the exemplary decoder that adopts the 8B/10B transfer encoding and decode;
Fig. 7 is for being used for judging the state transition graph of RD state;
Fig. 8 is the circuit diagram of unbalanced calculating and detection module in the decoder.
Embodiment
The present invention will be further described below in conjunction with the drawings and specific embodiments.
8B/10B encoder as shown in Figure 3 comprises the two-stage streamline, and wherein first order streamline comprises data character precoding module, control character precoding module, RD_turn computing module; Second level streamline comprises: data character precoding correcting module, control character precoding correcting module, RD computing module, data/control character are selected module.Described data character precoding module and data character precoding correcting module carry out respectively precoding and the correction of 5B/6B and 3B/4B to the data character.The eight bit data HGFEDCBA of input sends in three modules of first order streamline through register, and a control character Kin of input is sent to RD computing module in the streamline of the second level by the two-stage register; The result of calculation of data and control character RD_turn computing module is sent to RD computing module in the streamline of the second level by register, and the result of calculation RD_next of RD computing module outputs to register; The coding result of data character precoding module is connected to data character precoding correcting module by register, the coding result of control character precoding module is sent to control character precoding correcting module by register, sends into again in RD computing module and data character and the control character precoding correcting module through the RD_next signal of register; Guide data character and control character are revised precoding, and data character and the revised result of control character precoding select output through a selector by the K signal.
Described cataloged procedure has been introduced parameters R D(running disparity) represent degree of unbalance.Wherein RD+ represent " 1 " in the code word number more than the number that equals " 0 ", unnecessary the equal'sing of number " 1 " the number of " 0 " in the upper code word of " RD-" expression.RD by a upper code word selects 10bit code word corresponding to current enter code word as output.Encode for data character, the 8bit data are divided into low 5 and high 3, respectively it is carried out 5B/6B coding and 3B/4B coding, the 5B/6B codes selection be the RD that a upper byte code produces, and that the 3B/4B codes selection is the encode rd of generation of the adjacent 5B/6B in front.The RD value that whole byte code produces is obtained by the 3B/4B coding.Such as following table 1,2 and 3 listed:
Table 1
Table 2
Table 3
According to the code word identical or step-by-step negate of RD+ with the RD-coding, code is divided into neutral code and polar code.Wherein neutral code refers to that the coding result of this yard only has a kind of possible result, and the number of " 0 " equals the number of " 1 " in this coding; Polar code refers to the difference according to RD, and coding has two kinds of different possible outcomes.
As shown in Figure 4 the code device signal flow graph, in order to accelerate encoder speed, do not judge that first the input data are control character or data character, parallel to the input data according to control character and data character encode simultaneously, the calculating of RD, according to the Kin signal it is selected output more at last.First order module is carried out precoding to enter code word, is divided into 5B/6B precoding, 3B/4B precoding and the control character precoding of data character.During precoding all the situation according to RD-enter code word is encoded, (what be used for respectively indicating 5B/6B coding and 3B/4B coding such as p_56 and p_34 is neutral yard or polar code to obtain code word pre_abcdei, pre_fghj, c_pre_abcdeifghj and some flag bits in the middle of a group; Whether rd_turn_56 is used for indicating through the rd behind the 5B/6B coding opposite with input RD, and 1 expression is opposite, and 0 expression is identical).Calculate respectively in the time of precoding through the RD behind the current enter code word and whether want negate with respect to the RD of a upper code word.In like manner need simultaneously input character to be calculated respectively RD_turn as control character and data character.In the module of the second level, according to the RD of a upper code word, middle code word is revised.Data character precoding correcting module is divided into the correction of 5B/6B coding and the 3B/4B coding is revised.In 5B/6B coding correcting module, input RD and p_56 are control bits, if RD﹠amp; P_56=1, then exporting 6bit code abcdei is middle code word step-by-step negate., otherwise output equals middle code word.In the 3B/4B coding correcting module, if code word is not equal to 1110, rd and p_34 as control bit, if rd﹠amp in the middle of the 4bit; P_34=1, then exporting 4bit code fghj is code word step-by-step negate in the middle of the 4bit, otherwise output equals middle code word; If code word is 1110 in the middle of the 4bit, this moment, 5B/6B coding revised output e, i and rd, p_34 were as control bit, if
Then export fghj=1000, if
Then export fghj=0111, if otherwise rd﹠amp; P_34=1, fghj=0001 then, fghj=1110 in all the other situations.In the control character precoding correction, RD is control bit, if RD=1 then is output as the middle code word step-by-step of 10bit negate, otherwise output equals middle code word.By Kin revised control character coding and data character coding are selected as output, and selected that data character overturning mark position or control character overturning mark position were carried out XOR as final RD_turn with the RD value in a upper cycle of process register and obtain new RD value.
8B/10B decoder as shown in Figure 5 also comprises two-stage flowing water, and wherein first order streamline comprises input data decode module, the 6B of input data and the lack of uniformity computing module of 4B code; Second level streamline comprises code word error detection and character types judge module, unbalanced calculating and detection module and output data selection module.
Described input data decode module is divided into 6B/5B decoding and 4B/3B decoding, and the result of decoding sends into code word error detection and character types judge module and the output data selection module of second level flowing water through register; The result of calculation of the 6B of input data and the lack of uniformity computing module of 4B code is sent into unbalanced calculating and unbalanced error detection module through register, the unbalanced calculating of process and its output of unbalanced error detection are as the input of output data selection module, and this signal is through the again input of conduct oneself after register.8B/10B decoder signal flow graph shown in Figure 6, in input data decode module, if 6B and 4B are input as the valid data behind the coding in table 1, the table 2, be 5B and 3B to it according to decoding data in the table then, when input 6B code is 001111 or 110000, it is decoded as 11100, is input as misdata otherwise look, put respectively code_err6 or code_err4 and be 1 and be used for mark 6B code or 4B code mistake; If one of them is wrong for 6B or 4B data, then whole data are idle character, i.e. code_err=code_err6|code_err4.
By table 3 can shown in the coding of the spcial character seen the coding of eight spcial characters of two characteristics: the first, K28.x is arranged, wherein abcdei is 001111 or 110000, and this being coded in definitely is impossible in the data encoding; 2.; Completely contradict to the 4B code selection of " 7 " with the data character codes selection in second, the kx.7 coding, 1000 or 0111 coding appears in the fghj in spcial character, and can adopt 0001 or 1110 under the kindred circumstances in data encoding.Thereby p_28 is set,, p1 and p2 be used for sign and judge whether input is 12 effective control codes., when abcdei was 001111 or 110000, putting p_28 was 1; When abcdei can be decoded as D23,27,29,30 o'clock, putting p1 was 1, when fghj is 1000 or 0111, was 1 with p2 set; P_28, p1, p2 are 0 in all the other situations; As p_28| (p1﹠amp; P2)=1 o'clock, the input data just for the control data, are put K=1.5 flag bits of unbalanced degree computing module output of 6B code and 4B code, wherein, p6,, p4 is respectively the polarity mark position of 6B code and 4B code, if the number of " 1 " and " 0 " equates in this code word, putting it is 1, represents that this code is neutral code; Otherwise be set to 0, represent that this code is polar code.When code word was neutrality, corresponding disparity flag bit disp was just effective.When the number of " 1 " was more than the number of " 0 " in the code stream, disp was 1; Otherwise, then be 0.
In order to prevent similarly should to be encoded to 111000, and error coded is 000111 o'clock, detects not the out situation of code error, must to abcdei be 000111 and 111000 and fghj be 1100 and did special processing at 0011 o'clock.Although their " 0 " and " 1 " number equate, its corresponding p=0 must be set.When being input as 000111 or 0011, put disp6 and disp4 is 0; When being input as 111000 or 1100, put disp6 and disp4 is 1.So just can detect the unbalanced mistake of such yard, but since force mark these four neutral codes be polar code, and changed corresponding disp sign, this can cause the RD computing module to make a mistake, because these four code books are neutral code, RD when the RD of data should keep inputting afterwards through them, but become disp6 and disp4 this moment.In order to prevent this wrong the generation, also being provided with two flag bits is E_D7 and E_Dx3.When input abcdei was 000111 or 111000, E_D7 was set to 1, otherwise it is 0; When input fghj was 0011 or 1100, E_Dx.3 was set to 1, otherwise it is 0.
Unbalanced calculating and detection module in the decoder shown in Figure 8, wherein unbalanced calculating section as shown in Figure 7, the polarity that presents after the coded data of positive polarity and negative polarity is transmitted in the transfer of data just is the coded data polarity of self, and the data polarity after the neutral coded data transmission is then inherited the polarity of data.In 8B/10B decoder shown in Figure 5, if P6 or E_D7 are 1, data abcdei is neutral code; If P4 or E_Dx3 are 1 o'clock, data fghj is neutral code.So with they or as selecting signal.In the unbalanced test section, if RD equate with disp6, illustrate that then the unbalanced mistake of DC has occured for the abcdei of current data and the fghj of upper data; If rd equates with disp4, illustrate that then the balanced mistake of DC has occured for the abcdei of current data and current data fghj, namely
Be 1 and detected the unbalanced mistake of DC, but because when p=1, the disp invalidating signal, thereby
With
Only have just effective when p4=0 and p6=0 respectively.
This module has wrong indiffusion function.Owing to when n+1 code carried out the unbalanced detection of DC, need to use the RDn+1 that n input code calculates.If n code is wrong, the RDn+1 that is then obtained by it also is wrong, if this moment, n+1 input code was a correct non-neutral code, then owing to used wrong RDn+1, decoder can mistake this correct code is detected be the unbalanced error code of DC, its decoding is output as 10011100, but while RDn+2 equals the RD of n+1 code, then is correct.Thereby recycling RDn+2, just can not make a mistake when detecting to n+3 code; If n+1 input code is correct neutral code, and because this moment p4, p6 are 0, decoder can not be detected. as wrong code, thereby can export correct decoded result, but wrong RDn+1 can propagate along with the neutral code of input, until run into a non-neutral code, just can be corrected to the RD of this non-neutral code, thereby obtain correct RD, code stream decoding device afterwards will be correct detects and decodes it.
In a word, when wrong in the input code flow, decoder can detect it, but may cause decoder that a correct code of back is judged as error code simultaneously.But the code stream of the detection that after this, decoder can both be correct and decoding back.Because the probability that makes a mistake of link is very little, and this minor issue fully can be by the protocol identification on upper strata, and is corrected by software, thereby this minor issue is very little on the impact of whole system performance.If but will be at this minor issue of hardware corrigendum, then need much more very logics the misdeem type of error code and the reason that leads to errors, thereby obtain correct code, correct RD, can make pipeline stall like this, greatly reduce transmission rate, so think that this there is no need.
In the output data selection module, just considered idle character during owing to decoding, and simultaneously the idle character of inputting has been decoded as K28.4, thereby exported when selecting and only need to consider that the situation that the unbalanced mistake of direct current occurs gets final product.If RD_err is 1, then put and be output as K28.4, otherwise, be output as decoded output.
The present invention comprehensively is achieved under the process conditions of SIMC 90nm through DC, and this encoder all can be carried out work in the 900MHZ frequency under various PVT conditions, and area is about 1500um
2The present invention can be applicable in the design of encoder of the above HSSI High-Speed Serial Interface of 5Gbps, has widely application scenarios.
It should be noted last that above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although with reference to embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1. high speed 8B/10B encoder, comprise: data character precoding module (10a), RD_turn computing module (20a), RD computing module (20b) and data character precoding correcting module (30a) and control character precoding correcting module (30b) is characterized in that: this high speed 8B/10B encoder adopts pipeline organization and method for parallel processing;
Described data character precoding module (10a) and data character precoding correcting module (30a), RD computing module (20b) carry out respectively precoding and rear correction, whether described data character precoding module (10a) is carried out precoding to current enter code word in first order flowing water, and can cause RD to overturn by the described current enter code word of RD_turn computing module (20a) calculating; Described RD computing module (20b) calculates input traffic through the RD value behind the current enter code word in the streamline of the second level, and the RD value of utilizing a clock cycle to calculate gained is come the precoding result of current enter code word is revised;
Described data character precoding module (10a) is connected to data character precoding correcting module (30a) and output by first order register; Described RD_turn computing module (20a) is connected to RD computing module (20b) and output by first order register; Described RD computing module (20b) Output rusults is connected to data character precoding correcting module (30a) and control character precoding correcting module (30b) and RD computing module (20b) as their input signal by second level register.
2. high speed 8B/10B encoder according to claim 1, it is characterized in that: described encoder is encoded simultaneously according to the coding rule of data character and control character respectively, and described encoder also comprises control character precoding module (10b) and data/control character selection module (40); Described data character precoding correcting module (30a) and control character precoding correcting module (30b) connection data/control character is selected module (40), and described data/control character selects module (40) according to the control character flag bit K that inputs two kinds of codings to be selected output.
3. high speed 8B/10B encoder according to claim 2 is characterized in that: during precoding, give tacit consent to current RD value for negative, current enter code word is carried out the 5B/6B coding as data character to described data character precoding module (10a) and 3B/4B encodes; Described control character precoding module (10b) is encoded current enter code word as control character, and calculates input traffic through the change information of RD behind the current enter code word.
4. high speed 8B/10B encoder according to claim 2, it is characterized in that: described data character precoding correcting module (30a) and control character precoding correcting module (30b) are used for coming according to the RD value that upper one-period calculates gained and deposits second level register in the rear correction of control coding.
5. high speed 8B/10B decoder, comprise flag bit computing module (60) and lack of uniformity calculating and the unbalanced error detection module (80) such as data decode module (50), lack of uniformity, it is characterized in that: this high speed 8B/10B decoder adopts the structure of streamline and parallel processing, can decode simultaneously and detect the unbalanced mistake of code stream; The flag bit computing modules (60) such as described data decode module (50) and lack of uniformity, lack of uniformity are calculated and unbalanced error detection module (80) is used for respectively enter code word is decoded and unbalanced error detection;
Described data decode module (50) is decoded to enter code word in first order streamline, if be input as the efficient coding code word, it is decoded according to coding rule, if be input as the invalid code code word, then it is decoded as a fixing error flag code word, and obtains calculating needed flag bit for lack of uniformity calculating and unbalanced error detection module (80) by flag bit computing modules (60) such as lacks of uniformity;
Described lack of uniformity is calculated and unbalanced error detection module (80) carries out in the streamline of the second level that lack of uniformity is judged and the result's of decoding RD is calculated, and utilizes the RD value of a clock cycle calculating gained to judge whether to occur unbalanced mistake;
The input data communication device is crossed first order register and is connected to the flag bit computing modules (60) such as described data decode module (50) and lack of uniformity, in first order streamline, 10 bits input data are carried out 6B/5B decoding and 4B/3B decoding, and the lack of uniformity of calculating 6B and 4B data, the output of the flag bit computing modules (60) such as described lack of uniformity is connected to by second level register that lack of uniformity is calculated and unbalanced error detection module (80), and is re-used as the input signal of lack of uniformity calculating and unbalanced error detection module (80) after latching by the value that third level register calculated the RD of gained with a upper clock cycle.
6. high speed 8B/10B decoder according to claim 5 is characterized in that: described 8B/10B decoder also comprises code word error detection and character types judge module (70) and output data selection module (90);
Described code word error detection and character types judge module (70), whether the enter code word for detection of encoder is as a result code word of invalid code, carry out the code word error detection, and be used for judging that enter code word is data character or control character before encoding, carry out the code word type and judge;
Described output data selection module is used for according to the unbalanced error flag of the output position of lack of uniformity calculating and unbalanced error detection module (80) code word or the fixing error flag code word of decoding being selected output;
Described code word error detection and character types judge module (70) carry out the code word error detection in the streamline of the second level, detect whether wrong enter code word of 6B code in the enter code word that a upper cycle first order streamline receives and 4B code, and according to testing result to error flag position 0 or 1, the 10B enter code word code word mistake whether of judging the input that a upper cycle first order streamline receives by code word error detection and the interior simple combinational logic of character types judge module (70) again according to the value of its described error flag position of the decision logic in code word error detection and the character types judge module (70) then.
7. high speed 8B/10B decoder according to claim 6, it is characterized in that: described data decode module (50) is also for generation of 5 flag bits; Described code word error detection and character types judge module (70) are judged code word mistake and code word type by these flag bits;
Described 5 flag bits comprise: 4B code error flag position code_err4 is to represent that the 4B code word of inputting made a mistake at 1 o'clock; 6B code error flag position code_err6 is to represent that the 6B code word of inputting made a mistake at 1 o'clock; P_28 represents that the code word of inputting is " 001111 " or " 110000 "; P1 represents that the 6B code word of inputting is " 111010 " or " 000101 " or " 110110 " or " 001001 " or " 101110 " or " 010001 " or " 011110 " or " 100001 "; P2 represents that the 4B code word of inputting is " 1000 " or " 0001 ";
By 6B code error flag position code_err6 and 4B code error flag position code_err4 signal mutually or obtain code word error flag position code_err, namely code_err=code_err6|code_err4 if the code_err signal is 1, then judges the code word mistake;
By flag bit p_28, flag bit p1, flag bit p2 is according to formula K=p_28| (p1﹠amp; P2) obtain code word type code position K, if the K signal is 1, then former code word is control character; Be 0, then former code word is data character.
8. high speed 8B/10B decoder according to claim 6, it is characterized in that, in described lack of uniformity calculating and the unbalanced error detection module (80), the input of signal E_Dx3 and p4 conduct or door OR1, its output is as the selection signal input of the MUX MUX1 of alternative; The input of E_D7 and p6 conduct or door OR2, its output is as the selection signal input of the MUX MUX2 of alternative; Disp6 and RD are as the two paths of signals input of MUX MUX2 and the XOR gate XOR2 of alternative; The output signal rd of alternative MUX MUX2 and disp4 signal are as two signal inputs of XOR gate XOR1; The output signal rd of alternative MUX MUX2 and disp4 are as the two paths of signals input of alternative MUX MUX1; P4 and p6 signal are inputted as the signal of inverter N1 and inverter N2 respectively; The output signal of alternative MUX MUX1 is as the D signal input part of d type flip flop D1, and its output Q end is the signal input of alternative MUX MUX2 and XOR gate XOR2 as the RD signal; The clk termination clock signal of d type flip flop D1; The output conduct of inverter N1 and XOR gate XOR1 and two input signals of door AND1; The output conduct of XOR gate XOR2 and inverter N2 and two input signals of door AND2; With door AND1 and with the output signal of door AND2 as or the input signal of door OR3, it is output as the RD_err signal.
9. high speed 8B/10B decoder according to claim 5, it is characterized in that: the flag bit that the flag bit computing modules (60) such as described lack of uniformity produce comprises:
The E_D7 flag bit represents to input the 6B code word and is " 000111 " or " 111000 ";
The E_Dx3 flag bit represents to input the 4B code word and is " 0011 " " 1100 ";
Whether the number of " 0 " and " 1 " of p4 sign note bit representation input 4B code word equates that equal then p4 is 1, otherwise is 0;
Whether the number that the p6 flag bit represents to input " 0 " and " 1 " of 6B code word equates that equal then p6 is 1, otherwise is 0;
Disp4 is that 1 flag bit represents the quantity of " 1 " in the mark input 4B code stream greater than the quantity of " 0 ", is that the quantity of " 0 " in 0 expression 4B code stream is greater than the quantity of " 1 ";
Disp6 is that 1 flag bit represents the quantity of " 1 " in the mark input 6B code stream greater than the quantity of " 0 ", is that the quantity of " 0 " in 0 expression 6B code stream is greater than the quantity of " 1 "; But, when input 6B code word is " 111000 " or " 000111 ", put p6=0, wherein, when input 6B code word is " 111000 ", put disp6=1, when input 6B code word is " 000111 ", put disp6=0; When input 4B code word is " 1100 " or " 0011 ", put p4=0, wherein, when input 4B code word is " 1100 ", put disp4=1, when input 4B code word is " 0011 ", put disp4=0.
10. one kind based on the processing method of high speed 8B/10B encoder to mistake input, and the method may further comprise the steps:
(1) when control character flag bit K is 1, and enter code word is not when being 12 control characters stipulating in the 8B/10B coding rule, the enter code word that encoder is described is wrong, data character precoding module this moment (10a) is encoded the enter code word unification according to the 10B code of a direct current equilibrium, and through passing to control character precoding correcting module (30b) behind the one-level register, select module (40) through passing to data/control character after revising, and finally select coding result output by the K signal;
When (2) the current enter code word of decoder was wrong, if current enter code word does not belong to the coding result scope of 8B/10B coding schedule, then data decode module (50) fixedly was decoded as a balanced code word of fixing direct current with current enter code word; If the enter code word direct current of current enter code word and a upper clock cycle is unbalanced, then exported data selection module (90) and select the balanced code word of described fixing direct current as output according to the unbalanced error flag position that lack of uniformity is calculated and unbalanced error detection module (80) produces.
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| CN103199866B (en) * | 2012-01-06 | 2017-03-15 | 上海华虹集成电路有限责任公司 | 8b/10b decoding circuits based on rd |
| CN103516477A (en) * | 2012-06-29 | 2014-01-15 | 华为技术有限公司 | Data transmission method and device |
| CN103138889A (en) * | 2012-12-05 | 2013-06-05 | 无锡华大国奇科技有限公司 | High-speed 8B/10B encoding device and coder |
| CN105263023B (en) * | 2015-10-26 | 2018-08-03 | 西安电子科技大学 | Network code stream real-time reception method based on high-speed decoding platform |
| CN107783922A (en) * | 2016-08-31 | 2018-03-09 | 深圳市中兴微电子技术有限公司 | A kind of data decoding method and device |
| CN109889306B (en) * | 2019-01-16 | 2021-12-17 | 中国航空工业集团公司洛阳电光设备研究所 | Encoding polarity calculation method for high-speed optical fiber digital transmission system |
| CN111030953B (en) * | 2019-12-04 | 2021-11-09 | 中国电子科技集团公司第五十八研究所 | Low-delay 8B/10B coding method and device |
| CN112865807A (en) * | 2021-01-11 | 2021-05-28 | 电子科技大学 | 8B/10B coding and decoding circuit with anti-radiation function |
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