CN104821721A

CN104821721A - Semiconductor structures for enhanced transient response in low dropout (LDO) voltage regulators

Info

Publication number: CN104821721A
Application number: CN201510057249.0A
Authority: CN
Inventors: G·卢夫
Original assignee: Intersil Americas LLC
Current assignee: Intersil Americas LLC
Priority date: 2014-02-05
Filing date: 2015-02-04
Publication date: 2015-08-05
Anticipated expiration: 2035-02-04
Also published as: CN104821721B; CN108964451A; CN108964451B

Abstract

Systems, semiconductor structures, electronic circuits and methods for enhanced transient response in Low Dropout (LDO) voltage regulators are disclosed. For example, a semiconductor structure for enhanced transient response in an LDO voltage regulator is disclosed, which includes a first current mirror circuit coupled to an input connection and an output connection of the LDO voltage regulator, a second current mirror circuit coupled to the input connection of the LDO voltage regulator. A first input of a first amplifier circuit is coupled to the second current mirror circuit, a second input of the first amplifier circuit is coupled to the output connection of the LDO voltage regulator, and a third input of the first amplifier circuit is coupled to a reference voltage. An input of a second amplifier circuit is coupled to an output of the first amplifier circuit, an output of the second amplifier circuit is coupled to the first current mirror circuit, an input of a third amplifier circuit is coupled to the output of the first amplifier circuit, and an output of the third amplifier circuit is coupled to the second current mirror circuit. In some implementations, the semiconductor structure is an adaptively-biased LDO voltage regulator formed in a power management integrated circuit (PMIC) or in a power supply on a semiconductor IC, wafer, chip or die.

Description

For the semiconductor structure of enhancement mode transient response in low voltage difference (LDO) pressurizer

The cross reference of related application

The title that the application relates on February 5th, 2014 and submits to is " semiconductor structure (SEMICONDUCTORSTRUCTURES FOR ENHANCED TRANSIENT RESPONSE IN LOWDROPOUT (LDO) VOLTAGE REGULATORS) for enhancement mode transient response in low voltage difference (LDO) pressurizer " and is incorporated to U.S. Provisional Patent Application sequence number 61/936,111 herein by reference.The title that the application also relates on February 28th, 2014 and submits to is " semiconductor structure (SEMICONDUCTOR STRUCTURES FOR ENHANCEDTRANSIENT RESPONSE IN LOW DROPOUT (LDO) VOLTAGEREGULATORS) for enhancement mode transient response in low voltage difference (LDO) pressurizer " and is incorporated to U.S. Provisional Patent Application sequence number 61/946,268 herein by reference.The application requires the rights and interests of U.S. Provisional Patent Application sequence number 61/936,111 and 61/946,268 at this.

Technical field

The present invention relates generally to low voltage difference (LDO) pressurizer, and relates in particular to the adaptive-biased LDO voltage stabilizer of the enhancement mode transient response utilized in semiconductor integrated circuit, wafer, chip or nude film.

Background technology

Using in " super current mirror " conventional LDO voltage stabilizer of designing, adjuster rises to by their adaptive-biased loop the time restriction that suitable operating point spends to the response speed of transient state.But these LDO voltage stabilizer adopt from the adaptive-biased feedback of the grid of their turn-on transistor, and therefore the width of their adaptive-biased feedback loop limits by the large grid capacitance of their conducting device.Therefore, the output voltage that the transient state of these LDO voltage stabilizer is brought out falls quite large.

Summary of the invention

An embodiment is for a kind of semiconductor structure for enhancement mode transient response in LDO voltage stabilizer.Described semiconductor structure is the LDO voltage stabilizer comprising the adaptive-biased input stage be formed on semiconductor integrated circuit, wafer, chip or nude film.Adaptive-biased signal is the feedback signal being coupled to the input of described level from the output of input stage (such as, the first gain stage).Therefore, the transient response of the adaptive-biased feedback loop of gained is obviously faster than the transient response of the main feedback loop of LDO voltage stabilizer.Or rather, the drive current to the output stage of LDO voltage stabilizer increases with the speed of the speed apparently higher than output current, to give the gate capacitance charges of turn-on transistor device.Therefore, the output voltage that the load transient of adaptive-biased LDO voltage stabilizer brings out falls the output voltage being significantly less than conventional LDO voltage stabilizer and falls (such as, if use relatively little output capacitor).

Accompanying drawing explanation

Should be understood that accompanying drawing only depicted example embodiment and not thus being considered as in scope have limited, by using accompanying drawing, described exemplary is described other with extra selectivity and details.

Fig. 1 is the schematic block diagram of electronic circuit, and described electronic circuit can be used for implementing an exemplary of the present invention.

Fig. 2 is the schematic block diagram of the second electronic circuit, and described second electronic circuit can be used for implementing the second exemplary of the present invention.

Fig. 3 is the schematic block diagram of the 3rd electronic circuit, and described 3rd electronic circuit can be used for implementing the 3rd exemplary of the present invention.

Fig. 4 is the schematic block diagram of the 4th electronic circuit, and described 4th electronic circuit can be used for implementing the 4th exemplary of the present invention.

Fig. 5 is the schematic circuit of exemplary semiconductor structure, and described semiconductor structure can be used for the electronic circuit described in the electronic circuit implementing to describe in Fig. 2 or Fig. 4.

Fig. 6 is the schematic circuit of exemplary semiconductor structure, and described semiconductor structure can be used for the electronic circuit described in the electronic circuit implementing to describe in Fig. 1 or Fig. 3.

Fig. 7 A and Fig. 7 B shows according to the analogue phase allowance performance curve of the structurized LDO voltage stabilizer of embodiment of the present invention and the correlogram of gain margin performance curve.

Fig. 8 shows the curve chart according to the simulation transient load response of the structurized adaptive-biased LDO voltage stabilizer of embodiment of the present invention.

Fig. 9 describes the curve chart according to the performance mode of embodiment of the present invention under the simulated operation condition of LDO voltage stabilizer.

Figure 10 is the schematic block diagram of the example system being configured to power management integrated circuit (PMIC), and described power management integrated circuit can be used for the semiconductor structure for enhancement mode transient response implemented according to one or more embodiments of the present invention.

Figure 11 is the schematic block diagram of the example system being configured to PMIC, and described PMIC can be used for the semiconductor structure for enhancement mode transient response implemented according to one or more embodiments of the present invention.

Figure 12 is the flow chart of the exemplary methods of operationthe of the adaptive-biased LDO voltage stabilizer described according to one or more embodiments of the present invention.

The list of reference numbers of primary clustering in accompanying drawing

100 electronic circuits

102 first amplifiers

104 noninverting inputs

106 nodes

108 resistor R1

110 resistor R2

112 anti-phase inputs

114 export

116 bias current control inputs

118 inputs

120 second amplifiers

122 current mirrors

124 export

126 the first transistor devices

128 transistor seconds devices

130 input terminals

132 lead-out terminals

134 capacitor C1

136 earth terminals

200 electronic circuits

201 inputs

202 first amplifiers

203 buffer amplifiers

204 noninverting inputs

205 export

206 nodes

208 resistor R1

210 resistor R2

212 anti-phase inputs

214 export

216 bias current control inputs

218 inputs

220 second amplifiers

222 current mirrors

224 export

226 the first transistor devices

228 transistor seconds devices

230 input terminals

232 lead-out terminals

234 capacitor C1

236 earth terminals

300 electronic circuits

302 first amplifiers

304 noninverting inputs

305 the 3rd amplifiers

306 nodes

307 third transistor devices

308 resistor R1

309 the 4th transistor units

310 resistor R2

312 anti-phase inputs

316 bias current inputs

318 inputs

319 inputs

320 second amplifiers

322 first current mirrors

324 export

325 export

326 the first transistor devices

328 transistor seconds devices

330 input terminals

332 lead-out terminals

334 capacitor C1

336 earth terminals

338 second current mirrors

400 electronic circuits

401 inputs

402 first amplifiers

403 buffer amplifiers

404 noninverting inputs

405 the 3rd amplifiers

406 nodes

407 third transistor devices

408 resistor R1

409 the 4th transistor units

410 resistor R2

412 anti-phase inputs

416 bias current inputs

418 inputs

419 inputs

420 second amplifiers

422 first current mirrors

424 export

425 export

426 the first transistor devices

428 transistor seconds devices

430 input terminals

432 lead-out terminals

434 capacitor C1

436 earth terminals

438 second current mirrors

500 semiconductor structures

501 transistor M8

502 first amplifiers

503 buffer amplifiers

504 noninverting inputs

505 the 3rd amplifiers

506 nodes

507 third transistor devices

508 resistor R1

509 the 4th transistor units

510 resistor R2

512 anti-phase inputs

514 export

515 export

520 second amplifiers

522 first current mirrors

526 the first transistor devices

528 transistor seconds devices

530 input terminals

532 lead-out terminals

534 capacitor C1

536 earth terminals

538 second current mirrors

600 semiconductor structures

601 transistor M8

602 first amplifiers

604 noninverting inputs

605 the 3rd amplifiers

606 nodes

607 third transistor devices

608 resistor R1

609 the 4th transistor units

610 resistor R2

612 anti-phase inputs

614 export

620 second amplifiers

622 first current mirrors

626 the first transistor devices

628 transistor seconds devices

630 input terminals

632 lead-out terminals

634 capacitor C1

636 earth terminals

638 second current mirrors

700a curve chart

700b curve chart

800 curve charts

802 2.176V

900 curve charts

902a performance curve

902b performance curve

904a performance curve

904b performance curve

906a performance curve

906b performance curve

908a performance curve

908b performance curve

1000 systems

1002 adaptive-biased LDO voltage stabilizer

1004 VLOGIC passages export connector

1006 sequencers

1008 AVDD boost controllers

1010 strobe pulse modulators

1012 voltage detectors

1014 numerical control potentiometers

1030 input terminals

1032 lead-out terminals

1100 systems

1102 adaptive-biased LDO voltage stabilizer

1130 voltage inputs

1132 voltages export

1136 earth terminals

1200 flow charts

1202 pieces

1204 pieces

1206 pieces

1208 pieces

1210 pieces

Embodiment

In the following detailed description, with reference to the accompanying drawing forming a part of the present invention, and wherein show by means of certain illustrative embodiment.But, will understand, other embodiment can be utilized, and the change of logic, machinery and electric aspect can be carried out.In addition, the method presented in accompanying drawing and specification should not be understood to limit the order that can perform respective actions.Therefore, following detailed description should do not explained in a limiting sense.In whole accompanying drawing, use same or similar reference number to refer to same or similar construction package or part as far as possible.

Embodiment as herein described is provided for the semiconductor structure of the enhancement mode transient response in low voltage difference (LDO) pressurizer.For an exemplary, semiconductor structure comprises the LDO voltage stabilizer with adaptive-biased input stage.Adaptive-biased signal is the feedback signal being coupled to the input of described level from the output of input stage (such as, the first gain stage).Therefore, the transient response of the adaptive-biased feedback loop of gained is obviously faster than the transient response of the main feedback loop of LDO voltage stabilizer.Or rather, the drive current to the output stage of LDO voltage stabilizer increases, so that the gate capacitance charges to turn-on transistor device with the speed of the speed apparently higher than output current.Therefore, the output voltage that the load transient of adaptive-biased LDO voltage stabilizer brings out falls the output voltage being significantly less than conventional LDO voltage stabilizer and falls (such as, if use relatively little output capacitor).

The embodiment of the semiconductor structure of the present invention being used for enhancement mode transient response can be formed in such as semiconductor integrated circuit (IC), wafer, chip or nude film.Therefore, such as, described semiconductor structure can be used as the LDO voltage stabilizer in IC power supply or power management IC (PMIC) or is combined with it.For example, can need high level, low ESR (ESR) capacity load and enhancing Power Supply Rejection Ratio (PSRR) performance product in use this type of IC power supply or PMIC.So, such as, in the IC power supply that can be used for smart phone or similar products for the semiconductor structure of the present invention of enhancement mode transient response or PMIC, described product uses relatively large (μ F scope), low ESR ceramic capacitor for power decoupling.In addition, some product may require that this type of semiconducter IC is embodied as the LDO voltage stabilizer relatively low output capacitance to suitable transient response, because this type of ldo regulator of supply digital circuit usually experiences the unexpected increase of load current.Therefore, the gained output voltage of LDO voltage stabilizer should be made to fall and to minimize (such as, 10mV to 30mV), to keep LDO voltage stabilizer appropriate circuitry performance at lower voltages.So, semiconductor structure of the present invention for enhancement mode transient response easily meets this type of performance requirement owing to obtaining adaptive-biased feedback from the output of the first gain stage in LDO voltage stabilizer, the bandwidth of adaptive-biased feedback loop is not limited by the large grid capacitance of turn-on transistor device, and bandwidth is limited in conventional LDO voltage stabilizer.

Fig. 1 is the schematic block diagram of electronic circuit 100, and described electronic circuit can be used for implementing an exemplary of the present invention.For example, electronic circuit 100 can be used for implementing the adaptive-biased LDO voltage stabilizer for the enhancement mode transient response in semiconductor structure, such as semiconductor integrated circuit (IC), wafer, chip or nude film.

With reference to the exemplary shown in figure 1, electronic circuit 100 (such as, LDO voltage stabilizer) comprises the first amplifier 102, and described first amplifier is the input stage of the error amplifier also served as in circuit 100.In this exemplary, the first amplifier 102 is voltage gain amplifiers, and its current offset level is by its output voltage control (such as, self biased amplifier).First input voltage (such as, reference voltage or Vref) is coupled to the noninverting input 104 of the first amplifier 102.In some embodiments, the first input voltage is the fixed reference potential produced in electronic circuit 100.In other embodiments, the first input voltage is variable reference voltage (such as, being changed by D/A converter).In some embodiments, the first input voltage produces in electronic circuit 100 outside, and is connected to input 104 by the pin of such as semiconducter IC or chip.Second input voltage (such as, feedback voltage or Vfb) from being connected to the node 106 of the first resistor 108 and the second resistor 110 (such as, resistive voltage divider) be connected to the anti-phase input 112 of the first amplifier 102, and the output voltage of the first amplifier 102 from the output 114 of the first amplifier 102 be coupled back the first amplifier 102 bias current control inputs 116 (namely, automatic biasing), and be also coupled to the input 118 of the second amplifier 120.In this exemplary, the second amplifier 120 is inverting transconductance amplifiers, and described second amplifier forms the drive current being used for current mirror output stage 122.Or rather, gate terminal and the drain terminal of the first transistor device 126 of current mirror output stage 122 are coupled in the output 124 of the second amplifier 120, and are also coupled to the gate terminal of the transistor seconds device 128 of current mirror output stage 122.The source terminal of the first transistor device 126 and transistor seconds device 128 is coupled to input terminal 130 (such as, the V of electronic circuit 100 _iN).The drain terminal of transistor seconds device 128 is coupled to the side (such as, relative with the side of node 106) of the first resistor 108 and lead-out terminal 132 (such as, the V of electronic circuit 100 _oUT).Lead-out terminal 132 is coupled in the side of capacitor 134 (such as, output capacitor), and the opposite side of capacitor 134 is coupled to the earth terminal 136 (such as, GND or circuit ground) of electronic circuit 100.Earth terminal 136 is also coupled in second side (such as, relative with the side of node 106) of the second resistor 110.

In this exemplary, the output current of electronic circuit 100 is produced by second (mirror) transistor unit 128, and described second (mirror) transistor unit normally has total gate area of (mirror) transistor unit 126 than first or the total gate area of width larger about 50 to 500 times or the large turn-on transistor device of width.In other words, the current mirror 122 formed by the first transistor device 126 and transistor seconds device 128, compared with other conventional current mirror level, can have relatively high conduction ratio.The frequency compensation of electronic circuit 100 is provided by output capacitor 134, and described output capacitor produces dominant frequency limit in electronic circuit 100.The pole frequency produced by the grid capacitance of second (mirror) transistor unit 128 is increased by the first mirror transistor unit 126.Note, owing to exporting the electric capacity at 114 places, output 114 place of the first amplifier 102 also produces frequency pole.But the output impedance (and being therefore voltage gain) of the first amplifier 102 suitably reduces according to design alternative, thus this limit is made to be non-dominant.In addition, now notice that following content is useful: such as, depend on design or manufacture preference, p NMOS N-channel MOS N (PMOS) or n channel MOS (NMOS) transistor unit can be utilized to implement all crystals pipe device as herein described.It should be noted that in some embodiments, do not use first (mirror) transistor unit 126, therefore do not use current mirror output (122), and output stage is made up of output transistor 128 haply.

Fig. 2 is the schematic block diagram of the second electronic circuit 200, and described second electronic circuit can be used for implementing the second exemplary of the present invention.For example, electronic circuit 200 can be used for implementing the second adaptive-biased LDO voltage stabilizer for the enhancement mode transient response in semiconductor structure, such as semiconducter IC, wafer, chip or nude film.

With reference to the exemplary shown in figure 2, electronic circuit 200 (such as, LDO voltage stabilizer) comprises the first amplifier 202, and described first amplifier is the input stage of the error amplifier also served as in circuit 200.In this exemplary, the first amplifier 202 is voltage gain amplifiers, and its current offset level is by its output voltage control (such as, self biased amplifier).First input voltage (such as, reference voltage or Vref) is coupled to the noninverting input 204 of the first amplifier 202.In some embodiments, the first input voltage is the fixed reference potential produced in electronic circuit 200.In other embodiments, the first input voltage is variable reference voltage (such as, being changed by D/A converter).In some embodiments, the first input voltage produces in electronic circuit 200 outside, and is coupled to input 204 by the pin of such as semiconducter IC or chip.Second input voltage (such as, feedback voltage or Vfb) from being connected to the node 206 of the first resistor 208 and the second resistor 210 (such as, resistive voltage divider) be coupled to the anti-phase input 212 of the first amplifier 202, and the output voltage of the first amplifier 202 from the output 214 of the first amplifier 202 be coupled back the first amplifier 202 bias current control inputs 216 (namely, automatic biasing), and be also connected to the input 218 of the second amplifier 220.In this exemplary, the second amplifier 220 is inverting transconductance amplifiers, and described second amplifier forms the drive current being used for current mirror output stage 222.Or rather, the drain terminal of the first transistor device 226 of current mirror output stage 222 is coupled in the output 224 of the second amplifier 220, and is also coupled to the input 201 of the 3rd (such as, cushioning) amplifier 203.The gate terminal of the first transistor device 226 is coupled in the output 205 of the 3rd amplifier 203, and is also coupled to the gate terminal of the transistor seconds device 228 of current mirror output stage 222.

In this exemplary, the output current of electronic circuit 200 is produced by second (mirror) transistor unit 228 of current mirror output stage 222.Transistor seconds device 228 normally has total gate area of (mirror) transistor unit 226 than first or the total gate area of width larger about 50 to 500 times or the large turn-on transistor device of width.Note, in the illustrated exemplary embodiment, be coupling in being combined to form through buffer current mirror output stage 222 of the 3rd amplifier 203 between the output 224 of the second amplifier 220 and the gate terminal of the first transistor device 226 and transistor seconds device 228.In other words, such as, the 3rd amplifier 203 serves as buffer amplifier or voltage follower, with the relatively large grid capacitance of the transistor seconds device 228 of driven current mirror output stage 222.Therefore, the 3rd amplifier 203 can be used for the total bandwidth increasing current mirror output stage 222, thus exceedes the total bandwidth of the current mirror output stage 122 of electronic circuit 100.But, because use extra circuit unit, so this enhancing can be offset a little more than the current drain of electronic circuit 100 slightly by electronic circuit 200.

The source terminal of the first transistor device 226 and transistor seconds device 228 is coupled to input terminal 230 (such as, the V of electronic circuit 200 _iN).The drain terminal of transistor seconds device 228 is coupled to the side (such as, relative with the side of node 206) of the first resistor 208 and lead-out terminal 232 (such as, the V of electronic circuit 200 _oUT).Lead-out terminal 232 is coupled in the side of capacitor 234 (such as, output capacitor), and the opposite side of capacitor 234 is coupled to the earth terminal 236 (such as, GND or circuit ground) of electronic circuit 200.Earth terminal 236 is also coupled in second side (such as, relative with the side of node 206) of the second resistor 210.

Fig. 3 is the schematic block diagram of the 3rd electronic circuit 300, and described 3rd electronic circuit can be used for implementing the 3rd exemplary of the present invention.For example, electronic circuit 300 can be used for implementing the 3rd adaptive-biased LDO voltage stabilizer for the enhancement mode transient response in semiconductor structure, such as semiconducter IC, wafer, chip or nude film.

With reference to the exemplary shown in figure 3, electronic circuit 300 (such as, LDO voltage stabilizer) comprises the first amplifier 302, and described first amplifier is the input stage of the error amplifier also served as in circuit 300.In this exemplary, the first amplifier 302 is voltage gain amplifiers, and its current offset level is by its output voltage control (such as, self biased amplifier).First input voltage (such as, reference voltage or Vref) is coupled to the noninverting input 304 of the first amplifier 302.In some embodiments, the first input voltage is the fixed reference potential produced in electronic circuit 300.In other embodiments, the first input voltage is variable reference voltage (such as, being changed by D/A converter).In some embodiments, the first input voltage produces in electronic circuit 300 outside, and is coupled to input 304 by the pin of such as semiconducter IC or chip.Second input voltage (such as, feedback voltage or Vfb) from being connected to the node 306 of the first resistor 308 and the second resistor 310 (such as, resistive voltage divider) be coupled to the anti-phase input 312 of the first amplifier 302, and the output voltage of the first amplifier 302 is coupled to the input 318 of the second amplifier 320 from the output 314 of the first amplifier 302, and be also coupled to the input 319 of the 3rd amplifier 305.In this exemplary, the second amplifier 320 is inverting transconductance amplifiers, and described second amplifier forms the drive current being used for the first current mirror output stage 322.Or rather, gate terminal and the drain terminal of the first transistor device 326 of the first current mirror output stage 322 are coupled in the output 324 of the second amplifier 320, and are also coupled to the gate terminal of the transistor seconds device 328 of the first current mirror output stage 322.The source terminal of the first transistor device 326 and transistor seconds device 328 is coupled to input terminal 330 (such as, the V of electronic circuit 300 _iN).The drain terminal of transistor seconds device 328 is coupled to the side (such as, relative with the side of node 306) of the first resistor 308 and lead-out terminal 332 (such as, the V of electronic circuit 300 _oUT).Lead-out terminal 332 is coupled in the side of capacitor 334 (such as, output capacitor), and the opposite side of capacitor 334 is coupled to the earth terminal 336 (such as, GND or circuit ground) of electronic circuit 300.Earth terminal 336 is also coupled in second side (such as, relative with the side of node 306) of the second resistor 310.

In this exemplary, the output current of electronic circuit 300 is produced by transistor seconds device 328, and described transistor seconds device normally has than total gate area of the first transistor device 326 or the total gate area of width larger about 50 to 500 times or the large turn-on transistor device of width.In other words, the first current mirror 322 formed by the first transistor device 326 and transistor seconds device 328 has relatively high conduction ratio compared with other conventional current mirror level.

In this exemplary, the 3rd amplifier 305 is also anti-phase transconductance stage, and the anti-phase transconductance stage of described anti-phase transconductance stage and the second amplifier 320 works similarly.The gate terminal of the third transistor device 307 of the second current mirror stage 338 is coupled in the output 325 of the 3rd amplifier 305, and is also coupled to gate terminal and the drain terminal of the 4th transistor unit 309 of the second current mirror stage 338.The drain terminal of third transistor device 307 is coupled to the bias current input 316 of the first amplifier 302.Therefore, bias current is provided to the bias current input 316 of the first amplifier 302 by the 3rd amplifier 305 by the third transistor device 307 of the second current mirror stage 338 and the 4th transistor unit 309, and described bias current be fed to the first transistor device 326 of the first current mirror output stage 322 and the current in proportion of transistor seconds device 328 by the second amplifier 320.Ratio value is that mirror between the 3rd mirror transistor unit 307 of transconductance value by adjusting the second amplifier 320 and the second current mirror stage 338 and the 4th transistor unit 309 is than the design parameter arranged.It should be noted that the transconductance value of trsanscondutance amplifier 320 and 305 can be different, and the size of the transistor of comparable first current mirror stage 322 of the size of the transistor of the second current mirror stage 338 is much smaller.

Fig. 4 is the schematic block diagram of the 4th electronic circuit 400, and described 4th electronic circuit can be used for implementing the 4th exemplary of the present invention.For example, electronic circuit 400 can be used for implementing the 4th adaptive-biased LDO voltage stabilizer for the enhancement mode transient response in semiconductor structure, such as semiconducter IC, wafer, chip or nude film.

With reference to the exemplary shown in figure 4, electronic circuit 400 (such as, LDO voltage stabilizer) comprises the first amplifier 402, and described first amplifier is the input stage of the error amplifier also served as in circuit 400.In this exemplary, the first amplifier 402 is voltage gain amplifiers, and its current offset level is by its output voltage control (such as, self biased amplifier).First input voltage (such as, reference voltage or Vref) is coupled to the noninverting input 404 of the first amplifier 402.In some embodiments, the first input voltage is the fixed reference potential produced in electronic circuit 400.In other embodiments, the first input voltage is variable reference voltage (such as, being changed by D/A converter).In some embodiments, the first input voltage produces in electronic circuit 400 outside, is coupled to input 404 by the pin of such as semiconducter IC or chip.Second input voltage (such as, feedback voltage or Vfb) from being connected to the node 406 of the first resistor 408 and the second resistor 410 (such as, resistive voltage divider) be coupled to the anti-phase input 412 of the first amplifier 402, and the output voltage of the first amplifier 402 is coupled to the input 418 of the second amplifier 420 from the output 414 of the first amplifier 402, and be also coupled to the input 419 of the 3rd amplifier 405.In this exemplary, the second amplifier 420 is inverting transconductance amplifiers, and described second amplifier forms the drive current being used for the first current mirror output stage 422.Or rather, the drain terminal of the first transistor device 426 is coupled in the output 424 of the second amplifier 420, and is also coupled to the input 401 of buffer amplifier 403.The gate terminal of the first transistor device 426 is coupled in the output 405 of buffer amplifier 403, and is also connected to the gate terminal of the transistor seconds device 428 of the first current mirror output stage 422.The source terminal of the first transistor device 426 and transistor seconds device 428 is coupled to input terminal 430 (such as, the V of electronic circuit 400 _iN).The drain terminal of transistor seconds device 428 is coupled to the side (such as, relative with the side of node 406) of the first resistor 408 and lead-out terminal 432 (such as, the V of electronic circuit 400 _oUT).Lead-out terminal 432 is coupled in the side of capacitor 434 (such as, output capacitor), and the opposite side of capacitor 434 is coupled to the earth terminal 436 (such as, GND or circuit ground) of electronic circuit 400.Earth terminal 436 is also coupled in second side (such as, relative with the side of node 406) of the second resistor 410.

In this exemplary, the output current of electronic circuit 400 is produced by the transistor seconds device 428 of the first current mirror output stage 422.Transistor seconds device 428 normally has than total gate area of the first transistor device 426 or the total gate area of width larger about 50 to 500 times or the large turn-on transistor device of width.In other words, the first current mirror 422 formed by the first transistor device 426 and transistor seconds device 428, compared with other conventional current mirror level, can have relatively high conduction ratio.

In this exemplary, the 3rd amplifier 405 is also anti-phase transconductance stage, and the anti-phase transconductance stage of described anti-phase transconductance stage and the second amplifier 420 works similarly.The gate terminal of the third transistor device 407 of the second current mirror stage 438 is coupled in the output 425 of the 3rd amplifier 405, and is also coupled to gate terminal and the source terminal of the 4th transistor unit 409 of the second current mirror stage 438.The drain terminal of third transistor device 407 is coupled to the bias current input 416 of the first amplifier 402.Therefore, bias current is provided to the bias current input 416 of the first amplifier 402 by the 3rd amplifier 405 by the third transistor device 407 of the second current mirror stage 438 and the 4th transistor unit 409, and described bias current be fed to the first transistor device 426 of the first current mirror output stage 422 and the current in proportion of transistor seconds device 428 by the second amplifier 420.Ratio value is that mirror between the third transistor device 407 of transconductance value by adjusting the second amplifier 420 and the second current mirror stage 438 and the 4th transistor unit 409 is than the design parameter arranged.

Note, in the illustrated exemplary embodiment, the combination being coupling in the buffer amplifier 403 between the output 424 of the second amplifier 420 and the gate terminal of the first transistor device 426 and transistor seconds device 428 is for the formation of through buffer current mirror output stage 422.In other words, such as, buffer amplifier 403 serves as buffer amplifier or voltage follower to drive the relatively large grid capacitance of the transistor seconds device 428 of the first current mirror stage 422.Therefore, buffer amplifier 403 for increasing the total bandwidth of current mirror output stage 422, thus exceedes the total bandwidth of the current mirror output stage 322 of electronic circuit 300.It should be noted that the transconductance value of trsanscondutance amplifier 420 and 405 can be different, and the size of the transistor of comparable first current mirror stage 422 of the size of the transistor of the second current mirror stage 438 is much smaller.

Fig. 5 is the schematic circuit of exemplary semiconductor structure 500, and described semiconductor structure comprises the electronic circuit (such as, for the adaptive-biased LDO voltage stabilizer of enhancement mode transient response) that can be used for implementing electronic circuit 200 or electronic circuit 400.For example, semiconductor structure 500 can be semiconducter IC, wafer, chip or nude film.In this embodiment, buffer amplifier is included in circuit 500, such as to produce through buffer current mirror output stage, as shown in figs. 2 and 4 through buffer circuit mirror output stage 222,422.

With reference to the exemplary shown in figure 5 (and such as, structure in Fig. 5 and the structure shown in Fig. 2 and Fig. 4 are compared), semiconductor structure 500 comprises the first amplifier 502 (such as, indicated by the dotted line comprising transistor M1 to M4), described first amplifier is the input stage of also serving as error amplifier.In this exemplary, the first amplifier 502 is voltage gain amplifiers, and its current offset level is by its output voltage control (such as, self biased amplifier).Transistor 501 is coupled to the first amplifier 502, and response is coupled to the input voltage of the gate terminal of transistor 501 (such as, BIAS), transistor 501 produces fixed bias current, and therefore at such as underload place for the first amplifier 502 provides reference bias current.In some embodiments, input voltage (BIAS) is the fixed voltage produced in semiconductor structure 500.In other embodiments, input voltage (BIAS) is variable reference voltage (such as, being changed by D/A converter).In some embodiments, input voltage (BIAS) produces in semiconductor structure 500 outside, and is coupled to the gate terminal of transistor 501 by the pin of such as semiconducter IC or chip.

First input voltage (such as, reference voltage or Vref) is coupled to the noninverting input 504 (grid of transistor M1) of the first amplifier 502.In some embodiments, the first input voltage is the fixed reference potential produced in semiconductor structure 500.In other embodiments, the first input voltage produces in semiconductor structure 500 outside, and is coupled to input 504 by the pin of such as semiconducter IC or chip.Second input voltage (such as, feedback voltage or Vfb) from being connected to the node 506 of the first resistor 508 and the second resistor 510 (such as, resistive voltage divider) be coupled to the anti-phase input 512 (such as, the grid of transistor M2) of the first amplifier 502.The output voltage of the first amplifier 502 is coupled to the gate terminal (input) of the second amplifier 520 (transistor M9) from the output 514 of the first amplifier, and is also coupled to the gate terminal (input) of the 3rd amplifier 505 (transistor M5).

In this exemplary, the second amplifier 520 is inverting transconductance amplifiers, and described second amplifier forms the drive current being used for the first current mirror output stage 522.Or rather, the output (drain terminal) of the second amplifier 520 is coupled to buffer amplifier 503 (such as, indicated by the dotted line comprising transistor M10 to M13) input, and be also coupled to the drain terminal (transistor M10, M12 via being connected with diode) of the first transistor device 526.The gate terminal of the first transistor device 526 is coupled in the output 515 of buffer amplifier 503, and is also connected to the gate terminal of the transistor seconds device 528 of the first current mirror output stage 522.The source terminal of the first transistor device 526 and transistor seconds device 528 is coupled to input terminal 530 (such as, the V of semiconductor structure 500 _iN).The drain terminal of transistor seconds device 528 is coupled to the side (such as, relative with the side of node 506) of the first resistor 508 and lead-out terminal 532 (such as, the V of semiconductor structure 500 _oUT).Lead-out terminal 532 is coupled in the side of capacitor 534 (such as, output capacitor), and the opposite side of capacitor 534 is coupled to the earth terminal 536 (such as, GND or circuit ground) of semiconductor structure 500.Earth terminal 536 is also coupled in second side (such as, relative with the side of node 506) of the second resistor 510.

In this exemplary, the output current of semiconductor structure 500 is produced by the transistor seconds device 528 of the first current mirror output stage 522.Transistor seconds device 528 normally has possibility than total gate area of the first transistor device 526 or the total gate area of width larger about 50 to 500 times or the large turn-on transistor device of width.In other words, the first current mirror 522 formed by the first transistor device 526 and transistor seconds device 528, compared with other conventional current mirror level, can have relatively high conduction ratio.

In this exemplary, the 3rd amplifier 505 is also anti-phase transconductance stage, and the anti-phase transconductance stage of described anti-phase transconductance stage and the second amplifier 520 works similarly.The output (drain terminal) of the 3rd amplifier 505 is coupled to the second current mirror stage 538 (such as, indicated by the dotted line comprising transistor M5 to M7) the gate terminal of third transistor device 507, and be also coupled to gate terminal and the drain terminal of the 4th transistor unit 509 of the second current mirror stage 538.The drain terminal of third transistor device 507 is coupled to bias current input (source electrode of M1, M2) of the first amplifier 502.Therefore, bias current is provided to bias current input (source electrode of M1, M2) of the first amplifier 502 by the 3rd amplifier 505 by the third transistor device 507 of the second current mirror stage 538 and the 4th transistor unit 509, and described bias current be fed to the first transistor device 526 of the first current mirror output stage 522 and the current in proportion of transistor seconds device 528 by the second amplifier 520.Ratio value is that mirror between the third transistor device 507 of transconductance value by adjusting the second amplifier 520 (such as, by the size of adjustment transistor M5 relative to transistor M9) and the second current mirror stage 538 and the 4th transistor unit 509 is than the design parameter arranged.It should be noted that the transconductance value of trsanscondutance amplifier 520 and 505 can be different, and the size of the transistor of comparable first current mirror stage 522 of the size of the transistor of the second current mirror stage 538 is much smaller.

Note, in the illustrated exemplary embodiment, the combination being coupling in the buffer amplifier 503 between the output (drain terminal) of the second amplifier 520 and the gate terminal of the first transistor 526 and transistor seconds 528 is for the formation of through buffer current mirror output stage 522.In other words, such as, buffer amplifier 503 serves as buffer amplifier or voltage follower, to drive the relatively large grid capacitance of the transistor seconds device 528 of the first current mirror output stage 522.Therefore, buffer amplifier 503 for increasing the total bandwidth of current mirror output stage 522, thus exceedes other total bandwidth without buffer current mirror output stage (current mirror output stage 322 such as, shown in Fig. 3).

In operation, with reference to figure 5, when semiconductor structure 500 is such as embodied as LDO voltage stabilizer, consider following two kinds of output conditions or state: 1) by lead-out terminal 532 (V _oUT) load current be stable (DC); And 2) by lead-out terminal 532 (V _oUT) load current increase suddenly.For example, in steady state operation, semiconductor structure 500 utilizes three current mirror stage to run substantially: the current mirror pair 1) formed by transistor 526 and 528; 2) current mirror pair formed by transistor 520 and 505; And 3) current mirror that formed by transistor 509 and 507 is to (that is, M5 and M9).Tail current is coupled to the source terminal (such as, the bias current input of first amplifier 502) of difference transistor to M1 and M2 by these three current mirror stage generation tail currents also (by transistor 507).The value of this tail current is generally designed to the sub-fraction (therefore the sub-fraction of the size of the transistor of the second current mirror stage 538 normally size of the transistor of the first current mirror stage 522) of the output current of the transistor 528 by the first current mirror output stage 522.In steady state operation, the overall feedback loop of semiconductor structure 500 is in poised state, and the feedback voltage Vfb at node 506 place equals reference voltage Vref haply.So, when the value of output current is relatively little (such as, stable state), transistor 501 in response to be applied to transistor 501 grid voltage (BIAS) value and produce the quiescent bias current of the first amplifier 502, and the bias current produced by transistor 507 may be very little, or even insignificant.

In the second mode of operation, by lead-out terminal 532 (V _oUT) load current increase suddenly.Before can reacting to the change of this state in the overall feedback loop of semiconductor structure 500, extra load current makes output capacitor 534 discharge, and and then reduces output voltage V _oUTvalue.This of output voltage reduces the value reducing the feedback voltage Vfb at node 506 place, and described feedback voltage is the voltage of the gate terminal of the transistor M2 being applied to the first amplifier 502.It is uneven that the gained of the grid voltage of transistor M2 reduces the input voltage making differential pair transistors M1 and M2, thus increase the electric current by transistor M2, and and then increase the voltage being applied to the grid of transistor 505 and 520.The leakage current of the increase of the gained of transistor 505 feeds back to the bias current input of the first amplifier 502 to 509 and 507 by current mirror transistor, thus turn increase the value of the tail current just produced.This of tail current increases and increases by the electric current of transistor M2, and and then increases the voltage at the gate terminal place of transistor 505 and 520 with just (increase) speed.Meanwhile, by the electric current of the increase of transistor 520 to the large gate capacitance charges of output transistor 528 (such as, by buffer amplifier 503), until the enough offered load electric currents of the drain current of transistor 528.At this moment, output voltage V _oUTmagnitude turn back to stable state when increased electric current charges to output capacitor 534.So, the adaptive-biased layout (input stage) of the first amplifier 502 makes the levels of current of the first order be increased on the equilibrium level in overall feedback loop, to give the gate capacitance charges of output transistor 528 quickly.Therefore, reach new limit, adaptive bias reaches new equilibrium valve, described equilibrium valve by transistor to 528 and 526,520 and 505 and 509 and 507 gate area (or width) than clearly defining.

In a word, according to the teaching of the application, the relatively large grid capacitance of turn-on transistor 528 is at adaptive-biased loop-external.Adaptive-biased loop responds increased load current by the value increasing adaptive bias, to give the gate capacitance charges of turn-on transistor 528 quickly.Because the grid capacitance of turn-on transistor 528 is in the outside in adaptive-biased loop, so the response time in adaptive-biased loop is obviously faster than the response time in the normal bias loop in conventional LDO voltage stabilizer, and the output voltage of the gained of the LDO voltage stabilizer utilizing semiconductor structure 500 to implement falls the output voltage being significantly less than conventional LDO voltage stabilizer falls.

Note, in the exemplary of semiconductor structure 500, use positive feedback.Therefore, in bias current, being increased in the operating point of the first amplifier 502 of gained changes, thus turn increases produced adaptive bias.In the exemplary described by semiconductor structure 500, positive loop feedback gain is designed to be less than 1, to guarantee the stability in adaptive-biased loop.For example, select transistor size design to make self adaptation feedback transistor 505 with the current density operation of twice of current density being transistor M3 and M4.Therefore, because mutual conductance/drain current ratio (GM/Id) reduces along with current density, the loop gain being less than 1 is guaranteed.

Fig. 6 is the schematic circuit of exemplary semiconductor structure 600, described semiconductor structure comprises the electronic circuit (such as, as the adaptive-biased LDO voltage stabilizer for enhancement mode transient response) that can be used for implementing the electronic circuit 100 shown in Fig. 1 and Fig. 3 or electronic circuit 300.For example, semiconductor structure 600 can be semiconducter IC, wafer, chip or nude film.Note, the structure of semiconductor structure 600 and operation are similar to structure and the operation of the semiconductor structure 500 shown in Fig. 5 haply, but buffer amplifier level (such as, 503 in Fig. 5) is not included in semiconductor structure 600.

With reference to the exemplary shown in figure 6 (and such as, structure in Fig. 6 and the structure shown in Fig. 1 and Fig. 3 are compared), semiconductor structure 600 comprises the first amplifier 602 (such as, indicated by the dotted line comprising transistor M1 to M4), described first amplifier is the input stage of also serving as error amplifier.In this exemplary, the first amplifier 602 is voltage gain amplifiers, and its current offset level is by its output voltage control (such as, self biased amplifier).Transistor 601 is coupled to the first amplifier 602, and response is coupled to the input voltage of the gate terminal of transistor 601 (such as, BIAS), transistor 601 produces fixed bias current, and therefore at such as underload place for the first amplifier 602 provides reference bias current.In some embodiments, input voltage (BIAS) is the fixed voltage produced in semiconductor structure 600.In other embodiments, input voltage (BIAS) is variable reference voltage (such as, being changed by D/A converter).In some embodiments, input voltage (BIAS) produces in semiconductor structure 600 outside, and is coupled to the gate terminal of transistor 601 by the pin of such as semiconducter IC or chip.

First input voltage (such as, reference voltage or Vref) is coupled to the noninverting input 604 (grid of transistor M1) of the first amplifier 602.In some embodiments, the first input voltage is the fixed reference potential produced in semiconductor structure 600.In other embodiments, the first input voltage produces in semiconductor structure 600 outside, and is coupled to input 604 by the pin of such as semiconducter IC or chip.Second input voltage (such as, feedback voltage or Vfb) anti-phase input 612 (grid of transistor M2) of the first amplifier 602 is coupled to from the node 606 (such as, resistive voltage divider) being connected to the first resistor 608 and the second resistor 610.The output voltage of the first amplifier 602 is coupled to the gate terminal (input) of the second amplifier 620 (transistor M9) from the output 614 of the first amplifier 602, and is also coupled to the gate terminal (input) of the 3rd amplifier 605 (transistor M5).

In this exemplary, the second amplifier 620 is inverting transconductance amplifiers, and described second amplifier forms the drive current being used for the first current mirror output stage 622.Or rather, the drain terminal of the first transistor device 626 is coupled in the output (drain terminal) of the second amplifier 620, and is also coupled to the first transistor device 626 of the first current mirror output stage 622 and the gate terminal of transistor seconds device 628.The source terminal of the first transistor device 626 and transistor seconds device 628 is coupled to input terminal 630 (such as, the V of semiconductor structure 600 _iN).The drain terminal of transistor seconds device 628 is coupled to the side (such as, relative with the side of node 606) of the first resistor 508 and lead-out terminal 632 (such as, the V of semiconductor structure 600 _oUT).Lead-out terminal 632 is coupled in the side of capacitor 634 (such as, output capacitor), and the opposite side of capacitor 634 is coupled to the earth terminal 636 (such as, GND or circuit ground) of semiconductor structure 600.Earth terminal 636 is also coupled in second side (such as, relative with the side of node 606) of the second resistor 610.

In this exemplary, the output current of semiconductor structure 600 is produced by the transistor seconds device 628 of the first current mirror output stage 622.Transistor seconds device 628 normally has possibility than total gate area of the first transistor device 626 or the total gate area of width larger about 50 to 500 times or the large turn-on transistor device of width.In other words, the first current mirror output stage 622 formed by the first transistor device 626 and transistor seconds device 628, compared with other conventional current mirror level, can have relatively high conduction ratio.

In this exemplary, the 3rd amplifier 605 is also anti-phase transconductance stage, and the anti-phase transconductance stage of described anti-phase transconductance stage and the second amplifier 620 works similarly.The output (drain terminal) of the 3rd amplifier 605 is coupled to the second current mirror stage 638 (such as, indicated by the dotted line comprising transistor M5 to M7) the gate terminal of third transistor device 607, and be also coupled to gate terminal and the drain terminal of the 4th transistor unit 609 of the second current mirror stage 638.The drain terminal of third transistor device 607 is coupled to bias current input (source electrode of M1, M2) of the first amplifier 602.Therefore, bias current is provided to bias current input (source electrode of M1, M2) of the first amplifier 602 by the 3rd amplifier 605 by the third transistor device 607 of the second current mirror stage 638 and the 4th transistor unit 609, and described bias current be fed to the first transistor device 626 of the first current mirror output stage 622 and the current in proportion of transistor seconds device 628 by the second amplifier 620.Ratio value is that mirror between the third transistor device 607 of transconductance value by adjusting the second amplifier 620 and the second current mirror stage 638 and the 4th transistor unit 609 is than the design parameter arranged.

In operation, with reference to figure 6, when semiconductor structure 600 is embodied as such as LDO voltage stabilizer, consider following two kinds of output conditions or state: 1) by lead-out terminal 632 (V _oUT) load current be stable (DC); And 2) by lead-out terminal 632 (V _oUT) load current increase suddenly.For example, in steady state operation, semiconductor structure 600 utilizes three current mirror stage to run substantially: the current mirror pair 1) formed by transistor 626 and 628; 2) current mirror pair formed by transistor 620 and 605; And 3) current mirror that formed by transistor 609 and 607 is to (M5 and M9).These three current mirror stage produce tail current, and tail current is coupled to difference transistor to M1 and M2 (such as, the bias current input of the first amplifier 602) by (by transistor 607).The value of this tail current is designed by the sub-fraction of the output current of the transistor 628 of the first current mirror output stage 622.In steady state operation, the overall feedback loop of semiconductor structure 600 is in poised state, and the feedback voltage Vfb at node 606 place equals reference voltage Vref haply.So, when the value of output current is relatively little (such as, stable state), transistor 601 in response to be applied to transistor 601 grid voltage (BIAS) value and produce the quiescent bias current of the first amplifier 602, and the bias current produced by transistor 607 may be very little, or even insignificant.

In the second mode of operation, by lead-out terminal 632 (V _oUT) load current increase suddenly.Before can reacting to the change of this state in the overall feedback loop of semiconductor structure 600, extra load current makes output capacitor 634 discharge, and and then reduces output voltage V _oUTvalue.This of output voltage reduces the value reducing the feedback voltage level Vfb at node 606 place, and described feedback voltage is the voltage of the gate terminal of the transistor M2 being applied to the first amplifier 602.It is uneven that the gained of the grid voltage of transistor M2 reduces the input voltage making differential pair transistors M1 and M2, thus increase the electric current by transistor M2, and and then increase the voltage being applied to the grid of transistor 605 and 620.The leakage current of the increase of the gained of transistor 605 feeds back to the bias current input of the first amplifier 602 to 609 and 607 by current mirror transistor, thus turn increase the value of the tail current just produced.This of tail current increases and increases by the electric current of transistor M2, and and then increases the voltage at the gate terminal place of transistor 605 and 620 with just (increase) speed.Meanwhile, the large gate capacitance charges of output transistor 628 is given quickly by the electric current of the increase of transistor 620, until the enough offered load electric currents of the drain current of transistor 628.At this moment, output voltage V _oUTmagnitude turn back to stable state when increased electric current charges to output capacitor 634.So, the adaptive-biased layout (input stage) of the first amplifier 602 makes the levels of current of the first order be increased on the equilibrium level in overall feedback loop, to give the gate capacitance charges of output transistor 628.Therefore, reach new limit, adaptive bias reaches new equilibrium valve, described equilibrium valve by transistor to 628 and 626,620 and 605 and 609 and 607 gate area than clearly defining.

In a word, according to the teaching of the application, the relatively large grid capacitance of turn-on transistor 628 is at adaptive-biased loop-external.Adaptive-biased loop responds the load current of increase by the value increasing adaptive bias, to give the gate capacitance charges of turn-on transistor 628 quickly.Because the grid capacitance of turn-on transistor 628 is in the outside in adaptive-biased loop, so the response time in adaptive-biased loop is obviously faster than the response time in the normal bias loop in conventional LDO voltage stabilizer, and the output voltage of the gained of the LDO voltage stabilizer utilizing semiconductor structure 600 to implement falls the output voltage being significantly less than conventional LDO voltage stabilizer falls.

Note, in the exemplary of semiconductor structure 600, use positive feedback.Therefore, in bias current, being increased in the operating point of the first amplifier 602 of gained changes, thus turn increases produced adaptive bias.In the exemplary described by semiconductor structure 600, positive feedback loop gain design is become to be less than 1, to guarantee the stability in adaptive-biased loop.For example, select transistor size design to make self adaptation feedback transistor 605 with the current density operation of twice of current density being transistor M3 and M4.Therefore, because mutual conductance/drain current ratio (GM/Id) is along with the reduction of current density, the loop gain being less than 1 is guaranteed.

Fig. 7 A and Fig. 7 B describes according to the analogue phase allowance performance curve of the one or more and structurized adaptive-biased LDO voltage stabilizer in above-mentioned embodiment of the present invention and the correlogram of gain margin performance curve.These graph plots are applied in the simulated performance curve of the adaptive-biased LDO voltage stabilizer of different electrical power voltage, temperature and process corner.Level (X) axle indicates the load current applied, and the phase margin value of vertical (Y) axle pointer different operating condition that involved LDO voltage stabilizer is simulated and different output current level or gain margin value.

Note, as curve chart 700a and 700b indicates, give sizable design concern to the providing of acceptable level of circuit stability, described acceptable level is on the potential operating condition likely met with and output current level.But this level of stability is usually directed to the remarkable balance to quiescent current.But, indicated by ldo regulator performance characteristics as shown in figures 7 a and 7b, these analog results confirm that above-mentioned embodiment of the present invention can be used for implementing LDO voltage stabilizer, and described LDO voltage stabilizer realizes the acceptable level of the circuit stability being used for small-signal and large-signal.In other words, as shown in curve chart 700a and 700b, for all different operating conditions (such as, supply voltage, temperature, process corner) and the output current level that applies, the overall performance of involved LDO voltage stabilizer is similar haply.

Fig. 8 describes according to the above-mentioned teaching of the application the curve chart of the simulation transient load response of structurized adaptive-biased LDO voltage stabilizer.For shown simulation, at 500 μ s places, 300mA load current step-length is applied to adaptive-biased LDO voltage stabilizer.Note, Fig. 8 shows that the improvement that exceedes the transient voltage drop performance of conventional LDO voltage stabilizer transient voltage drop performance produces primarily of the response speed of increase of the response speed exceeding conventional LDO voltage stabilizer.For example, shown in Fig. 8, the output voltage of simulation LDO voltage stabilizer " falls " to about 2.176V (802) at about 500.45 μ s places.In remarkable contrast, the output voltage of conventional LDO voltage stabilizer will at 500.5 μ s places or the time drops at least 2.142V after a while.So, compared with conventional LDO voltage stabilizer, the enhancement mode transient response of adaptive-biased LDO voltage stabilizer is mainly implemented as follows.Be similar to a little conventional LDO voltage stabilizer, the output voltage of adaptive-biased LDO voltage stabilizer reduces when increased load is for discharging to output capacitor.But adaptive-biased LDO voltage stabilizer increases its bias current, the gate capacitance charges of turn-on transistor device can be given quickly.The transient response time of adaptive-biased feedback loop is than the transient response time much shorter in the overall feedback loop of LDO voltage stabilizer, and therefore, adaptive-biased LDO voltage stabilizer than the conventional LDO voltage stabilizer responsive load transient state more quickly without adaptive-biased feedback loop, and than having conventional LDO voltage stabilizer (wherein said adaptive-biased feedback loop comprises usually the input capacitance of larger output device) the responsive load transient state more quickly of adaptive-biased feedback.In addition, the transient state that adaptive-biased LDO voltage stabilizer experiences is fallen and is significantly less than the transient state that conventional LDO voltage stabilizer experiences and falls.

Fig. 9 describes adaptive-biased LDO voltage stabilizer at High Operating Temperature (125C), 2.5V input voltage (such as, V _iN) and 2.2V rated output voltage (such as, V _oUT) simulated operation condition under the curve chart of simulated performance pattern.As shown in Figure 9, although simulation is carried out under multiple different process, temperature and input voltage condition, the performance mode of adaptive-biased LDO voltage stabilizer is kept haply.In other words, curve chart depicted in figure 9 shows that how little manufacture change (m) performance on adaptive-biased LDO voltage stabilizer has impact.So, performance change depicted in figure 9 mainly produces from the change of operating temperature.For example, upper curve 902a to the 908a shown in Fig. 9 describes maximum voltage error or the transient overshoot of adaptive-biased LDO voltage stabilizer, and lower curve 902b to 908b describe involved by the minimum voltage of adaptive-biased LDO voltage stabilizer or transient state fall.The instruction of level (X) axle is used for the process corner of this simulation manufacturing situation for following five kinds: situation 0 indicates the process corner being used for typical n NMOS N-channel MOS N (NMOS) and p raceway groove (PMOS) transistor; Situation 1 indicates the process corner being used for slow NMOS and PMOS transistor; Situation 2 indicates the process corner being used for fast NMOS and PMOS transistor; Situation 3 indicates the process corner being used for slow nmos pass transistor and fast PMOS transistor; And situation 4 indicates the process corner being used for fast nmos pass transistor and slow PMOS transistor.In this exemplary simulated, performance curve 902a and 902b pointer are to the circuit performance of 2.5V input voltage and 125C operating temperature; Curve 904a and 904b pointer are to the circuit performance of 5.5V input voltage and 125C operating temperature; Curve 906a and 906b pointer are to the circuit performance of 5.5V input voltage with-20C operating temperature; And curve 908a and 908b pointer are to the circuit performance of 2.5V input voltage and-20C operating temperature.2.2V output voltage (specified) is for all simulations.Note, the enhancement mode transient overshoot of the above-mentioned adaptive-biased LDO voltage stabilizer of simulation instruction shown in Fig. 9 and drop performance are better than transient overshoot and the drop performance of conventional LDO voltage stabilizer.

Figure 10 describes the schematic block diagram being configured to the example system 1000 of PMIC, and described PMIC can be used for the semiconductor structure for enhancement mode transient response implemented according to one or more embodiments of the present invention.In some embodiments, system 1000 can be implemented on semiconducter IC, wafer, chip or nude film.In the illustrated exemplary embodiment, system 1000 can be implemented as integrated PMIC, so that such as the Thin Film Transistor-LCD (TFT-LCD) in notebook, tablet personal computer (PC), monitor provides electric power, and also for the TFT-LCD of small-size display (as smart phone display) provides electric power.With reference to Figure 10, for an exemplary, system 1000 comprises the adaptive-biased LDO voltage stabilizer 1002 of configuration according to one or more in the above-mentioned embodiment described in Fig. 1 to 6.Adaptive-biased LDO voltage stabilizer 1002 is coupled to voltage input pad 1030 to receive input voltage (V _iN), and be coupled to voltage and export connector 1032 with will through regulation voltage (V _oUT) output to VLOGIC passage output connector 1004.Is be coupled to for driving the relatively low voltage that VLOGIC passage exports the external digital circuit of 1004 from adaptive-biased LDO voltage stabilizer 1002 through regulation output voltage.Ldo regulator 1002 will be also for being provided to sequencer 1006, simulation Vdd or supply voltage (AVDD) boost controller 1008, strobe pulse modulator (GPM) 1010, voltage detector 1012 through regulation voltage and being used as calibrator to adjust the V of the LCD used _cOMthe numerical control potentiometer (DCP) 1014 of voltage.In this example system, LDO voltage stabilizer 1002 is external adjustable parts (such as, the contact pin via semiconducter IC or wafer), and exposes as " independence " function.In other example system, LDO voltage stabilizer 1002 is not external adjustable.So, according to above-mentioned teaching of the present invention, adaptive-biased LDO voltage stabilizer 1002 provides enhancement mode (such as, the haply faster) transient response of the transient response being better than conventional LDO voltage stabilizer in system 1000.

Figure 11 describes the schematic block diagram being configured to second example system 1100 of PMIC, and described PMIC can be used for the semiconductor structure for enhancement mode transient response implemented according to one or more embodiments of the present invention.In some embodiments, system 1100 can be implemented on semiconducter IC, wafer, chip or nude film.In the illustrated exemplary embodiment, system 1100 is embodied as the high-efficiency power for small size, hand-held display device (such as smart phone TFT-LCD).With reference to Figure 11, for an exemplary, system 1100 comprises the adaptive-biased LDO voltage stabilizer 1102 of the configuration according to the one or more of the above-mentioned embodiment described in Fig. 1 to 6.Adaptive-biased LDO voltage stabilizer 1102 is coupling between the current earthing 1136 of system 1100 and other circuit unit numerous, to provide suitable decoupling for the power circuit in system 1100.So, in some example embodiments, adaptive-biased LDO voltage stabilizer 1102 is integrated with " on chip " Voltage Cortrol, to realize the follow-up manufacture Voltage Cortrol of adaptive-biased LDO voltage stabilizer 1102.Substantially, in operation, the input 1130 (V of adaptive-biased LDO voltage stabilizer 1102 _iN) voltage at place provides from booster converter 1101, described booster converter is suitable for the output 1132 (V following the trail of adaptive-biased LDO voltage stabilizer 1102 _oUT) voltage at place, to provide just enough voltage drop for adaptive-biased LDO voltage stabilizer 1102 as required operation.So, according to teaching of the present invention, adaptive-biased LDO voltage stabilizer 1102 provides enhancement mode (such as, the faster) transient response of the transient response being better than conventional LDO voltage stabilizer in system 1100.

Figure 12 is the flow chart of the exemplary methods of operationthe 1200 of the adaptive-biased LDO voltage stabilizer described according to one or more embodiments of the present invention.For example, method 1200 can be used for describing Fig. 1 to the one or more operation in exemplary depicted in figure 6.With reference to Figure 12, for an exemplary, first amplifier (such as, error amplifier) export suitable voltage (1202), described voltage transitions (such as, pass through trsanscondutance amplifier) become the load current of output device (such as, turn-on transistor) for controlling adaptive-biased LDO voltage stabilizer.First amplifier also receives the feedback voltage (1204) of the output voltage representing adaptive-biased LDO voltage stabilizer.If fall (such as by the feedback voltage of the first amplifier accepts, the output voltage be associated with the transient state of load current reduces) (1206), so fall in response to output voltage, the first amplifier uses positive feedback loop to increase the bias current (1208) of himself.Note, positive feedback loop does not comprise the electric capacity (such as, the grid capacitance of conducting or output transistor) be associated with the control terminal of output device.In response to the increase of bias current, the first amplifier increases its output voltage and (such as, via trsanscondutance amplifier), and then increases the load current (1210) going to output device.But if (1206) feedback voltage does not fall, so flow process turns back to and monitors output voltage (1204).

In discussion herein and claims, the term that uses relative to bi-material " ... on ", one another " on " to mean between these materials at least some contacts, and " ... top " mean that these materials are close, but may have one or more additional insert layer, therefore contact is possible instead of necessary.As used herein " ... upper (on) " or " ... top (over) " all do not imply any directivity.The listed value of term " about " instruction can be changed to some extent, as long as described change does not cause inconsistent to the process of illustrated embodiment or structure.

The term of the relative position used in the application defines based on the plane that the conventional plane or working surface with wafer or substrate is parallel, and do not consider the orientation of wafer or substrate.Term as used in this application " level ", " transverse direction " are defined as the plane parallel with the conventional plane of wafer or substrate or working surface, and do not consider the orientation of wafer or substrate.Term " vertically " refers to the direction with horizontal vertical.Such as " ... on ", " side " (side as in " sidewall "), " higher ", " lower ", " ... on ", " top " and " ... under " be define relative to the conventional plane be positioned on wafer or its top surface or working surface, and do not consider the orientation of wafer or substrate.

Although this article has illustrated and described specific embodiment, it will be understood by a person skilled in the art that, any layout that plan realizes identical object can replace shown specific embodiments.Therefore, obviously wish only to limit the present invention by appended claims and equipollent thereof.

Claims

1. a semiconductor structure, it comprises:

First current mirroring circuit, described first current mirroring circuit is coupled to the input pad of described semiconductor structure and exports connector;

Second current mirroring circuit, described second current mirroring circuit is coupled to the described input pad of described semiconductor structure;

First amplifier circuit, described second current mirroring circuit is coupled in first input of described first amplifier circuit, the described output connector of described semiconductor structure is coupled in second input of described first amplifier circuit, and reference voltage is coupled in the 3rd of described first amplifier circuit the input;

Second amplifier circuit, the output of described first amplifier circuit is coupled in the input of described second amplifier circuit, and described first current mirroring circuit is coupled in the output of described second amplifier circuit; And

3rd amplifier circuit, the described output of described first amplifier circuit is coupled in the input of described 3rd amplifier circuit, and described second current mirroring circuit is coupled in the output of described 3rd amplifier circuit.

2. semiconductor structure as claimed in claim 1, it also comprises:

4th amplifier circuit, described 4th amplifier circuit is connected between the described output of described second amplifier circuit and described first current mirroring circuit.

3. semiconductor structure as claimed in claim 1, wherein said reference voltage is fixed voltage.

4. semiconductor structure as claimed in claim 1, described second input of wherein said first amplifier circuit is suitable for receiving the feedback voltage proportional with the output voltage of described semiconductor structure.

5. semiconductor structure as claimed in claim 1, described first input of wherein said first amplifier circuit comprises bias current input.

6. semiconductor structure as claimed in claim 1, wherein said first amplifier circuit comprises error amplifier, and described second amplifier circuit comprises trsanscondutance amplifier; And described 3rd amplifier circuit comprises trsanscondutance amplifier.

7. semiconductor structure as claimed in claim 2, wherein said 4th amplifier circuit comprises buffer amplifier.

8. semiconductor structure as claimed in claim 1, wherein said semiconductor structure comprises adaptive-biased low voltage difference (LDO) pressurizer on semiconductor integrated circuit (IC), wafer, chip or nude film.

9. semiconductor structure as claimed in claim 1, described first input of wherein said first amplifier circuit is connected to the drain terminal of the first transistor device of described second current mirroring circuit, and described first amplifier circuit and then comprise self biased amplifier circuit.

10. an electronic circuit, it comprises:

The first transistor device, described the first transistor device is coupled to the input pad of described electronic circuit and exports connector;

Transistor seconds device, described transistor seconds device is coupled to the described the first transistor device of described electronic circuit and described input pad, wherein said the first transistor device and described transistor seconds device comprise the first current mirror stage, and described the first transistor device comprises the output transistor of described electronic circuit;

Third transistor device, described third transistor device is coupled to the described input pad of described electronic circuit;

4th transistor unit, described 4th transistor unit is coupled to the described input pad of described electronic circuit and described third transistor device, and wherein said third transistor device and described 4th transistor unit comprise the second current mirror stage;

Error amplifier, described error amplifier is coupled to described the first transistor device and described transistor seconds device via the first trsanscondutance amplifier, and be coupled to described third transistor device and described 4th transistor unit via the second trsanscondutance amplifier, and the drain terminal of described 4th transistor unit is coupled in the input of the bias current of described error amplifier, wherein said error amplifier is suitable for comparing with reference to voltage and the feedback voltage proportional with the output voltage of described electronic circuit, and current signal is coupled to described first current mirror stage and described second current mirror stage to drive described first current mirror stage and described second current mirror stage.

11. electronic circuits as claimed in claim 10, it also comprises voltage follower, and described voltage follower is connected between described first trsanscondutance amplifier and described first current mirror stage.

12. electronic circuits as claimed in claim 10, wherein said electronic circuit comprises adaptive-biased LDO voltage stabilizer.

13. electronic circuits as claimed in claim 10, wherein said electronic circuit comprises all or part of of IC power supply or power management IC (PMIC).

The method of 14. 1 kinds of adaptive-biased LDO voltage stabilizer of operation, it comprises:

The feedback voltage that first amplifier accepts is associated with the output voltage of described adaptive-biased LDO voltage stabilizer;

Described feedback voltage and reference voltage compare by described first amplifier, and produce the first voltage in response to described comparison;

In response to described first voltage, the first trsanscondutance amplifier produces the first output current, and the second trsanscondutance amplifier produces the second output current;

In response to described second output current, produce the bias current being used for described first amplifier; And

In response to described first output current, produce the output current of described adaptive-biased LDO voltage stabilizer.

15. methods as claimed in claim 14, wherein said first amplifier is error amplifier circuit.

16. methods as claimed in claim 14, the described bias current that wherein said generation is used for described first amplifier comprises the input of the output of described second trsanscondutance amplifier being coupled to current mirroring circuit, and

The output of described current mirroring circuit is coupled to the bias current input of described first amplifier.

17. methods as claimed in claim 14, the described output current of the described adaptive-biased LDO voltage stabilizer of wherein said generation comprises the input of the output of described first trsanscondutance amplifier being coupled to current mirroring circuit, and described current mirroring circuit comprises the output transistor of described adaptive-biased LDO voltage stabilizer.

18. methods as claimed in claim 17, the described input that the described current mirroring circuit of the described output transistor comprising described adaptive-biased LDO voltage stabilizer is coupled in the wherein said described output by described first trsanscondutance amplifier comprises:

The described output of described first trsanscondutance amplifier is coupled to the input of buffer amplifier circuit; And

The output of described buffer amplifier circuit is coupled to the described input of described current mirroring circuit.

19. methods as claimed in claim 14, wherein perform described method in the adaptive-biased LDO voltage stabilizer of IC power supply or PMIC.

20. 1 kinds of systems, it comprises:

Sequencer unit;

Analog power voltage (AVDD) boost controller;

Strobe pulse modulator (GPM);

Voltage detector;

Numerical control potentiometer (DCP); And

Adaptive-biased LDO voltage stabilizer, it is coupled to the one or more of described sequencer unit, AVDD boost controller, GPM, voltage detector and DCP, and wherein said adaptive-biased LDO voltage stabilizer comprises:

First current mirroring circuit, described first current mirroring circuit is coupled to the input pad of described adaptive-biased LDO voltage stabilizer and exports connector;

Second current mirroring circuit, described second current mirroring circuit is coupled to the described input pad of described adaptive-biased LDO voltage stabilizer;

First amplifier circuit, described second current mirroring circuit is coupled in first input of described first amplifier circuit, the described output connector of described adaptive-biased LDO voltage stabilizer is coupled in second input of described first amplifier circuit, and reference voltage is coupled in the 3rd of described first amplifier circuit the input;

21. systems as claimed in claim 20, wherein said system comprises the power supply be formed on semiconductor wafer, chip, IC or nude film.

22. 1 kinds of systems, it comprises:

Power supply, described power supply is used for Thin Film Transistor-LCD (TFT-LCD); And

Adaptive-biased LDO voltage stabilizer, described adaptive-biased LDO voltage stabilizer is used for decoupling or switches to the one or more frequency signal of circuit ground produced by one or more assemblies of described power supply, and described adaptive-biased LDO voltage stabilizer comprises:

23. the system as claimed in claim 22, wherein said system comprises and is formed at PMIC on semiconductor wafer, chip, IC or nude film or power supply.

24. 1 kinds of LDO voltage stabilizer, it comprises:

Lead-out terminal;

Be coupled to the output device of described lead-out terminal, described output device is suitable for the load current for being applied to described LDO voltage stabilizer; And

Comprise the error amplifier circuit of positive feedback loop, described error amplifier circuit is coupled to the control terminal of described lead-out terminal, reference voltage and described output device; Described positive feedback loop does not comprise the electric capacity be associated with the described control terminal of described output device, wherein said error amplifier circuit is suitable for described reference voltage and the voltage that is associated with the output voltage of described lead-out terminal to compare, if and be associated with the transient state of described load current in described output voltage fall generation, so use described positive feedback loop to increase the bias current of described error amplifier circuit.

25. LDO voltage stabilizer as claimed in claim 24, wherein said output device is the output transistor of circuit mirror circuit.

26. LDO voltage stabilizer as claimed in claim 24, it also comprises:

Trsanscondutance amplifier, described trsanscondutance amplifier is coupled to the output of described error amplifier circuit and the described control terminal of described output device.

27. LDO voltage stabilizer as claimed in claim 24, wherein said positive feedback loop comprise the output of being coupled to described error amplifier circuit trsanscondutance amplifier, be coupled to the output of the described trsanscondutance amplifier of current mirroring circuit and be coupled to the described current mirroring circuit of biased input of described error amplifier circuit.

28. LDO voltage stabilizer as claimed in claim 24, it also comprises buffer amplifier, and described buffer amplifier is coupling between the output of described error amplifier circuit and the described control terminal of described output device.

29. 1 kinds of methods operating LDO voltage stabilizer, it comprises:

Offered load electric current is by the lead-out terminal of described LDO voltage stabilizer;

Monitor the output voltage on the described lead-out terminal of described LDO voltage stabilizer;

Whether falling of determining to be associated with the transient state of described load current in described output voltage occurs, and

If falling of being associated with the transient state of described load current in described output voltage occurs, so use positive feedback loop increase to go to the electric current of the control terminal of the output device of described LDO voltage stabilizer, wherein said positive feedback loop does not comprise the electric capacity be associated with the described control terminal of described output device.

30. methods as claimed in claim 29, wherein said supply is performed by current mirror output circuit.

31. methods as claimed in claim 29, wherein said positive feedback loop comprises trsanscondutance amplifier and current mirroring circuit.

32. methods as claimed in claim 29, wherein said supervision and determine to be performed by error amplifier circuit, and described output device comprises turn-on transistor.

33. methods as claimed in claim 29, the described positive feedback loop of wherein said use performs by error amplifier circuit the bias current increasing described error amplifier circuit.