CN104810297A - 用于制造倒装芯片电路装置的方法和倒装芯片电路装置 - Google Patents

用于制造倒装芯片电路装置的方法和倒装芯片电路装置 Download PDF

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CN104810297A
CN104810297A CN201510028691.0A CN201510028691A CN104810297A CN 104810297 A CN104810297 A CN 104810297A CN 201510028691 A CN201510028691 A CN 201510028691A CN 104810297 A CN104810297 A CN 104810297A
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osculating element
circuit carrier
bonding agent
contact
osculating
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P·狄塞耳
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Robert Bosch GmbH
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Robert Bosch GmbH
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Abstract

本发明涉及一种用于制造倒装芯片电路装置的方法，方法具有至少以下步骤：制造或者提供具有第一表面和施加到第一表面上的接通面的电路载体以及具有第二表面和施加到第二表面上的接触位置的半导体构件，施加第一接触单元到接通面上，施加与第一接触单元对应的第二接触单元到接触位置上，如此使第一接触单元平坦化，使得第一接触单元的接触表面在第一公差之内限定共同的第一接触平面，施加粘接剂到第一接触单元和/或第二接触单元上，按压半导体构件和电路载体以便构成第一和第二接触单元之间的电连接，以及使粘接剂硬化以便建立半导体构件和电路载体之间的机械连接。

Description

用于制造倒装芯片电路装置的方法和倒装芯片电路装置
技术领域
本发明涉及一种用于制造倒装芯片电路装置的方法和一种相应的倒装芯片电路装置。
背景技术
在倒装芯片装配技术中将例如单片半导体元件(芯片、裸芯片(Die))以其有效的接通侧直接装配和接通到电路载体——例如衬底或电路板——上。半导体元件的接触位置在此在无连接引线(引线键合)的情况下与电路载体上的接通面——例如印制导线接通。由此可实现小的面积需求。
为此，例如由金制成的钉头凸点(Stud-Bump)施加到半导体构件的接触位置上并且随后铺设到电路载体的印制导线上，其中，所述钉头凸点相当于由常规的球楔键合(Ball-Wedge-Bonden)方法形成的球形键合。然后，按压半导体构件到电路载体上，从而在印制导线和钉头凸点部分地变形的情况下构造电连接。在借助非导电胶粘剂(NCA，非导电胶粘剂)的倒装芯片方法中，在按压之前或者之后将粘合剂置于芯片和电路载体之间，所述粘合剂然后硬化。
尤其在电路载体的不平整的表面——该表面过渡到印制导线的表面——的情况下，可能在按压钉头凸点的情况下发生不可靠的电接触，因为基于不平整性，局部不同的按压力发生作用。由此，印制导线可能由于其小的高度容易被破坏或者说机械变形，并且位于其下方的电路载体也可能塑性变形。此外，各个凸出的区域可能导致损坏或机械紧固。
为此，在WO 02/056345 A2中提出一种倒装芯片连接，在所述倒装芯片连接中，钉头凸点不仅仅施加在半导体构件的接触位置上，而且也施加在印制导线上或者电路载体的接触盘上。为了构造均质的接触表面，通过压印使钉头凸点平坦化，从而补偿在电路载体和半导体构件上的、也传递到接触表面上的不平整性，并且因此，钉头凸点的接触表面大致位于电路载体或者说半导体构件之上的大约相等的高度上。接着，半导体构件的和电路载体的钉头凸点相对于彼此对齐地叠置并且在键合方法中接合在一起，其方式是，加热、彼此相对地按压和附加地以超声处理所述钉头凸点，以便实现接触材料在两个钉头凸点的接触表面上的扩散。由此构造电连接和机械连接。
发明内容
根据本发明设置，电路载体、尤其注塑的电路载体(模塑互联器件，MID，molded interconnect device)和优选单片的半导体构件(芯片，裸芯片)在倒装芯片方法中相互连接和接通，其中，对着施加在半导体构件上的第二接触单元按压与电路载体连接的和经平坦化的第一接触单元，并且附加地使至少部分地包围两个接触单元的粘接剂硬化，以便持久地连接两个彼此相对地按压的接触单元。由此构造倒装芯片电路装置。
在此，第一和第二接触单元优选实施为金块或者金球，即所谓的钉头凸点，所述第一和第二接触单元与在球楔键合方法中的球形键合部类似地施加到半导体构件上的接触位置上并且施加到电路载体上的接通面——例如由电镀结构例如铜、镍/磷和金电镀的印制导线——上。
由此已经能够实现一些优点。
因此，通过在两个待接通的元件上使用钉头凸点来实现，在按压时在电路载体和钉头凸点之间布置的、例如作为印制导线使用的接通面较不强烈地受压。因此通过在印制导线上施加的钉头凸点，“变形平面”在按压时从印制导线优选向上移动到钉头凸点中，并且因此发生作用的表面负荷从电路载体和印制导线向上迁移，从而在按压时力主要作用到钉头凸点的接触表面上并且仅仅小的通过钉头凸点所传递的力作用到印制导线上。由此能够例如强烈地降低在表面负荷中的、可能导致电路载体和印制导线的损坏的峰值，并且因此能够避免印制导线和由塑料制造的电路载体的变形；改善接触的可靠性。
此外，能够通过第一接触单元的平坦化补偿电路载体的表面上的不平整性，所述不平整性可能位于10μm-20μm的数量级中。这在倒装芯片制造过程中具有以下优点：能够防止接触单元由于各个突出的接触单元在按压时的损坏。
在此，在本发明的范畴内，平坦化或者平整化理解为，使接触表面与第一接触单元至少部分地相适应，即在一个公差内位于第一接触平面中。这可以例如机械地、例如通过置于接触表面上的凸模或者通过材料侵蚀——例如通过激光烧蚀来确保。但也可以考虑其他的使接触表面移动到平面或者接触平面中的方法。在平整化时，优选也略微增大接触表面的面积，因为在平整化时，接触材料也部分地被推开至侧面。在此，公差尤其为由制造决定的公差，例如由于凸模的粗糙度或另外的在平坦化过程中出现的处理精度，所述公差可以位于几百纳米的范围内。
与在WO 02/056345A2中所设置的键合过程——其中接触单元相对彼此被按压、加热和借助超声处理——中不同地，根据本发明优选不发生接触材料——例如金的扩散；因此，所述接触单元不像尤其在键合时那样被焊接，而是根据本发明优选相叠地按压并且仅仅通过经硬化的粘合剂保持相互靠近。
由此可以以有利的方式使制造费用保持小，因为在所述制造中不需要附加的方法步骤，如例如借助超声的处理。此外，可以通过省去超声处理来避免接触单元和整个倒装芯片电路装置的附加要求。
优选在按压之前如此施加粘接剂到电路载体上，使得所述粘接剂优选完全覆盖第一接触单元和接触表面，其中，粘接剂也可以分布在直接邻近的接通面(印制导线)上。在此，例如如此选择粘接剂的量，使得粘接剂在两个接触单元的按压之后完全填充电路载体和半导体构件之间的间隙，即基本上完全地贴靠电路载体的和半导体构件的表面，以便在硬化之后提高两个元件的机械连接的稳定性。在此，优选仅仅通过以下方式实现机械接合：粘接剂将半导体构件与电路载体连接或者粘接并且因此接触单元保持相互靠近。原则上，也可能的是，粘接剂附加地或者取而代之地施加到半导体构件的表面上。
接着，半导体构件的、在由制造决定的公差之内形成第二接触平面的第二接触单元相对于第一接触单元对准并且相互靠近，直到它们碰触到，其中，第一和第二接触平面平行于彼此平放。随后，按压第二接触单元到第一接触单元上，从而粘接剂被挤出到侧面并且在侧面在接触单元周围、也在接触表面的区域中铺设。因此，两个接触单元的接触表面相对于彼此处于电接触中，即粘接剂几乎完全从接触表面之间的间隙中挤出。
在此，粘接剂例如为非导电胶(NCA，non conductive adhesive)，以便以有利的方式防止，通过粘接剂将相互邻近的接通面和钉头凸点相互电连接。也可以考虑，附加地使用导电粘接剂、例如银导电胶，其例如仅仅局部地施加在接触表面的区域中，优选在施加非导电粘接剂之前。在按压时，首先将非导电粘接剂挤出直到两个接触单元碰触到导电粘接剂并且同样将所述导电粘接剂挤出，其中，所述导电粘接剂然后至少部分地也可以残留在接触表面之间的间隙中，以便补偿例如小的公差。此外，可以改善电过渡，因为能够减少或者说避免接触表面之间的非导电粘接剂的夹杂物。
为了使粘接剂硬化，优选加热所述粘接剂。为此，视粘接剂而定地设置大约250°的温度。有帮助地，通过温度提高也加热接触单元，由此所述接触单元变得更软并且因此可以更容易变形。由此，优选不实现接触材料的扩散、即接触单元的焊接在一起。
通过加热接触单元也可以以有利的方式实现不同地成形的接触表面的相互匹配。在此，在按压时，例如使所述一个接触表面的各个突出的区域如此机械变形，使得它们与相对置的接触表面相适应并且因此改善电过渡。
在此，制造步骤可以改变。因此，第二接触单元的施加例如与第一接触单元的施加和平坦化无关，即在时间上可以在其之前或者之后发生。
附图说明
附图示出：
图1示出电路载体和半导体构件在接通之前的示意性视图，
图2示出根据图1的、具有所施加的接通面的电路载体，
图3示出根据图2的、具有施加到接通面上的第一接触单元的电路载体，
图4示出使第一接触单元平坦化的步骤，
图5示出在接通之前的倒装芯片电路装置，
图6示出接通的倒装芯片电路装置，以及
图7示出根据本发明的方法的流程图。
具体实施方式
为了构造在图6中所示出的倒装芯片电路装置3，首先根据图1提供电路载体1——例如电路板、尤其注塑的电路载体(模塑互联器件，MID，molded interconnect device)和单片的半导体构件2或者说芯片或者裸芯片。电路载体1由非导电材料、优选塑料制造并且具有不平整的表面4，其中，在制造时和通过附加的表面处理(激光处理)可能出现不平整性。芯片2具有表面5，在该表面上布置有多个相互隔离的接触位置6——例如接触盘，所述接触位置与集成的开关电路在芯片2中连接。
为了将电路载体1与芯片2连接，首先设置，在电路载体1上施加接通面7——例如印制导线和/或接触盘——或者提供具有已经处理的接通面7的电路载体1。为此，根据图2，例如在电镀过程中施加导电层——例如由相应的由铜、镍/磷和金制成的电镀结构——到经表面处理的表面4上，从而构造尽可能无缺陷的接通面7。在此，接通面7形成电路图，该电路图在表面4上基本上沿x方向和y方向延伸，其中，y方向在图中垂直于图平面地定向。分布在表面4上的接通面7的高度、即在z方向上的延展是大致相等的并且为大约10μm至20μm。
由于电路载体1的不平整性，这些接通面7在z方向上相对于彼此移位，即在z方向上的相对定位改变；因此，在表面4上的不平整性也传递到接通面7上。
为了补偿所述移位，在根据本发明的方法中尤其设置，施加第一接触单元8.1、8.2到接通面7上(St1)。在此，第一接触单元8.1、8.2实施为所谓的钉头凸点。这些钉头凸点在键合方法中施加到接通面7上，所述键合方法例如为常规的球楔键合的一部分。
为此，球楔键合部的尖端被引至接通面7之上，并且接着加热由所述尖端突出的金引线，从而金熔化并且通过表面张力形成球(Ball)。该球借助短的超声脉冲压紧或者键合到接通面7上，从而在接通面7和球之间产生电连接。接着，在球的紧上方剪断金引线。球和被剪断的金引线形成钉头凸点，所述第一接触单元8.1、8.2。在此，钉头凸点的高度9.1、9.2为大约50μm并且可以具有大约1μm-2μm的由制造决定的公差。
此外，在施加第一接触单元8.1、8.2之后，所述第一接触单元在z方向上相对于彼此移位，因为表面4的不平整性通过接通面7也传递到钉头凸点8.1、8.2上，如尤其在图3中可以看出的那样。钉头凸点的由制造决定的公差可以在最大程度上保持不被考虑，因为该公差相对于表面4的可能位于10μm-20μm范围内的不平整性是可忽略的。
为了补偿所述不平整性，在以下的步骤St2中使第一接触单元8.1、8.2平坦化，即如此匹配其高度9.1、9.2，使得所有第一接触单元8.1、8.2的接触表面10.1、10.2以第一公差20位于共同的第一接触平面11中，根据图4，所述第一接触平面在x-y方向上延展。
为了进行平坦化，在此根据该实施，使用具有平整的下侧13的凸模12，所述凸模在整个电路载体1上延展或者在铺设到所述电路载体上时覆盖至少一个区域，待平坦化的第一接触单元8.1、8.2在电路载体1上布置在所述至少一个区域中。可以在所有三个空间方向上例如由通过控制装置12.1控制的伺服电动机12.2调节凸模12的或者说下侧13的位置。
为此，由伺服电动机12.2使凸模12从上方靠近第一接触单元8.1、8.2并且如此定向，使得下侧13平行于之前所确定的第一接触平面11。接着，下侧13以如此程度向下行进，直到该下侧碰触到各个突出的第一接触单元8.1、8.2或者它们的接触表面10.1、10.2。随后，以均匀的力沿按压方向R按压凸模12到接触表面10.1、10.2上，从而第一接触单元8.1、8.2机械变形，由此减小所述第一接触单元的高度9.1、9.2并且使每一个接触单元8.1、8.2的接触表面10.1、10.2平整并且因此略微增大接触表面的面积。大约以如此程度按压凸模12，直到下侧13靠触所有接触单元8.1、8.2，并且因此也碰触到最邻近地位于表面4上的接触单元8.1、8.2。整体上，如此强烈地在按压方向R上调节凸模12，直到所有接触表面10.1、10.2在由制造决定的第一公差20之内位于第一接触平面11中，并且此外使得每一个接触表面10.1、10.2平整。
因此，通过平坦化实现第一接触平面11，可以施加布置在半导体构件2上的第二接触单元15.1、15.2到该第一接触平面上。在此，第二接触单元15.1、15.2根据图5同样实施为钉头凸点，所述钉头凸点施加到接触位置6上，例如在步骤St1.1中与钉头凸点施加到接通面7上一起。第二接触单元15.1、15.2以其接触表面16.1、16.2限定第二接触平面17，所述第二接触平面由制造决定地可以具有1μm-2μm的第二公差21。
在第二接触单元15.1、15.2施加到第一接触单元8.1、8.2上之前，在步骤St3中，将粘接剂18——例如非导电环氧树脂胶(NCA，non-conductiveadhesive：非导电粘结剂)如此施加到电路载体1的表面4上，使得完全覆盖第一接触单元8.1、8.2并且也完全覆盖周围的区域，如尤其在图5中所示出的那样。附加地，可以在施加非导电粘接剂18之前将导电粘接剂18.1局部地施加到接触表面10.1、10.2上，而两个邻近的第一接触单元8.1、8.2不因此相互接通。接着，相对于电路载体1如此定向半导体构件2，使得对应于第一接触单元8.1、8.2的第二接触单元15.1、15.2上下相叠地定位并且平面11和17平行于彼此。随后，在步骤St4中，使半导体构件2靠近电路载体1，直到第二接触单元15.1、15.2碰触到第一接触单元8.1、8.2，并且如此彼此相对按压，使得粘接剂18被挤到侧面并且在两个接触单元8.1、8.2、10.1、10.2周围铺设并且优选完全包围它们。在此，优选完全以粘接剂18填充电路载体1和半导体构件2之间的间隙，如在图6中所示出的那样。导电粘接剂18.1也被挤到侧面，但是至少部分地残留在接触表面10.1、10.2、16.1、16.2之间的间隙中。
为了使两个接触单元8.1、8.2、15.1、15.2持久地相互连接，在接着的步骤St5中使粘接剂18硬化；在此，可以略微收缩(zusamenziehen)粘接剂18，以致于半导体构件2绷紧到电路载体1上。因此，粘接剂18负责使两个接触单元8.1、8.2、15.1、15.2粘牢。因此，优选首先通过粘接剂18实现机械粘牢，所述粘接剂将半导体构件2保持在电路载体1上。为了进行硬化，至少加热在接触表面8.1、8.2、15.1、15.2周围的区域，其中，视粘接剂18而定地将温度调节到250°以内。
通过加热有帮助地，接触表面10.1、10.2、16.1、16.2也变得较软，从而所述接触表面在按压时由于机械变形能够相互匹配，即可以附加地补偿接触表面10.1、10.2、16.1、16.2中的小的不平整性和由制造决定的公差。在粘接剂18的硬化之后，完成根据图6的倒装芯片电路装置3。

Claims (16)

1.一种用于制造倒装芯片电路装置(3)的方法，所述方法具有至少以下步骤：
制造或者提供具有第一表面(4)和施加到所述第一表面上的接通面(7)的电路载体(1)以及具有第二表面(5)和施加到所述第二表面上的接触位置(6)的半导体构件(2)(St0)，
施加第一接触单元(8.1，8.2)到所述接通面(7)上(St1)，
施加与所述第一接触单元(8.1，8.2)对应的第二接触单元(15.1，15.2)到所述接触位置(6)上(St1.1)，
如此使所述第一接触单元(8.1，8.2)平坦化，使得所述第一接触单元(8.1，8.2)的接触表面(10.1，10.2)在第一公差(20)之内限定共同的第一接触平面(11)(St2)，
施加粘接剂(18)到所述第一接触单元(8.1，8.2)和/或所述第二接触单元(15.1，15.2)上(St3)，
按压所述半导体构件(2)和所述电路载体(1)以便构成所述第一和第二接触单元(8.1，8.2，15.1，15.2)之间的电连接(St4)，以及
使所述粘接剂(18)硬化以便建立半导体构件(2)和电路载体(1)之间的机械连接(St5)。
2.根据权利要求1所述的方法，其特征在于，在所述按压之前在所述对应于所述第二接触单元的第一接触单元(8.1，8.2)上对准所述第二接触单元(15.1，15.2)。
3.根据权利要求2所述的方法，其特征在于，在所述对准时大致与由所述第二接触单元(15.1，15.2)的接触表面(16.1，16.2)在第二公差(21)之内所限定的第二接触平面(17)平行地调节所述第一接触平面(11)。
4.根据以上权利要求中任一项所述的方法，其特征在于，如此施加所述粘接剂(18)到所述电路载体(1)上，使得所述第一和/或第二接触单元(8.1，8.2，15.1，15.2)完全被覆盖并且所述粘接剂(18)在所述按压之后贴靠所述第一表面(4)和所述第二表面(5)。
5.根据以上权利要求中任一项所述的方法，其特征在于，所述粘接剂(18)为非导电胶，并且如此按压所述半导体构件(2)和所述电路载体(1)，使得所述粘接剂(18)至少部分地从所述第一接触单元(8.1，8.2)的接触表面(10.1，10.2)和所述第二接触单元(15.1，15.2)的接触表面(16.1，16.2)之间的间隙中挤出。
6.根据以上权利要求中任一项所述的方法，其特征在于，在施加所述粘接剂(18)之前附加地将导电粘接剂(18.1)局部地施加到所述第一接触单元(8.1，8.2)的所述接触表面(10.1，10.2)上和/或所述第二接触单元(8.1，8.2)的所述接触表面(16.1，16.2)上。
7.根据以上权利要求中任一项所述的方法，其特征在于，加热所述粘接剂(18)用于硬化。
8.根据以上权利要求中任一项所述的方法，其特征在于，机械式地实施所述平坦化的步骤。
9.根据权利要求8所述的方法，其特征在于，借助于具有平整的下侧(12)的凸模(12)实施所述平坦化，其中，使所述凸模(12)靠近所述第一接触单元(8.1，8.2)的所述接触表面(10.1，10.2)并且接着借助恒定的力使所述凸模如此朝按压方向(R)行进，使得所述第一接触单元(8.1，8.2)变形。
10.根据以上权利要求中任一项所述的方法，其特征在于，通过球形键合施加所述第一和/或第二接触单元(8.1，8.2，15.1，15.2)以便形成钉头凸点。
11.根据以上权利要求中任一项所述的方法，其特征在于，使用注塑的、由塑料制成的电路载体——例如MID(molded interconnect device：模塑互联器件)作为电路载体(1)并且使用单片的构件作为半导体构件(2)。
12.一种倒装芯片电路装置(3)，其至少具有：
具有多个接通面(7)的电路载体(1)，第一接触单元(8.1，8.2)施加在所述多个接通面上，
具有接触位置(6)的半导体构件(2)，第二接触单元(15.1，15.2)分别施加在所述接触位置上，
其中，所述第一接触单元(8.1，8.2)具有接触表面(10.1，10.2)，所述接触表面在第一公差(20)之内位于第一接触平面(11)中，并且所述接触表面与所述第二接触单元(15.1，15.2)接通，
其中，所述第一接触单元(8.1，8.2)和所述第二接触单元(8.1，8.2)通过至少包围所述第一和第二接触单元(8.1，8.2，15.1，15.2)的粘接剂(18)相互机械连接。
13.根据权利要求12所述的倒装芯片电路装置(3)，其特征在于，所述第一和第二接触单元(8.1，8.2，15.1，15.2)仅仅通过所述粘接剂(18)相互机械连接，其中，所述粘接剂(18)贴靠在所述电路载体(1)的第一表面(4)上和在所述半导体构件(2)的第二表面(5)上。
14.根据权利要求12或13所述的倒装芯片电路装置(3)，其特征在于，所述电路载体(1)为注塑的、由塑料制成的电路载体，例如MID(moldedinterconnect device：模塑互联器件)。
15.根据权利要求12至14中任一项所述的倒装芯片电路装置(3)，其特征在于，所述第一和/或第二接触单元(8.1，8.2，15.1，15.2)为钉头凸点。
16.根据权利要求12至15中任一项所述的倒装芯片电路装置(3)，其特征在于，所述粘接剂(18)为非导电胶，并且在所述接触表面(10.1，10.2，16.1，16.2)的区域中附加地布置有导电粘接剂(18.1)。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1130306A (zh) * 1994-12-26 1996-09-04 松下电器产业株式会社 半导体器件及其制造方法
CN1392024A (zh) * 2002-06-28 2003-01-22 威盛电子股份有限公司 高分辨率焊接凸块形成方法
CN1519892A (zh) * 2003-01-21 2004-08-11 颀邦科技股份有限公司 消除晶圆及晶粒上金属凸块的高度差异的方法
CN1619807A (zh) * 2004-12-06 2005-05-25 友达光电股份有限公司 包括集成电路芯片的基板及其上的集成电路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020093108A1 (en) 2001-01-15 2002-07-18 Grigorov Ilya L. Flip chip packaged semiconductor device having double stud bumps and method of forming same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1130306A (zh) * 1994-12-26 1996-09-04 松下电器产业株式会社 半导体器件及其制造方法
CN1392024A (zh) * 2002-06-28 2003-01-22 威盛电子股份有限公司 高分辨率焊接凸块形成方法
CN1519892A (zh) * 2003-01-21 2004-08-11 颀邦科技股份有限公司 消除晶圆及晶粒上金属凸块的高度差异的方法
CN1619807A (zh) * 2004-12-06 2005-05-25 友达光电股份有限公司 包括集成电路芯片的基板及其上的集成电路

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