CN104810297A - Method for manufacturing a flip chip circuit device and the flip chip circuit device - Google Patents
Method for manufacturing a flip chip circuit device and the flip chip circuit device Download PDFInfo
- Publication number
- CN104810297A CN104810297A CN201510028691.0A CN201510028691A CN104810297A CN 104810297 A CN104810297 A CN 104810297A CN 201510028691 A CN201510028691 A CN 201510028691A CN 104810297 A CN104810297 A CN 104810297A
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- Prior art keywords
- osculating element
- circuit carrier
- bonding agent
- contact
- osculating
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- 238000009792 diffusion process Methods 0.000 description 3
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Classifications
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a method for manufacturing a flip chip circuit device, with at least the following steps: producing or providing a circuit carrier with a first surface and and a conductive face applied on the first surface, and a semiconductor component with a second surface and and a contact point applied on the second surface; applying a first contact unit on the conductive face, and applying a second contact unit corresponding to the first contact unit to the contact point, to smooth the first contact unit, and to make a contact surface of the first contact uint limit a common first contact plane within a first tolerance; applying adhesive on the first contact unit and/or second contact unit; and pressing the semiconductor component and the circuit carrier to form electric connection between the first contact unit and the second contact unit, and to hard the adhesive to establish mechanical connection between the semiconductor component and the circuit carrier.
Description
Technical field
The present invention relates to a kind of method for the manufacture of flip-chip circuit device and the corresponding flip-chip circuit device of one.
Background technology
In flip-chip assemblies technology, such as individual pieces of semiconductor elements (chip, bare chip (Die)) is effectively connected side with it and directly assemble and be switched to circuit carrier on---such as substrate or circuit board---.The contact position of semiconductor element when this without connecting lead wire (wire bonding) with the connection face on circuit carrier---such as printed conductor is connected.Little area requirements can be realized thus.
For this reason, the contact position that the stud bump (Stud-Bump) be made of gold is applied to semiconductor component such as, be routed on the printed conductor of circuit carrier subsequently, wherein, described stud bump is equivalent to the ball bond that formed by ball Wedge Bond (Ball-Wedge-Bonden) method of routine.Then, pressing semiconductor component is on circuit carrier, thus the structure electrical connection when printed conductor and stud bump are partly out of shape.In the Flipchip method by non-conductive adhesive (NCA, non-conductive adhesive), be placed between chip and circuit carrier before depression or afterwards by adhesive, then described adhesive hardens.
Especially on the irregular surface of circuit carrier---this surface transition is to surface of printed conductor---, when pressing stud bump, insecure electrical contact may occur, because based on out-of-flatness, the different pressing force in local is had an effect.Thus, printed conductor due to the easily destroyed mechanical deformation in other words of its little height, and may be positioned at the circuit carrier also possibility plastic deformation below it.In addition, each region of protruding may cause damaging or mechanical fasteners.
For this reason, in WO 02/056345 A2, propose a kind of flip-chip connect, in described flip-chip connects, stud bump is not only applied on the contact position of semiconductor component, and be applied on printed conductor or circuit carrier contact disc on.In order to construct the contact surface of homogeneous, stud bump planarization is made by impression, thus compensate on circuit carrier and semiconductor component, be also delivered to out-of-flatness on contact surface, and therefore, the contact surface of stud bump is roughly positioned on the approximately equal height of circuit carrier in other words on semiconductor component.Then, semiconductor component relative to each other stacked alignedly and be bonded together in bonding method with the stud bump of circuit carrier, its mode is, heating, relative to one another pressing and additionally with the described stud bump of ultrasonic process, to realize the diffusion of contact material on the contact surface of two stud bump.Structure electrical connection and mechanical connection thus.
Summary of the invention
Arranged according to the present invention, circuit carrier, especially circuit carrier (the molding interconnection element of injection moulding, MID, molded interconnect device) and the semiconductor component (chip of preferred monolithic, bare chip) be interconnected in Flipchip method and connect, wherein, that be connected with circuit carrier facing to the second osculating element pressing be applied on semiconductor component and through the first osculating element of planarization, and additionally make the adhesive hardens of surrounding two osculating elements at least in part, to connect two osculating elements pressed relative to one another enduringly.Construct flip-chip circuit device thus.
At this, first and second osculating elements are preferably embodied as gold bullion or gold goal, i.e. so-called stud bump, on described first and second osculating elements and the contact position be applied to like ball bond category in ball Wedge Bond method on semiconductor component and on the connection face be applied on circuit carrier---printed conductor such as electroplated by electroplated structural such as copper, nickel/phosphorus and gold---.
Can realize some advantages thus.
Therefore, by using stud bump to realize on two elements to be connected, connection face that arrange between circuit carrier and stud bump when pressing, that such as use as printed conductor pressurized more consumingly.Therefore the stud bump by applying on printed conductor, " deformation plane " is preferably moved upwards up to stud bump from printed conductor when pressing, and the surface loading of therefore having an effect upwards moves from circuit carrier and printed conductor, thus on the contact surface of advocating to be applied to stud bump when pressing and only the little power transmitted by stud bump is applied on printed conductor.Such as can be reduced in surface loading, that the damage of circuit carrier and printed conductor may be caused peak value consumingly thus, and therefore, it is possible to the distortion of circuit carrier avoided printed conductor and manufactured by plastics; Improve the reliability of contact.
In addition, can by the out-of-flatness on the surface of the flattening compensation circuit carrier of the first osculating element, described out-of-flatness may be arranged in the order of magnitude of 10 μm-20 μm.This has the following advantages in flip-chip manufacture process: osculating element can be prevented due to each damage of outstanding osculating element when pressing.
At this, in category of the present invention, planarization or leveling are interpreted as, contact surface and the first osculating element are adapted at least in part, namely in a tolerance, is arranged in the first contact plane.This can such as mechanically, such as by being placed in punch on contact surface or by material corrosion---such as guaranteed by laser ablation.But also can consider that other the contact surface that makes moves to method in plane or contact plane.When leveling, preferably also slightly increase the area of contact surface, because when leveling, contact material is also partly open to side.At this, tolerance is especially that such as due to roughness or the other processing accuracy occurred in planarization process of punch, described tolerance can be positioned at the scope of hundreds of nanometer by manufacturing the tolerance determined.
With bonding process set in WO 02/056345A2 in---wherein osculating element is pressed relative to each other, heats and by ultrasonic process---differently, preferably do not come in contact material according to the present invention---the such as diffusion of gold; Therefore, described osculating element is soldered unlike especially when bonding, but according to the present invention's preferably pressing stackedly and keep close to each other only by the adhesive through sclerosis.
Manufacturing expense can be made thus in an advantageous manner to keep little, because do not need the method step added in described manufacture, as such as by ultrasonic process.In addition, the additional requirement of osculating element and whole flip-chip circuit device can be avoided by saving ultrasonic process.
Preferably so apply bonding agent before depression on circuit carrier, make described bonding agent preferably cover the first osculating element and contact surface completely, wherein, bonding agent also can be distributed on directly contiguous connection face (printed conductor).At this, such as so select the amount of bonding agent, make bonding agent after the pressing of two osculating elements, fill gap between circuit carrier and semiconductor component completely, namely substantially fully recline circuit carrier with the surface of semiconductor component, to improve the stability of the mechanical connection of two elements after the hardening.At this, preferably realize mechanical engagement only by with under type: bonding agent semiconductor component is connected with circuit carrier or bonding and therefore osculating element keep close to each other.In principle, also possible that, bonding agent additionally or is instead applied on the surface of semiconductor component.
Then, semiconductor component, to aim at relative to the first osculating element and close to each other by manufacturing the second osculating element forming the second contact plane within the tolerance that determines, until they touch, wherein, the first and second contact planes are parallel to and keep flat each other.Subsequently, press the second osculating element on the first osculating element, thus bonding agent is expressed into side and lays in the region of contact surface around osculating element, also in side.Therefore, the contact surface of two osculating elements is relative to each other in electrical contact, and namely bonding agent is almost extruded complete gap between contact surface.
At this, bonding agent is such as non-conductive adhesive (NCA, non conductive adhesive), to prevent in an advantageous manner, is electrically connected to each other in mutually contiguous connection face and stud bump by bonding agent.Also can consider, additionally use electrically conducting adhesive, such as silver conductive adhesive, it is such as only applied in the region of contact surface partly, preferably before applying non-conductive adhesive.When pressing, first non-conductive adhesive is extruded until two osculating elements touch electrically conducting adhesive and extruded by described electrically conducting adhesive equally, wherein, then described electrically conducting adhesive also can remain in the gap between contact surface at least in part, to compensate such as little tolerance.In addition, electric transition can be improved, because the field trash of the non-conductive adhesive avoided in other words between contact surface can be reduced.
In order to make adhesive hardens, the preferably described bonding agent of heating.For this reason, the temperature of about 250 ° is set depending on bonding agent.Helpfully, improve also also contacts unit by temperature, described osculating element becomes softer and therefore can more easily be out of shape thus.Thus, welding together of diffusion, the i.e. osculating element of contact material is not preferably realized.
Also the mutual coupling of the contact surface be differently shaped can be realized in an advantageous manner by also contacts unit.At this, when pressing, such as, make each outstanding region mechanical deformation like this of a described contact surface, make them adapt with opposite contact surface and therefore improve electric transition.
At this, manufacturing step can change.Therefore, the applying of the second osculating element such as has nothing to do with the applying of the first osculating element and planarization, namely can occur before it or afterwards in time.
Accompanying drawing explanation
Accompanying drawing illustrates:
Fig. 1 illustrates circuit carrier and semiconductor component explanatory view before turn,
Fig. 2 illustrate according to Fig. 1, the circuit carrier with applied connection face,
Fig. 3 illustrate according to Fig. 2, the circuit carrier of the first osculating element had on the connection face of being applied to,
Fig. 4 illustrates the step making the first osculating element planarization,
Fig. 5 illustrates flip-chip circuit device before turn,
Fig. 6 illustrates the flip-chip circuit device of connection, and
Fig. 7 illustrates the flow chart according to method of the present invention.
Embodiment
In order to be configured in the flip-chip circuit device 3 shown in Fig. 6, first circuit carrier 1 is provided according to Fig. 1---circuit carrier (the molding interconnection element of such as circuit board, especially injection moulding, MID, molded interconnect device) and semiconductor component 2 chip or the bare chip in other words of monolithic.Circuit carrier 1 is by non-conducting material, preferably plastics manufacture and have irregular surperficial 4, wherein, may occur out-of-flatness during fabrication and by additional surface treatment (laser treatment).Chip 2 has surface 5, is furnished with multiple mutually isolated contact position 6 on a surface---and such as contact disc, described contact position is connected in chip 2 with integrated switching circuit.
In order to be connected with chip 2 by circuit carrier 1, first arrange, circuit carrier 1 apply connection face 7---such as printed conductor and/or contact disc---or the circuit carrier 1 with treated connection face 7 is provided.For this reason, according to Fig. 2, such as, in electroplating process, apply conductive layer---such as by the corresponding electroplated structural be made up of copper, nickel/phosphorus and gold---on surface treated surperficial 4, thus the flawless as far as possible connection face 7 of structure.At this, connection face 7 forms circuit diagram, and this circuit diagram extends with y direction on the surface 4 substantially in the x-direction, and wherein, y direction is directed perpendicular to plan ground in the drawings.The height in distribution connection face 7 on the surface 4, i.e. extension are in a z-direction roughly equal and are about 10 μm to 20 μm.
Due to the out-of-flatness of circuit carrier 1, these connection faces 7 are relative to each other shifted in a z-direction, and namely relative positioning in a z-direction changes; Therefore, out-of-flatness on the surface 4 is also delivered on connection face 7.
In order to compensate described displacement, especially arranging in the method according to the invention, applying the first osculating element 8.1,8.2 to (St1) on connection face 7.At this, the first osculating element 8.1,8.2 is embodied as so-called stud bump.These stud bump are applied on connection face 7 in bonding method, and described bonding method is such as a part for conventional ball Wedge Bond.
For this reason, the tip in ball Wedge Bond portion is directed on connection face 7, and then heats the gold wire given prominence to by described tip, thus gold melts and forms ball (Ball) by surface tension.This ball by short ultrasonic pulse compression or the connection face of being bonded to 7, thus produces electrical connection between connection face 7 and ball.Then, gold wire is cut off the immediately above of ball.Ball and formed stud bump, described first osculating element 8.1,8.2 by the gold wire cut off.At this, the height of stud bump 9.1,9.2 for about 50 μm and can have about 1 μm-2 μm by manufacturing the tolerance determined.
In addition, after applying first osculating element 8.1,8.2, described first osculating element is relative to each other shifted in a z-direction, because the out-of-flatness on surface 4 is also delivered in stud bump 8.1,8.2, as can be found out especially in figure 3 by connection face 7.The tolerance determined by manufacture of stud bump can keep not being considered to the full extent, because this tolerance is insignificant relative to the out-of-flatness that may be positioned at 10 μm of-20 μm of scopes on surface 4.
In order to compensate described out-of-flatness, the first osculating element 8.1,8.2 planarization is made in following step St2, namely its height 9.1,9.2 is so mated, the contact surface 10.1,10.2 of all first osculating elements 8.1,8.2 is made to be arranged in the first common contact plane 11 with the first tolerance 20, according to Fig. 4, described first contact plane extends in x-y direction.
In order to carry out planarization, at this according to this enforcement, use the punch 12 with smooth downside 13, described punch extends or covers at least one region when being routed on described circuit carrier on whole circuit carrier 1, treats that the first osculating element 8.1,8.2 of planarization is arranged at least one region described on circuit carrier 1.The position of the downside 13 in other words of punch 12 such as can be regulated in all three spatial directions by the servomotor 12.2 controlled by control device 12.1.
For this reason, make punch 12 near the first osculating element 8.1,8.2 and so directed from top by servomotor 12.2, make downside 13 be parallel to before determined first contact plane 11.Then, advance downwards with degree like this in downside 13, until touch each the first outstanding osculating element 8.1,8.2 or their contact surface 10.1,10.2 on the downside of this.Subsequently, punch 12 is pressed on contact surface 10.1,10.2 along pressing direction R with uniform power, thus the first osculating element 8.1,8.2 mechanical deformation, reduce the height 9.1,9.2 of described first osculating element thus and make the contact surface 10.1 of each osculating element 8.1,8.2,10.2 smooth and therefore slightly increase the area of contact surface.Approximately with degree pressing punch 12 like this, until downside 13 is by touching all osculating elements 8.1,8.2, and therefore also touch the osculating element 8.1,8.2 be positioned adjacently at most on surface 4.On the whole, on pressing direction R, regulating punch 12 so consumingly, until all contact surfaces 10.1,10.2 are being arranged in the first contact plane 11 by manufacturing within the first tolerance 20 of determining, and making each contact surface 10.1,10.2 smooth in addition.
Therefore, realize the first contact plane 11 by planarization, can apply to be arranged in the second osculating element 15.1,15.2 on semiconductor component 2 on this first contact plane.At this, the second osculating element 15.1,15.2 is embodied as stud bump equally according to Fig. 5, and described stud bump is applied on contact position 6, such as, together with being applied to stud bump in step St1.1 on connection face 7.Second osculating element 15.1,15.2 limits the second contact plane 17 with its contact surface 16.1,16.2, by manufacturing, described second contact plane determines that ground can have second tolerance 21 of 1 μm-2 μm.
Before the second osculating element 15.1,15.2 is applied on the first osculating element 8.1,8.2, in step St3, by bonding agent 18---such as non-conductive epoxy glue (NCA, non-conductiveadhesive: non-conductive binding agent) be so applied on the surface 4 of circuit carrier 1, make to cover the first osculating element 8.1,8.2 completely and the region also covering surrounding completely, as especially in Figure 5.Additionally, before applying non-conductive adhesive 18, electrically conducting adhesive 18.1 can be applied on contact surface 10.1,10.2 partly, and therefore the first osculating element 8.1,8.2 of two vicinities is not connected mutually.Then, directed semiconductor component 2 like this relative to circuit carrier 1, makes the second osculating element 15.1, about 15.2 corresponding to the first osculating element 8.1,8.2 locate stackedly and plane 11 and 17 is parallel to each other.Subsequently, in step St4, make semiconductor component 2 near circuit carrier 1, until the second osculating element 15.1,15.2 touches the first osculating element 8.1,8.2, and so press toward each other, make bonding agent 18 be pressed against side and lay around two osculating elements 8.1,8.2,10.1,10.2 and preferably surround them completely.At this, fill gap between circuit carrier 1 and semiconductor component 2 with bonding agent 18 preferably completely, as illustrated in Figure 6.Electrically conducting adhesive 18.1 is also pressed against side, but remains at least in part in the gap between contact surface 10.1,10.2,16.1,16.2.
In order to make two osculating elements 8.1,8.2,15.1,15.2 be interconnected enduringly, in step St5 then, bonding agent 18 is made to harden; At this, slightly can shrink (zusamenziehen) bonding agent 18, so that semiconductor component 2 is tightened on circuit carrier 1.Therefore, bonding agent 18 is responsible for two osculating elements 8.1,8.2,15.1,15.2 are cemented.Therefore, preferably first realize machinery by bonding agent 18 and cement, semiconductor component 2 remains on circuit carrier 1 by described bonding agent.In order to harden, at least heat the region around contact surface 8.1,8.2,15.1,15.2, wherein, 18 temperature is adjusted within 250 ° depending on bonding agent.
Helpful by heating, contact surface 10.1,10.2,16.1,16.2 also becomes softer, thus described contact surface can mate due to mechanical deformation mutually when pressing, little out-of-flatness in contact surface 10.1,10.2,16.1,16.2 namely additionally can be compensated and by manufacturing the tolerance determined.After the sclerosis of bonding agent 18, complete the flip-chip circuit device 3 according to Fig. 6.
Claims (16)
1., for the manufacture of a method for flip-chip circuit device (3), described method has at least following steps:
Manufacture or provide and there is first surface (4) and be applied to the circuit carrier (1) in the connection face (7) on described first surface and there is second surface (5) and be applied to semiconductor component (2) (St0) of the contact position (6) on described second surface
Apply the first osculating element (8.1,8.2) to described connection face (7) upper (St1),
Apply second osculating element (15.1,15.2) corresponding with described first osculating element (8.1,8.2) to described contact position (6) upper (St1.1),
So make described first osculating element (8.1,8.2) planarization, make described first osculating element (8.1,8.2) contact surface (10.1,10.2) limit within the first tolerance (20) common the first contact plane (11) (St2)
Apply bonding agent (18) to described first osculating element (8.1,8.2) and/or described second osculating element (15.1,15.2) upper (St3),
Press described semiconductor component (2) and described circuit carrier (1) to form the electrical connection (St4) between described first and second osculating elements (8.1,8.2,15.1,15.2), and
Described bonding agent (18) is hardened to set up the mechanical connection (St5) between semiconductor component (2) and circuit carrier (1).
2. method according to claim 1, is characterized in that, at described the first osculating element (8.1,8.2) described second osculating element of upper aligning (15.1,15.2) corresponding to described second osculating element before described pressing.
3. method according to claim 2, it is characterized in that, described to punctual roughly with by described second osculating element (15.1,15.2) the second contact plane (17) that contact surface (16.1,16.2) limits within the second tolerance (21) regulates described first contact plane (11) abreast.
4. the method according to any one of the preceding claims, it is characterized in that, the described bonding agent of applying like this (18) is on described circuit carrier (1), make the described first and/or second osculating element (8.1,8.2,15.1,15.2) described first surface (4) and described second surface (5) is capped and described bonding agent (18) reclines after described pressing completely.
5. the method according to any one of the preceding claims, it is characterized in that, described bonding agent (18) is non-conductive adhesive, and the so described semiconductor component of pressing (2) and described circuit carrier (1), make described bonding agent (18) at least in part from described first osculating element (8.1,8.2) contact surface (10.1,10.2) and described second osculating element (15.1,15.2) extrude in the gap between contact surface (16.1,16.2).
6. the method according to any one of the preceding claims, it is characterized in that, before the described bonding agent of applying (18), additionally electrically conducting adhesive (18.1) is applied to described first osculating element (8.1 partly, 8.2) described contact surface (10.1,10.2) upper and/or described second osculating element (8.1,8.2) on described contact surface (16.1,16.2).
7. the method according to any one of the preceding claims, is characterized in that, heats described bonding agent (18) for sclerosis.
8. the method according to any one of the preceding claims, is characterized in that, mechanically implements the step of described planarization.
9. method according to claim 8, it is characterized in that, described planarization is implemented by means of the punch (12) with smooth downside (12), wherein, make described punch (12) near described first osculating element (8.1,8.2) described contact surface (10.1,10.2) and then by constant power, described punch is so advanced towards pressing direction (R), described first osculating element (8.1,8.2) is out of shape.
10. the method according to any one of the preceding claims, is characterized in that, applies the described first and/or second osculating element (8.1,8.2,15.1,15.2) to form stud bump by ball bond.
11. methods according to any one of the preceding claims, it is characterized in that, to use injection moulding, the circuit carrier that is made of plastics---such as MID (molded interconnect device: molding interconnection element) uses the component of monolithic as semiconductor component (2) as circuit carrier (1).
12. 1 kinds of flip-chip circuit devices (3), it at least has:
Have the circuit carrier (1) of multiple connection face (7), the first osculating element (8.1,8.2) is applied on described multiple connection face,
Have the semiconductor component (2) of contact position (6), the second osculating element (15.1,15.2) is applied on described contact position respectively,
Wherein, described first osculating element (8.1,8.2) there is contact surface (10.1,10.2), described contact surface is arranged in the first contact plane (11) within the first tolerance (20), and described contact surface and described second osculating element (15.1,15.2) are connected
Wherein, described first osculating element (8.1,8.2) and described second osculating element (8.1,8.2) by least surrounding described first and second osculating elements (8.1,8.2,15.1,15.2) bonding agent (18) is mechanically connected mutually.
13. flip-chip circuit devices (3) according to claim 12, it is characterized in that, described first and second osculating elements (8.1,8.2,15.1,15.2) be mutually mechanically connected only by described bonding agent (18), wherein, it is upper and on the second surface (5) of described semiconductor component (2) that described bonding agent (18) abuts in the first surface (4) of described circuit carrier (1).
14. flip-chip circuit devices (3) according to claim 12 or 13, it is characterized in that, circuit carrier that described circuit carrier (1) is injection moulding, that be made of plastics, such as MID (moldedinterconnect device: molding interconnection element).
15., according to claim 12 to the flip-chip circuit device (3) according to any one of 14, is characterized in that, the described first and/or second osculating element (8.1,8.2,15.1,15.2) is stud bump.
16. according to claim 12 to the flip-chip circuit device (3) according to any one of 15, it is characterized in that, described bonding agent (18) is non-conductive adhesive, and at described contact surface (10.1,10.2,16.1,16.2) electrically conducting adhesive (18.1) is additionally furnished with in region.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102014201166.3 | 2014-01-23 | ||
DE102014201166.3A DE102014201166A1 (en) | 2014-01-23 | 2014-01-23 | Method for producing a flip-chip circuit arrangement and flip-chip circuit arrangement |
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CN104810297A true CN104810297A (en) | 2015-07-29 |
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CN201510028691.0A Pending CN104810297A (en) | 2014-01-23 | 2015-01-20 | Method for manufacturing a flip chip circuit device and the flip chip circuit device |
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DE (1) | DE102014201166A1 (en) |
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DE102020114669A1 (en) | 2020-06-02 | 2021-12-02 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | ELECTRICAL DEVICE |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1130306A (en) * | 1994-12-26 | 1996-09-04 | 松下电器产业株式会社 | Semiconductor and its producing method |
CN1392024A (en) * | 2002-06-28 | 2003-01-22 | 威盛电子股份有限公司 | Forming method for high resolution welding lug |
CN1519892A (en) * | 2003-01-21 | 2004-08-11 | 颀邦科技股份有限公司 | Method for eliminating height difference between metal lugs on wafer and crystal grain |
CN1619807A (en) * | 2004-12-06 | 2005-05-25 | 友达光电股份有限公司 | Substrate including integrated circuit chip and integrated circuit on said substrate |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020093108A1 (en) | 2001-01-15 | 2002-07-18 | Grigorov Ilya L. | Flip chip packaged semiconductor device having double stud bumps and method of forming same |
-
2014
- 2014-01-23 DE DE102014201166.3A patent/DE102014201166A1/en not_active Withdrawn
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2015
- 2015-01-20 CN CN201510028691.0A patent/CN104810297A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1130306A (en) * | 1994-12-26 | 1996-09-04 | 松下电器产业株式会社 | Semiconductor and its producing method |
CN1392024A (en) * | 2002-06-28 | 2003-01-22 | 威盛电子股份有限公司 | Forming method for high resolution welding lug |
CN1519892A (en) * | 2003-01-21 | 2004-08-11 | 颀邦科技股份有限公司 | Method for eliminating height difference between metal lugs on wafer and crystal grain |
CN1619807A (en) * | 2004-12-06 | 2005-05-25 | 友达光电股份有限公司 | Substrate including integrated circuit chip and integrated circuit on said substrate |
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