CN103199865A - Optical serial port self-adaptive decoding circuit - Google Patents
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Abstract
The invention relates to an optical serial port self-adaptive decoding circuit which can automatically judge whether an input code stream is an inter range instrumentation group B (IRIG-B) code stream or a FT3 code stream in terms of the type and decode the type of the code stream in a self-adaptive mode. The optical serial port self-adaptive decoding circuit comprises a self-adaptive module, a multiplex control module, an IRIG-B code decoding module, a FT3 code decoding module and a storage module. The self-adaptive module judges whether the input code stream is the IRIG-B code stream or the FT3 code stream in terms of the type through a high-frequency clock counting analysis mode; the multiplex control module distributes the input code stream to the corresponding IRIG-B code decoding module or the corresponding FT3 code decoding module according to the type of the input code stream provided by the self-adaptive module; and the storage module is used for storing decoded IRIG-B code time information and FT3 code information which can be read and checked by an external central processing unit (CPU). The decoding circuit is achieved based on a FPHA chip, and thus the decoding circuit has the advantages of being good in expansibility and operating real-time performance, simple in structure, low in power consumption, short in development period and low in development cost.
Description
Technical field
The present invention relates to a kind of decoding device, be specifically related to light serial ports self adaptation IRIG-B and the FT3 sign indicating number decoding circuit in the intelligent grid technical field, used.
Background technology
IRIG is the abbreviation of English Inter Range Instrumentation Group, it is the time encoding form that is put forward by instrument group between U.S. target range, become the universal standard in the world, in West Europe, countries and regions such as Japan, Australia have obtained using widely.IRIG timing code standard has two big classes.One class is parallel time sign indicating number form, and this class sign indicating number is owing to be parallel form, and transmission range is nearer, and is binary system, uses therefore that to can not show a candle to serial form extensive.Another kind of is the serial timing code, has six kinds of forms.Be IRIG-A, B, D, E, G, H.Their main difference is the frame rate difference of timing code, the G form from the D format of a slowest per hour frame to the fastest per ten millisecond of one frame.Wherein the B IRIG-B format time code since the time frame period be 1 second, be fit to people's demand, so IRIG-B uses the most generally the most at most, GPS is exactly that it one of is used.Along with intelligent grid equipment is more and more higher to the requirement of time unification, and therefore gps system has easy to use, advantages such as timing accuracy is high, signal stabilization have obtained extensive use in many Electric Power Automation Equipments.IRIG-B needs just can restore concrete temporal information through the decoding of signal in concrete the use.
FT3 is the frame format of stipulating in the IEC60044-8 standard, and it is the electronic current mutual inductor standard of being made by International Electrotechnical Commission (IEC).Electronic current mutual inductor is the visual plant in the electric power system, study it with the interface of electric substation automation system with communicate by letter, have great significance for the digitlization of transformer station.A lot of power system devices were all used and were supported the light digital signal of FT3 to insert present stage, and FT3 is very extensive in application on power system.
In order to realize detection, test and the control to the intelligent grid automation equipment, need to use the light digital test equipment that possesses the light digital interface, according to the intelligent substation actual conditions, these light digital test equipments need provide the light serial ports that is applicable to IEC60044-7/8 (FT3) message to insert, and be applicable to that light IRIG-B sign indicating number light serial ports inserts, realize the mutual of IEC60044-7/8 (FT3) light digital sample values SV message respectively and be used for the test of intelligent substation clock synchronization system.Utility model ZL201020526425 discloses a kind of protection, observing and controlling and merge cells integrated apparatus; wherein just provide independently light serial ports access respectively to FT3 signal and IRIG-B signal respectively; this demand must cause this smooth digital testing apparatus interface numerous; with high costs; power consumption is big, therefore how to solve IRIG-B sign indicating number and FT3 code self-adapting reception problem and have stronger realistic meaning in portable intelligent electrical network testing equipment.
Summary of the invention
In order to solve the problems of the technologies described above, the invention provides a kind of smooth serial ports adaptive de decoding circuit, the type that can judge input code flow automatically still is the FT3 code stream for the IRIG-B code stream, and decode at the code stream type adaptively, it is characterized in that: comprise adaptation module, multiplexing control module, IRIG-B sign indicating number decoder module, FT3 sign indicating number decoder module and memory module; Described adaptation module judges that by high-frequency clock count analysis mode the type of input code flow still is the FT3 code stream for the IRIG-B code stream; The type of the input code flow that described multiplexing control module provides according to adaptation module is distributed to corresponding IRIG-B sign indicating number decoder module with input code flow or FT3 sign indicating number decoder module is decoded; Memory module, IRIG-B sign indicating number temporal information and FT3 sign indicating number information that storage decodes out can read for outer CPU and check.
In technique scheme, when adaptation module judges that the type of input code flow is the FT3 code stream, further parse the speed of FT3 code stream by high-frequency clock count analysis mode, and speed and the length information of FT3 code stream offered FT3 sign indicating number decoder module.
In technique scheme, when adaptation module judges that the type of input code flow is the FT3 code stream, multiplexing control module is chosen FT3 sign indicating number decoder module, distributes input code flow for the signal input part of FT3 sign indicating number decoder module, distributes ' 0 ' data flow for IRIG-B sign indicating number decoder module signal input part.
In technique scheme, when adaptation module judges that the type of input code flow is the IRIG-B code stream, multiplexing control module is chosen IRIG-B sign indicating number decoder module, distribute input code flow for the signal input part of IRIG-B sign indicating number decoder module, distribute ' 0 ' data flow for FT3 sign indicating number decoder module signal input part.
In technique scheme, the decoder module that is assigned with ' 0 ' data flow also is set to reset mode simultaneously.
In technique scheme, described IRIG-B sign indicating number decoder module adopts the high-frequency clock that the input code flow high level is counted, if the high level in each 10ms cycle can be judged as 82 yards, corresponding code word P more than or equal to 7.4ms; If less than 7.4ms, can be judged as 55 yards more than or equal to 4.4ms, corresponding code word ' 1 '; Otherwise, can be judged as 28 yards, corresponding code word ' 0 ' scans in the code word that parses then, finds two P code positions of representative frame reference point, deposit the information position according to the IRIG-B code stream again, find out second information successively, branch information, the time information, day information is stored in the described memory module and goes.
In technique scheme, described IRIG-B sign indicating number decoder module produces pps pulse per second signal output according to code element information.
In technique scheme, described FT3 sign indicating number decoder module can be adapted to adopt the input signal of GB FT3 speed 5Mbit/s; The input signal of speed 2Mbit/s, the 4Mbit/s of employing national grid standard definition, 6Mbit/s, 8Mbit/s, 10Mbit/s; Adopt the input signal of self-defined speed 781.25Kbit/s, 1Mbit/s, 1.6Mbit/s, 3.125Mbit/s, 20Mbit/s.
In technique scheme, the high-frequency clock that described adaptation module, IRIG-B sign indicating number decoder module, FT3 sign indicating number decoder module adopt is same clock source, and frequency is 40MHz～200MHz.
In technique scheme, the frequency in described clock source is 100MHz.
The present invention has obtained following technique effect:
(1) the present invention adopts IRIG-B sign indicating number and FT3 to share an interface, can reduce light digital test equipment interface number, reduces volume, reduces power consumption.Can obtain the gps time data for other devices on the intelligent grid in addition, improve precision and the real-time of its measurement.The decoding of the necessary IRIG-B of intelligent grid and FT3 sign indicating number has been merged in the present invention, has certain versatility and multifunctionality;
(2) FT3 decoding of the present invention is suitable for GB FT3 speed 5Mbit/s; National grid standard definition speed 2Mbit/s, 4Mbit/s, 6Mbit/s, 8Mbit/s, 10Mbit/s; The self-defined speed 781.25Kbit/s of producer, 1Mbit/s, 1.6Mbit/s, 3.125Mbit/s, 20Mbit/s.This makes based on smooth digital test equipment applicability of the present invention more comprehensively with extensive;
(3) it is simple also to have a hardware configuration based on smooth digital test equipment of the present invention, the advantage that the design cycle is short.
Description of drawings
Fig. 1 is the outside drawing of hand-hold type light digital testing system;
Fig. 2 can insert signal schematic representation for the light serial ports of hand-hold type light digital testing system;
Fig. 3 is light serial ports adaptive decoding circuit structure diagram.
Mark among the figure: 210-hand-hold type shell; 220-SD clamping mouth; The 230-charging inlet; The 240-button; The 250-liquid crystal display screen; 260-luminous power test interface; 270-optical Ethernet interface; 280-light serial interface; The 100-decoding circuit; The 110-IRIG-B/FT3 input code flow; The 120-multiplexing control module; The 130-adaptation module; The 140-IRIG-B decoder module; The 150-FT3 decoder module; The 160-memory module; The 170-outer CPU.
Embodiment
Understand and enforcement the present invention for the ease of those of ordinary skills, the present invention is described in further detail below in conjunction with the drawings and the specific embodiments.
Adopt the hand-hold type light digital testing system of light serial ports adaptive de decoding circuit can use one group of light serial ports to finish the processing of FT3 message and the processing of light IRIG-B sign indicating number, to significantly reduce the interface quantity of hand-hold type light digital testing system, reduce the wiring complexity, and dwindle the volume of this handheld test equipment.The outward appearance of this hand-hold type light digital testing system preferably as shown in Figure 1, it comprises hand-hold type shell 210, SD clamping mouth 220, charging inlet 230, button 240, liquid crystal display screen 250, luminous power test interface 260, optical Ethernet interface 270, light serial interface 280, light serial interface 280 wherein can be 2 groups or more groups, satisfying the demand of different test events, and each group light serial interface 280 all can both insert the FT3 signal and inserted the IRIG-B signal.
The signal type that light serial ports 280 can insert as shown in Figure 2; adopt the demand of IEC60044-7/8 (FT3) message transmissions sampled value at the part intelligent substation; but 2 pairs of light serial ports 280 simulated intelligence transformer station merge cellses (MU) are realized the output of IEC60044-7/8 (FT3) light digital sample values SV message; transmission rate 5Mbps/10Mbps is optional; to adapt to different specification requirements; be used for test intelligent substation protection IED (Intelligent Electronic Device); observing and controlling IED and other IED; and the GOOSE switching value by feeding back in the above-mentioned IED test process of aforementioned lights Ethernet interface 270 receptions, whether checking light digital protection device and other IED be working properly.
Receive the angle of monitoring from light numeral message, 2 pairs of light serial ports 280 can be intercepted automatically and be received IEC60044-7/8 (FT3) the light digital sample values SV message that merge cells (MU) sends, and in the man-machine interface of liquid crystal display screen 250 the explicit message true form, resolve content, the monitoring of realization message, and carry out frame losing statistics and message time analysis of Uniformity, the voltage that transmits for the light numeral message that receives, electric current, information such as time-delay show in man-machine interface, to voltage, current information, adopt the known effective value of power industry, waveform, phasor, modes such as order amount show in man-machine interface, and can further show voltage, current channel is humorous to be involved single-phase or three phase power.
The two pairs of light serial ports 280 can also multiplexing reception light IRIG-B sign indicating number, to tester to the time and in man-machine interface display light IRIG-B sign indicating number information, be used for the test of intelligent substation clock synchronization system.
For the FT3 sign indicating number of realizing above-mentioned smooth serial ports and the multiplexing function of IRIG-B sign indicating number, the invention provides a kind of smooth serial ports self adaptation IRIG-B and FT3 sign indicating number decoding circuit, its structure as shown in Figure 3, decoding circuit 100 comprises self adaptation (ADAPT) module 120, multiplexing control (MUX_CTRL) module 130, IRIG-B sign indicating number decoder module 140, FT3 sign indicating number decoder module 150, storage (RAM) module 160.The light digital signal that the light serial ports will be imported transfers electric digital signal to, it is IRIG-B/FT3 input code flow 110, and the IRIG-B/FT3 input code flow is input in the decoding circuit 100 self adaptation in the decoding circuit 100 (ADAPT) module 120, this IRIG-B/FT3 input code flow 110 of multiplexing control (MUX_CTRL) module 130 parallel receives.
At first, self adaptation (ADAPT) module is resolved scheme by the high-frequency clock count, judges tentatively whether input code flow is 10 millisecond period code words, if this input code flow is the IRIG-B code word so; Otherwise be the FT3 code word.If the FT3 code word needs further to resolve, according to the code word hop period, judge FT3 code word speed.The speed of obtaining is passed to FT3 sign indicating number decoder module, allow it carry out the decode operation of respective rate.
Particularly, according to IRIG-B coding techniques standard, each bit of IRIG-B signal is fixed as 10ms, per second sends 1 frame data, namely 100 bits wherein continue 2ms with first high level, and the bit that back low level continues 8ms is defined as " 0 ", elder generation's high level continues 5ms, the bit that back low level continues 5ms is defined as " 1 ", and first high level continues 8ms, and the bit that back low level continues 2ms is defined as " P ", therefore in theory by the clock signal of 1kHz, can realize the parsing of IRIG-B code stream.The stream rate of FT3 signal is then much higher, it is minimum to be 781.25Kbit/s, be up to 20Mbit/s, therefore by a high frequency clock more than the 20MHz IRIG-B/FT3 input code flow is counted, can tell the signal type of input code flow, when (100K clock cycle in) input signal in 10ms only saltus step once be the IRIG-B input signal, otherwise be the FT3 input signal.Based on same principle, when the clock that adopts higher frequency is counted input signal, then not only can distinguish the type of IRIG-B input signal and FT3 input signal, can also judge the stream rate of FT3 input signal simultaneously.Cause distortion because code stream can be introduced noise in extraneous transmission course, when code stream being carried out electrical level judging here, preferably take to carry out greater than the clock of transmission code stream frequency more than 5 times, can eliminate and incorporate The noise.So adopt the high frequency clock of 100MHz here.
The code stream attribute that multiplexing control (MUX_CTRL) module goes out according to self adaptation (ADAPT) module parses, distribute input code flow or ' 0 ' data flow for respectively the signal input part of IRIG-B sign indicating number decoder module and FT3 sign indicating number decoder module, distribute effective global reset signal or ' 1 ' for the Enable Pin of IRIG-B sign indicating number decoder module and FT3 sign indicating number decoder module.Be assigned input code flow and overall effective reset signal with the decoder module of input code flow type matching, in running order; And the unmatched module assignment of type is ' 0 ' data flow and ' 1 ' reset values, is in reset mode, and not work has reduced power consumption.
If multiplexing control (MUX_CTRL) module has been chosen IRIG-B sign indicating number decoder module, this IRIG-B sign indicating number decoder module brings into operation.The high level in each 10ms cycle adopt the high-frequency clock to code stream high level counting, if can be judged as 82 yards, corresponding code word P greater than 7.4ms; If greater than 4.4ms, can be judged as 55 yards, corresponding code word ' 1 '; Otherwise, can be judged as 28 yards, corresponding code word ' 0 '.In the code word that parses, scan then, find two P sign indicating numbers, representative frame reference point, the beginning of a frame; Then deposit the information position according to the IRIG-B code stream, choose second information successively, branch information, the time information, day information etc. is stored in the memory module one by one and goes.
The IRIG-B decoder module can also parse pps pulse per second signal PPS except parsing temporal information, for the synchronous usefulness of device in the intelligent grid.In addition, it also can produce IRIG-B locking (irigb_locked) signal, and when detecting the frame reference point, this signal is effectively high, and expression IRIG-B code stream is effective; When arriving invalid IRIG-B code stream by the house dog count detection, this signal is for low invalid, and expression IRIG-B code stream is invalid.This signal can be made the usefulness of caution.
If FT3 sign indicating number decoder module has been chosen in multiplexing control (MUX_CTRL), this FT3 sign indicating number decoder module brings into operation.Self adaptation (ADAPT) module can pass to the stream rate attribute that parsing is obtained FT3 sign indicating number decoder module, if this code check attribute is 0001, expression input FT3 stream rate is 1Mbit/s; If be 0010, expression input FT3 stream rate is 2Mbit/s; If be 0011, expression input FT3 stream rate is 5Mbit/s; If be 0100, expression input FT3 code stream is 4Mbit/s; If be 0101, expression input FT3 code stream is 10Mbit/s; If be 0110, expression input FT3 code stream is 8Mbit/s; If be 0111, expression input FT3 code stream is 20Mbit/s; If be 1000, expression input FT3 code stream is 6Mbit/s; If be 1001, expression input FT3 code stream is 781.25Kbit/s; If be 1010, expression input FT3 code stream is 3.125Mbit/s; If be 1011, expression input FT3 code stream is 1.6Mbit/s.FT3 sign indicating number decoder module can carry out corresponding decode operation according to the stream rate attribute.
FT3 sign indicating number decoder module equally also is to adopt the high-frequency clock that the code stream high level is carried out analysis of accounts in running.Because FT3 code streams by using Manchester's code, input code flow is not rule so, resolve the comparison difficulty, here adopted the recodification scheme, the certain rule that possesses according to input code flow, the regular code word of encoding out is come out, and then new code word is resolved the complexity before oversimplifying like this.During new code stream resolved, scan-data packet header 0564 in case find packet header, was saved in the data that next parse in the memory module successively.
The recodification thought that FT3 sign indicating number decoder module adopts is to count the code word duty ratio of input signal with bit rate clock, one group of high-low level is analyzed as the code word of centre, then code word height duty ratio have 2: 2,2: 1,1: 2 and 1: 1 four kinds of form, correspond to the sequence of 101 yards, 100 yards, 01 yard and 11 or 00 yards respectively; The code word of determining with reference to this code word front, centre judges that this can be judged to 01 yard, 00 yard, 1 yard identical code value with reference code respectively again, and so just decoding has obtained the code word of input signal correspondence.
FT3 sign indicating number decoder module is the FT3 signal bit stream of the multiple speed of self adaptation, and therefore bag length also may be often to change.Self adaptation (ADAPT) module also can be transmitted the corresponding length attribute of code stream simultaneously and give FT3 sign indicating number decoder module when transmitting stream rate, allows it decode complete bag data and comes out.
Light numerical protection IED, failure wave-recording IED, observing and controlling IED and other IED device that the present invention can be on the intelligent grid provide the gps time data, improve precision and the real-time measured.The utility model realizes based on fpga chip, so have autgmentability and the computing real-time is good, simple in structure, low in energy consumption and the construction cycle is short, development cost is low advantage.
Claims (10)
1. light serial ports adaptive de decoding circuit, the type that can judge input code flow automatically still is the FT3 code stream for the IRIG-B code stream, and decode according to the input code flow type adaptively, it is characterized in that: comprise adaptation module, multiplexing control module, IRIG-B sign indicating number decoder module, FT3 sign indicating number decoder module and memory module; Described adaptation module judges that by high-frequency clock count analysis mode the type of input code flow still is the FT3 code stream for the IRIG-B code stream; The type of the input code flow that described multiplexing control module provides according to adaptation module is distributed to corresponding IRIG-B sign indicating number decoder module with input code flow or FT3 sign indicating number decoder module is decoded; Described memory module, IRIG-B sign indicating number temporal information and FT3 sign indicating number information that storage decodes out supply outer CPU to read and check.
2. smooth serial ports adaptive de decoding circuit according to claim 1, it is characterized in that: when adaptation module judges that the type of input code flow is the FT3 code stream, further parse the speed of FT3 code stream by high-frequency clock count analysis mode, and speed and the length information of FT3 code stream offered FT3 sign indicating number decoder module.
3. smooth serial ports adaptive de decoding circuit according to claim 1, it is characterized in that: when adaptation module judges that the type of input code flow is the FT3 code stream, multiplexing control module is chosen FT3 sign indicating number decoder module, distribute input code flow for the signal input part of FT3 sign indicating number decoder module, distribute ' 0 ' data flow for IRIG-B sign indicating number decoder module signal input part.
4. smooth serial ports adaptive de decoding circuit according to claim 1, it is characterized in that: when adaptation module judges that the type of input code flow is the IRIG-B code stream, multiplexing control module is chosen IRIG-B sign indicating number decoder module, distribute input code flow for the signal input part of IRIG-B sign indicating number decoder module, distribute ' 0 ' data flow for FT3 sign indicating number decoder module signal input part.
5. according to claim 3 or 4 described smooth serial ports adaptive de decoding circuits, it is characterized in that: the decoder module that is assigned with ' 0 ' data flow also is set to reset mode simultaneously.
6. smooth serial ports adaptive de decoding circuit according to claim 1, it is characterized in that: described IRIG-B sign indicating number decoder module adopts the high-frequency clock that the input code flow high level is counted, if the high level in each 10ms cycle can be judged as 82 yards, corresponding code word P more than or equal to 7.4ms; If less than 7.4ms, can be judged as 55 yards more than or equal to 4.4ms, corresponding code word ' 1 '; Otherwise, can be judged as 28 yards, corresponding code word ' 0 ' scans in the code word that parses then, finds two P code positions of representative frame reference point, deposit the information position according to the IRIG-B code stream again, find out second information successively, branch information, the time information, day information is stored in the described memory module and goes.
7. smooth serial ports adaptive de decoding circuit according to claim 6 is characterized in that: described IRIG-B sign indicating number decoder module produces pps pulse per second signal output according to code element information.
8. according to each described smooth serial ports adaptive de decoding circuit among the claim 1-7, it is characterized in that: described FT3 sign indicating number decoder module can be adapted to adopt the input signal of GB FT3 speed 5Mbit/s; The input signal of speed 2Mbit/s, the 4Mbit/s of employing national grid standard definition, 6Mbit/s, 8Mbit/s, 10Mbit/s; Adopt the input signal of self-defined speed 781.25Kbit/s, 1Mbit/s, 1.6Mbit/s, 3.125Mbit/s, 20Mbit/s.
9. according to each described smooth serial ports adaptive de decoding circuit among the claim 1-7, it is characterized in that: the high-frequency clock that described adaptation module, IRIG-B sign indicating number decoder module, FT3 sign indicating number decoder module adopt is same clock source, and frequency is 40MHz～200MHz.
10. smooth serial ports adaptive de decoding circuit according to claim 9, it is characterized in that: the frequency in described clock source is 100MHz.
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| CN114006620A (en) * | 2021-10-27 | 2022-02-01 | 北斗天汇（北京）科技有限公司 | IRIG alternating-current B code decoding method and system with automatic adjustment function |
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