CN104751875B - Fail bit figure analysis method applied to NVM chips - Google Patents
Fail bit figure analysis method applied to NVM chips Download PDFInfo
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- CN104751875B CN104751875B CN201310726710.8A CN201310726710A CN104751875B CN 104751875 B CN104751875 B CN 104751875B CN 201310726710 A CN201310726710 A CN 201310726710A CN 104751875 B CN104751875 B CN 104751875B
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Abstract
The invention discloses a kind of fail bit figure analysis method applied to NVM chips, this method inputs HV signals from chip exterior by the tester with bitmap analysis function, the erasing of test chip, programming, read functions, analyzed with bitmap analysis method, in memory cell array, row or column near defect shows as read error in bitmap, row or column away from defect shows as reading correct, according to bitmap to reflect defect characteristic information analysis failure mechanism and positioning invalid position in bitmap.The present invention is by improving conventional fail bit figure analysis method, HV signals are produced by chip internal Pump circuit modules and are changed to be inputted by chip exterior tester, so as in the case of the whole memory cell Read failures of NVM storage arrays, the message bit pattern with defect characteristic of chip failing is obtained, the limitation of conventional bitmap analysis method is not only breached, and substantially increases the validity and the scope of application of bitmap analysis positioning.
Description
Technical field
The present invention relates to the failure analysis in IC manufacturing field, more particularly to IC chip, more specifically
Say, be memory caused by being related to the HV voltage signals used in being acted because of NVM memory cell arrays Erase or Program extremely
The failure analysis of array whole storage-unit-failure.
Background technology
NVM（Non-Volatile Memory, non-volatility memorizer）The common technology means of chip failure analysis are to make
With failure bitmap location（Bitmap）, this method is that the fail address of memory chip memory cell is obtained using tester, is built
Vertical physical address bitmap mapping, so as to position the physical location of failure on chip failing, then carries out corresponding failure mechanism
Analysis and physics of failure analysis.
The method is applied to can to test the analysis for obtaining memory cell feature failure address by conventional func, but
Under certain situation, defect may cause the key signal current potential in memory cell array overall abnormal so that NVM chips are entered
During row test, Read（Read）Result be that all memory cells in whole memory cell array fail, thus without
Method obtains the validity feature address information related to failures position, i.e., can not obtain effective failure message bit pattern, then
Just Analysis on Mechanism and physical positioning further can not be carried out to defective locations.
By the way that to causing the reason for all memory cell Read fail in NVM chips to analyze, failure cause can be divided
For two kinds of main Types, a kind of is to lack the peripheral circuit region being trapped in outside memory cell array to cause circuit function failure,
Another is to lack to be trapped in memory cell array region, causes the HV of memory cell array（Erase/Program high voltages）
Signal network potential anomalies, so as to cause the Erase (erasing) or Program of all memory cell（Programming）Disabler.It is right
In both failure types, the effective message bit pattern for being available for analyzing can not be formed using conventionally test bitmap analysis method, because
This can not make further Analysis of Failure Mechanism and defect location analysis using bitmap analysis method to it.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of fail bit figure analysis method applied to NVM chips, it can
To improve the validity and the scope of application of bitmap analysis positioning.
In order to solve the above technical problems, the fail bit figure analysis method applied to NVM chips of the present invention, this method is from core
HV signals, the erasing of test chip, programming, read functions, with position are inputted by the tester with bitmap analysis function outside piece
Figure analysis method is analyzed, in memory cell array, and the row or column near defect shows as read error in bitmap, remote
The row or column of defect shows as reading correct, the defect characteristic information analysis failure mechanism that reflects according to bitmap and fixed in bitmap
Position invalid position.
The present invention is produced HV signals by chip internal Pump circuit modules by improving conventional fail bit figure analysis method
Life is changed to be inputted by chip exterior tester, so as in the case of the whole memory cell Read failures of NVM storage arrays, obtain
The message bit pattern with defect characteristic of chip failing, solves conventional bitmap analysis method and faces what is be led to by manufacturing defect
NVM memory cell arrays whole element failures and the problem of can not obtain with feature failure message bit pattern, and substantially increase
The validity and the scope of application of bitmap analysis positioning.
Brief description of the drawings
Fig. 1 is chip design diagram.
Fig. 2 is whole memory cell Read failures bitmaps.
Fig. 3 is whole normal bitmaps of memory cell Read.
Fig. 4 is four kinds of common failure feature bitmaps.
Embodiment
Have for technology contents, feature and effect to the present invention and more specifically understand, in conjunction with accompanying drawing, details are as follows：
Latter event for causing all memory cell Read failure in NVM chips, by NVM circuitry principle and
The analysis of considered repealed case, find Erase/Program action used in HV voltages be NVM chip-storeds cellular zone most
Easily by defective effect key signal, when manufacturing process lack be trapped in memory cell areas when, can frequently result in HV voltage signals with
Occur short circuit between other electric potential signals and produce leakage current.Simultaneously as HV signals are generally by internal Pump（Boosting）Circuit mould
Block is produced, and its current driving ability is smaller, when the leakage current value that short circuit is caused is more than its driving force, will drag down Pump electricity
The output voltage amplitude of road module so that the voltage on the HV signal network lines in the whole memory cell region for sharing its output
Amplitude can not meet memory cell and carry out the required magnitude of voltage of Erase/Program operations, so as to cause all storages in chip
The Erase/Program failures of unit, and then Read failures are shown as, just can not be obtained using conventional bitmap analysis method can be anti-
Reflect the message bit pattern of defect characteristic.But, if we can input a HV signal from chip exterior by tester replaces core
Pump HV signals inside piece, because the driving force of the HV signals of tester offer is better than chip internal leakage current, it applies
The total physical efficiency of current potential on HV signal networks keeps it to input amplitude.But because via resistance is deposited on HV signal paths in chip
Short-circuit leakage current forms voltage on HV paths, so that closer to defect location of short circuit, its current potential is lower, may make
The HV signal amplitudes obtained close to defective locations can not still meet the successful requirement of Erase/Program operations.In this case
Go the Erase/Program/Read functions of test chip and analyzed using bitmap analysis method, then can be showed in bitmap
For the row or column Read mistakes near defect in memory cell array, then Read is correct for the row/column away from defect point.By this
Method, we just result in the message bit pattern with defect characteristic.
Based on above-mentioned principle, the present invention proposes a kind of improved bitmap analysis method, comprises the following steps：
Step 1, in chip design stage, memory cell Erase/Program is acted to the HV signals used and passes through connection
Path is drawn out to chip HV test pins, as shown in Figure 1.
Step 2, Erase, Program and Read operation are carried out to chip failing by tester, determines that chip functions are different
Often action is Erase or Program operations.Meanwhile, object chip failure situation satisfaction is failed originally using following operation acknowledgement
Two applicability features of method：
1）Bitmap test analysis is carried out in Read operations, confirms that chip has memory cell all failures, it is impossible to present
The feature of feature failure bitmap, as shown in Figure 2.
2）HV signal voltage amplitude measurements in dysfunction action process are come out, confirm that HV signals have voltage magnitude
Relatively low abnormal feature.
Step 3, data storage background setting is carried out to chip failing using usual manner, if that is, abnormal operation object is moved
When work is Erase, then routine Program is carried out to chip and operated, it is right if abnormal operation object action is Program
Chip carries out routine Erase operations.
Step 4, after data background is provided with, one is applied to the HV signal testings pin of chip failing by tester
HV magnitudes of voltage corresponding with design specification, carry out the test operation of the dysfunction action, i.e., to chip on this condition
Erase or Program, then carries out Read operations to chip and obtains message bit pattern using bitmap method of testing.
Step 5, if the bitmap obtained in step 4 still can not expression characteristicses failure message bit pattern, need adjustment walk
Additional HV magnitudes of voltage described in rapid 4, and step 3 and the test process described in step 4 are re-started, until the message bit pattern obtained
Defect speciality failure characteristics can be presented（Such as Fig. 4）.
Changing the specific method of additional HV voltages is：When previous bitmap is rendered as whole storage-unit-failures（Such as Fig. 2）,
Then increase additional HV magnitudes of voltage on the basis of previous HV voltages；When previous bitmap be rendered as whole memory cell it is normal when（As schemed
3）, then additional HV magnitudes of voltage are reduced on the basis of previous HV voltages.
Step 6, according to the message bit pattern with defect characteristic of acquisition（Such as Fig. 4）, carry out further failure mechanism point
Analysis and failure positioning.
The embedded flash memory chip failure of embodiment 1 is analyzed
The present invention illustrated below is in an embedded Flash（Flash memory）The practical application of chip product failure analysis.
Flash storage in chip can use two HV high voltage signals in Erase/Program operations, and one is
Positive HV signals, we term it VPOS, another is negative HV signals, and we term it VNEG.Above-mentioned two HV signals are all
Belong to chip internal signal, in actual applications and need not be drawn out to external terminal, but in order to realize measurability and should
Test analysis is carried out with bitmap analysis method of the present invention, we will pass through connecting path and are connected in chip design stage
Chip exterior test pin is connected to, external testing pin is respectively designated as passing through controlling switch on VPOS and VNEG, connecting path
Control the break-make of connecting path.
Low yield issues occur in the fabrication process for the chip product, and failure testing project is relevant with the Flash in chip,
Need to analyze its failure cause.Chip failing is analyzed using the bitmap analysis method of the present invention, step includes：
The first step, Erase operations are first carried out using the tester with bitmap analysis function to the FLASH in failure sample
（VPOS and VNEG not applied voltage）, data Read then is carried out to chip and conventional bitmap analysis is carried out, as a result shown
Read data after Erase are normal, illustrate that Erase operations are abnormal without occurring.Then, Program tests are carried out to FLASH to grasp
Make（VPOS and VNEG not applied voltage）, data Read then is carried out to it and conventional bitmap analysis is carried out, as a result finds to deposit
All memory cell of memory array fail, and it is the abnormal operation object of chip failure to illustrate Program operations.Further,
The test access for opening VPOS and VNEG by tester control chip is switched, by the VPOS in Program test operating procedures
And VNEG magnitudes of voltage are measured, it is found that VPOS magnitudes of voltage in Program operating process are lower than design specification value Vspec, category
In abnormal ranges, and VNEG magnitudes of voltage are in normal range (NR).So as to confirm that the failure characteristics of the chip failing meet the present invention
Two applicability features, while confirm chip failing abnormal operation occur in Program operations.
Second step, Erase test operations are carried out to chip failing, and the data background for making its NVM memory is shape after Erase
State.
3rd step, the test access for opening VPOS by tester control chip is switched, while being applied to VPOS test pins
Plus Vspec voltage, Program operations are carried out on this condition, and Read is then carried out to chip and is tested using bitmap to obtain
Bitmap data after Program operations, it is found that all memory cell Read data of storage array are normal, illustrate additional
VPOS voltages make fault location current potential reach the requirement that the normal Program of satisfaction is operated.
4th step, for exposure defect characteristic, is operated after resetting memory array background, appropriate reduction to chip Erase
VPOS applied voltage value, on this condition, Program operations is carried out to chip, is then carried out Read operations to chip and is obtained
The bitmap data of memory array is obtained, as a result finds that bitmap shows ranks and intersects failure characteristics, that is, obtains and lost with defect
Imitate effective message bit pattern of feature.It should be noted, if need to be changed the trial of VPOS voltages, made with chip failing defect
Into electric leakage degree it is related, this step is optional step.Obtain after effective message bit pattern, then failure can be had according to acquisition
The message bit pattern of feature carries out Analysis of Failure Mechanism and positioning.
By the method for the invention, it can be obtained in the case of the whole memory cell Read failures of NVM storage arrays
The message bit pattern with defect characteristic of chip failing, breaches the limitation of conventional bitmap analysis method, substantially increases bitmap
The validity and the scope of application of analyzing and positioning.According to we certain NVM memory chip product failure analysis practical experience,
Using in the case of bitmap analysis, the growing number that can obtain validity feature message bit pattern using conventional bitmap analysis method is accounted for
40% or so, it is necessary to account for 60% or so using the growing number for inventing proposed bitmap analysis method.Conventional bit map method has
Effect property, dependent on chip circuit design, laying out pattern relative to defective workmanship type sensitiveness.With integrated circuit minimum line
HV voltage networks are such to the sensitiveness more and more higher of manufacturing defect in wide diminution and the application of low power dissipation design, NVM chips
The ratio failed in all failures of NVM chips also more and more higher, therefore the validity of conventional bitmap analysis method will increasingly
It is low, and improved bitmap analysis method proposed by the present invention is possible to greatly improve the success rate of NVM chip product failure analyses
And the scope of application.
Claims (4)
1. the fail bit figure analysis method applied to NVM chips, it is characterised in that from chip exterior by with bitmap analysis function
Tester input erasing-programming high voltage signal, the erasing of test chip, programming, read functions, with the bitmap after improvement point
Analysis method is analyzed, in memory cell array, and the row or column memory cell near defected memory cell is shown as in bitmap
Read error, the row or column memory cell away from defected memory cell shows as reading correctly in bitmap, is reflected according to bitmap
Defect characteristic information analysis failure mechanism and positioning invalid position；Bitmap analysis method after the improvement, including following step
Suddenly：
1) in chip design stage, the erasing-programming high voltage signal that memory cell is wiped and programming action is used is passed through even
Connect road and be drawn out to chip erasing-programming high voltage signal test pin；
2) chip failing is wiped by tester, programmed and read operation, it is erasing to determine chip functions abnormal operation
Or programming operation；
3) the data storage background of chip failing is set：If chip functions abnormal operation is erasing operation, chip is carried out
Programming operation, if chip functions abnormal operation is programming operation, erasing operation is carried out to chip；
4) applied by tester to the erasing-programming high voltage signal test pin of the dysfunction action object of chip failing
One erasing-programming high-voltage value corresponding with design specification, carries out step 2 to chip on this condition) dysfunction
The test operation of action, is then read to chip, and obtains having with failure characteristics using bitmap method of testing
Imitate message bit pattern；
5) Analysis of Failure Mechanism and failure positioning analysis are carried out according to the message bit pattern of acquisition.
2. further comprise the steps according to the method described in claim 1, it is characterised in that step 2)：
21) bitmap test analysis is carried out in read operation, confirms whether chip there is memory cell all to fail, can not present
The feature of feature failure bitmap；
22) the erasing-programming high voltage signal voltage magnitude in measurement dysfunction action process, confirms the high electricity of erasing-programming
Signal is pressed to whether there is the relatively low abnormal feature of voltage magnitude.
3. according to the method described in claim 1, it is characterised in that step 4) and step 5) between, it is further comprising the steps of：Adjust
Erasing-programming high-voltage value described in whole step 4), and carry out step 3) and step 4) described in test process, until obtaining energy
The message bit pattern of defect speciality failure characteristics is enough presented.
4. method according to claim 3, it is characterised in that the method for adjustment of the erasing-programming high-voltage value is：When
When previous bitmap is rendered as whole storage-unit-failures, then increase erasing-programming on the basis of previous erasing-programming high voltage high
Magnitude of voltage；When previous bitmap be rendered as whole memory cell it is normal when, then on the basis of previous erasing-programming high voltage reduce wipe
Except/programming high-voltage value.
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| CN201310726710.8A CN104751875B (en) | 2013-12-25 | 2013-12-25 | Fail bit figure analysis method applied to NVM chips |
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| CN104751875B true CN104751875B (en) | 2017-10-24 |
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| CN107610738A (en) * | 2017-09-29 | 2018-01-19 | 北京中电华大电子设计有限责任公司 | A kind of efficient out of memory analysis method |
| CN109283451B (en) * | 2018-09-18 | 2020-12-29 | 电子科技大学 | Integrated circuit good product detection system and method |
| TWI701429B (en) * | 2019-09-12 | 2020-08-11 | 力晶積成電子製造股份有限公司 | Defect analysis method and memory chip |
| CN113823349A (en) * | 2021-08-30 | 2021-12-21 | 全芯智造技术有限公司 | Chip failure mode determination method and terminal |
| CN114758693B (en) * | 2022-05-12 | 2023-11-10 | 西安紫光国芯半导体有限公司 | Positioning method and positioning device for invalid word line of memory array |
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