CN112098720B - Device and method for testing clock precision and drift by utilizing satellite timekeeping - Google Patents
Device and method for testing clock precision and drift by utilizing satellite timekeeping Download PDFInfo
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Abstract
The invention provides a testing device and a method for realizing clock precision and drift by using satellite timekeeping, belonging to the technical field of data communication and comprising a satellite receiver, a FPGA and a clock controller, wherein the satellite receiver is used for sending time information to the FPGA; the FPGA is used for accessing a clock to be tested, receiving a master control command and analyzing a test time node and a test time length according to time information sent by the satellite receiver; the master control CPU is used for sending test duration to the FPGA and calculating to obtain theoretical frequency of a clock rising edge and test frequency of the clock rising edge; and the clock module to be tested is used for comparing the theoretical frequency of the clock rising edge with the test frequency of the clock rising edge to obtain the precision of the clock to be tested, calculating an aging curve according to the sampled unit time node of the clock to be tested and the precision of the clock to be tested for a plurality of times, and obtaining the test states of the clock precision and the drift according to the aging curve. The invention solves the problem of clock frequency test precision.
Description
Technical Field
The invention belongs to the technical field of data communication, and particularly relates to a device and a method for testing clock precision and drift by utilizing satellite timekeeping.
Background
In the field of data communication, a clock is an indispensable ring, and at present, many technologies have high requirements on the precision and aging of the clock, and the testing of the clock Zhong Jingdu and the drift is also the following technical requirement, and there are two common frequency measurement methods: frequency measurement and periodic measurement. In the frequency measurement method, the number of pulses N of a signal to be measured is counted in time t, and the number of pulses per unit time is obtained, i.e., the frequency of the signal to be measured. The periodic measurement method is to measure the period T of the signal to be measured and then find the frequency of the signal to be measured from the frequency f = 1/T. Both of the above methods, however, produce errors of ± 1 measured pulse.
Disclosure of Invention
Aiming at the defects in the prior art, the device and the method for testing the clock frequency by using the satellite time keeping to realize the clock precision and the drift solve the problem of testing the clock frequency.
In order to achieve the above purpose, the invention adopts the technical scheme that:
the scheme provides a testing device for realizing clock precision and drift by utilizing satellite timekeeping, which comprises an FPGA, and a satellite receiver, a master control CPU and a clock module to be tested which are respectively connected with the FPGA;
the satellite receiver is used for sending time information to the FPGA;
the FPGA is used for accessing a clock to be tested, receiving a master control command, and analyzing a test time node and a test time length according to time information sent by the satellite receiver;
the master control CPU is used for sending test duration to the FPGA and respectively calculating theoretical frequency of a clock rising edge and test frequency of the clock rising edge by using the test time node and the test time length;
the clock module to be tested is used for comparing the theoretical frequency of the clock rising edge with the testing frequency of the clock rising edge to obtain the precision of the clock to be tested, calculating the precision of the clock to be tested according to the sampled unit time node of the clock to be tested and a plurality of times of the clock to be tested to obtain an aging curve, and obtaining the testing states of the clock precision and the drift according to the aging curve.
The beneficial effects of the invention are: the invention solves the problem of testing the clock frequency precision, and the testing precision can reach ns level; the experimental testing steps are more flexible, the testing time node can be freely configured by the master control, and can be set to any time point, such as xx minutes xx seconds when xx, the testing time length can be freely configured by the master control, and can be set to any time length; according to the satellite time service system, very accurate time information can be received, which is beneficial to accurately mastering the time span of the test; the working clock of the FPGA is accurate, which is beneficial to improving the precision of clock frequency test; meanwhile, the whole experimental framework can also be applied to other projects, such as time-keeping measurement and other experiments.
Preferably, the clock testing device further comprises a peripheral and an LED which are respectively connected with the FPGA, and the peripheral and the LED are both used for displaying the clock precision and the testing state of the drift.
The beneficial effects of the further scheme are as follows: the invention can display the experimental state visually through the peripheral and the LED, and indicate the connection state of the satellite time service through the LED, if the satellite receiving module is effectively connected with the satellite, the experimental data and the experimental results such as the tested clock precision, the tested drift curve and the like can also be output visually through the LED.
Based on the device, the invention also discloses a method for testing clock precision and drift by using satellite timekeeping, which comprises the following steps:
s1, receiving time information sent by a satellite, sending the time information to an FPGA (field programmable gate array), and analyzing the time information and 1pps timekeeping information through the FPGA;
s2, accessing a clock to be tested, receiving a command of a main control CPU, and analyzing a test time node and a test time length according to the time information;
s3, counting the working clock of the FPGA between the rising edge of each 1pps of timekeeping information and the rising edge of the clock to be tested, recording the frequency of the working clock of the FPGA as P0, and recording the working clock count value CNT of the test start time node and the working clock count value CNT' of the test end time node;
s4, sampling and counting rising edges of the clock to be tested between the test starting time node and the test ending time node, and recording the rising edges as DATA;
s5, calculating to obtain the theoretical frequency of the clock rising edge according to the test time node and the theoretical values of the number of the rising edges of the clock to be tested within the test time;
s6, calculating according to the frequency P0 of the working clock of the FPGA, the sampling number of the rising edge of the clock to be tested, the test time node, the working clock counting value CNT of the test starting time node and the working clock counting value CNT' of the test ending time node to obtain the test frequency of the rising edge of the clock;
s7, comparing the theoretical frequency of the clock rising edge with the testing frequency of the clock rising edge to obtain the precision of the clock to be tested;
s8, sampling a unit time node of a clock to be tested;
and S9, calculating according to the unit time node of the sampled clock to be tested and the precision of the clock to be tested for a plurality of times to obtain an aging curve, and obtaining the test state of the clock precision and the drift according to the aging curve.
The beneficial effects of the invention are: the invention solves the problem of testing the clock frequency precision, and the testing precision can reach ns level; the experimental testing steps are more flexible, the testing time node can be freely configured by the master control, and can be set to any time point, such as xx minutes xx seconds when xx, the testing time length can be freely configured by the master control, and can be set to any time length; according to the satellite time service system, very accurate time information can be received, which is beneficial to accurately mastering the time span of the test; the working clock of the FPGA is accurate, which is beneficial to improving the precision of clock frequency test; meanwhile, the whole experimental framework can also be applied to other projects, such as time-keeping measurement and other experiments.
Further, the expression of the theoretical frequency of the clock rising edge in step S5 is as follows:
wherein, P represents the theoretical frequency of the clock rising edge, C represents the theoretical value of the number of the rising edges of the clock to be tested in the test duration, T represents the test starting time node, and T' represents the test ending time node.
Still further, the expression of the test frequency of the clock rising edge in step S6 is as follows:
C'＝DATA
wherein, P ' represents the clock rising edge test frequency, T represents the test start time node, T ' represents the test end time node, CNT represents the working clock count value of the test start time node, CNT ' represents the count value of the test end time node, and P0 represents the working frequency of the FPGA.
The beneficial effects of the further scheme are as follows: according to the sampling counting of the working clock of the FPGA, the sampling errors of the clock to be tested at the start time and the end time of the experiment are effectively weakened, and the clock is very accurate because the working clock of the FPGA is calibrated through internal phase locking.
Still further, the expression of the aging curve in step S9 is as follows:
S＝P' 1 ,P' 2 ,...,P' n
C' n ＝DATA n
wherein S represents an aging curve, P' n Test frequency, C 'representing the number of n-th rising edges' n The number of rising edges of the nth clock to be tested is shown as an experimental value, P0 represents the working frequency of the FPGA, and CNT n Denotes an operation clock count value, CNT ', of an nth test start time node' n And a count value indicating an nth test end time node.
The beneficial effects of the further scheme are as follows: a plurality of experimental data can be obtained through the design, and then a curve of the frequency and the time of the clock to be tested, namely an aging curve, can be obtained according to the time node and the obtained experimental result.
Drawings
FIG. 1 is a schematic view of the present invention.
FIG. 2 is a flow chart of the method of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Example 1
As shown in fig. 1, the present invention provides a testing apparatus for realizing clock precision and drift by using satellite timekeeping, including an FPGA, and a satellite receiver, a main control CPU and a clock module to be tested, which are respectively connected to the FPGA; the satellite receiver is used for sending time information to the FPGA; the FPGA is used for accessing a clock to be tested, receiving a master control command and analyzing a test time node and a test time length according to time information sent by the satellite receiver; the master control CPU is used for sending the test duration to the FPGA and respectively calculating the theoretical frequency of the clock rising edge and the test frequency of the clock rising edge by using the test time node and the test time length; and the clock module to be tested is used for comparing the theoretical frequency of the clock rising edge with the test frequency of the clock rising edge to obtain the precision of the clock to be tested, calculating an aging curve according to the sampled unit time node of the clock to be tested and the precision of the clock to be tested for a plurality of times, and obtaining the test states of the clock precision and the drift according to the aging curve. Preferably, the clock testing device comprises a peripheral and an LED which are respectively connected with the FPGA, and the peripheral and the LED are both used for displaying the clock precision and the testing state of drift.
In this embodiment, the FPGA mainly performs functions of implementing sampling test and system management in the whole system, and provides a platform basis for the test. As shown in fig. 1, the FPGA uses a high-precision and high-frequency clock source as a working clock of the FPGA, the power supply set on the board is controlled to be powered up and down, the chips on the board are reset, the access of the master control cpu is supported, the satellite receiving device is accessed, and the clock device to be tested is accessed and sampled. The peripheral and the LED can visually display the test state.
In this embodiment, the satellite receiver receives a satellite signal through an antenna, the satellite signal carries time information, the satellite receiver analyzes the signal and then sends the time information to the FPGA through the NMEA0183 protocol, and meanwhile, the satellite receiver also sends a 1PPS standard second flag signal to the FPGA. The FPGA can analyze calendar time information such as year, month, day, time, minute, second and the like from the NMEA0183 protocol received from the satellite receiver module, and takes the rising edge of the 1PPS signal as a quasi-second mark.
In this embodiment, after the FPGA normally receives the time information sent by the satellite receiver, the system starts to operate, the main controller issues a command to an internal register of the FPGA through a bus, and a test start time node may be selected as a certain minute and a certain second (international standard time) at a certain time in a certain day in a certain month and a certain month in a certain year, and is written as T. The test duration is controlled by controlling the test ending time node, and the test ending time node can also be selected to be a certain minute and a certain second (international standard time) at a certain time and a certain day in a certain month and a certain month in a certain year and is recorded as T'.
In this embodiment, the FPGA counts the operating clock (frequency is denoted as P0, unit Hz) of the FPGA between the rising edge of each 1PPS signal and the rising edge of the clock to be tested, and records the first value after the test start time node as CNT and the first value before the test end time node as CNT', which are data for avoiding that the rising edge of the clock to be tested is not sampled or the rising edge of the clock to be tested is multi-sampled at the test time node. The FPGA counts the rising edge samples of the clock to be tested (frequency is denoted as P, unit Hz) between the test start time node and the test end time node, and is denoted as DATA.
In this embodiment, the theoretical value of the number of rising edges of the clock to be tested in the test duration is denoted as C, the theoretical frequency is denoted as P, the unit Hz, T represents the test start time node, T' represents the test end time node, and the unit s is:
the experimental value of the number of rising edges of the clock to be tested in the test time is recorded as C ', the experimental frequency is recorded as P', and the unit Hz is as follows:
C'＝DATA
by comparing P and P', the precision of the clock to be tested can be obtained.
In this embodiment, the length of the test time is set as the unit time, the sampling test is performed for multiple times, and the sampling data can be collected and recorded once per second, per minute, and per hour, where the hourly record is taken as the unit time, for example, the working clock of the FPGA is counted, and the first numerical value after the test start time node and the first numerical value before the test end time node are recorded as the CNTs respectively 0 ,CNT 1 ,...,CNT n And CNT' 0 ,CNT' 1 ,...,CNT' n In unit time, FPGA samples and counts the rising edge of the clock to be tested and respectively records the number as DATA 0 ,DATA 1 ,...,DATA n 。
The number of rising edges of the clock to be tested in the test time period is recorded as C, the theoretical frequency is recorded as P, and the unit Hz has the following values:
1h＝C/P
the experimental value of the number of rising edges of the clock to be tested in the test duration is recorded as C ', the test frequency is recorded as P', and the unit Hz has the following values:
C' 1 ＝DATA 1
...
C' n ＝DATA n
theoretical value P and experimental value P 'can be obtained' 1 ,P' 2 ,...,P' n According to P' 1 ,P' 2 ,...,P' n The values may result in an aging curve S, i.e. a drift state.
As shown in fig. 2, the present invention provides a method for testing clock accuracy and drift by using satellite timekeeping, which includes the following steps:
s1, receiving time information sent by a satellite, sending the time information to an FPGA (field programmable gate array), and analyzing the time information and 1pps timekeeping information through the FPGA;
s2, accessing a clock to be tested, receiving a command of a main control CPU, and analyzing a test time node and a test time length according to the time information;
s3, counting the working clock of the FPGA between the rising edge of each 1pps of timekeeping information and the rising edge of the clock to be tested, recording the frequency of the working clock of the FPGA as P0, and recording the working clock count value CNT of the test start time node and the working clock count value CNT' of the test end time node;
s4, sampling and counting rising edges of the clock to be tested between the test starting time node and the test ending time node, and recording the rising edges as DATA;
s5, calculating to obtain the theoretical frequency of the clock rising edge according to the test time node and the theoretical values of the number of the rising edges of the clock to be tested within the test time;
s6, calculating to obtain the testing frequency of the rising edge of the clock according to the frequency P0 of the working clock of the FPGA, the sampling number of the rising edge of the clock to be tested, the testing time node, the working clock count value CNT of the testing starting time node and the working clock count value CNT' of the testing ending time node;
s7, comparing the theoretical frequency of the clock rising edge with the testing frequency of the clock rising edge to obtain the precision of the clock to be tested;
s8, sampling a unit time node of a clock to be tested;
and S9, calculating according to the unit time node of the sampled clock to be tested and the precision of the clock to be tested for a plurality of times to obtain an aging curve, and obtaining the test state of the clock precision and the drift according to the aging curve.
Through the design, the problem of testing the clock frequency is solved, the testing precision can reach ns level, the testing time node can be freely configured by the master control, the testing time length can be freely configured by the master control, the clock frequency testing precision is improved according to the satellite time service system, and meanwhile, the whole experimental testing step is more flexible.
Claims (6)
1. The testing device for realizing clock precision and drift by using satellite timekeeping is characterized by comprising an FPGA, and a satellite receiver, a master control CPU and a clock module to be tested which are respectively connected with the FPGA;
the satellite receiver is used for sending time information to the FPGA;
the FPGA is used for accessing a clock to be tested, receiving a master control command and analyzing a test time node and a test time length according to time information sent by the satellite receiver;
the master control CPU is used for sending test duration to the FPGA and respectively calculating theoretical frequency of a clock rising edge and test frequency of the clock rising edge by using the test time node and the test time length;
the clock module to be tested is used for comparing the theoretical frequency of the clock rising edge with the testing frequency of the clock rising edge to obtain the precision of the clock to be tested, calculating an aging curve according to the sampled unit time node of the clock to be tested and the precision of the clock to be tested for a plurality of times, and obtaining the testing state of the clock precision and the drift according to the aging curve, wherein the testing process of the testing device is as follows:
receiving time information sent by a satellite, sending the time information to the FPGA, and analyzing the time information and 1pps time keeping information through the FPGA;
accessing a clock to be tested, receiving a command of a main control CPU, and analyzing a test time node and a test time length according to the time information;
counting the working clock of the FPGA between the rising edge of each 1pps of timekeeping information and the rising edge of the clock to be tested, recording the working clock frequency of the FPGA as P0, and recording a working clock count value CNT of a test start time node and a working clock count value CNT' of a test end time node;
acquiring the rising edge of the clock to be tested between the test starting time node and the test ending time node, and recording the rising edge as DATA;
calculating to obtain the theoretical frequency of the clock rising edge according to the test time node and the theoretical values of the number of the rising edges of the clock to be tested within the test time length;
calculating to obtain the test frequency of the rising edge of the clock according to the frequency P0 of the working clock of the FPGA, the sampling number of the rising edge of the clock to be tested, the test time node, the working clock count value CNT of the test starting time node and the working clock count value CNT' of the test ending time node;
comparing the theoretical frequency of the clock rising edge with the test frequency of the clock rising edge to obtain the precision of the clock to be tested;
sampling a unit time node of a clock to be tested;
and calculating according to the unit time node of the sampled clock to be tested and the precision of the clock to be tested for a plurality of times to obtain an aging curve, and obtaining the test state of the clock precision and the drift according to the aging curve.
2. The device for testing the clock accuracy and the clock drift by using the satellite timekeeping as claimed in claim 1, further comprising a peripheral and an LED respectively connected to the FPGA, wherein the peripheral and the LED are both used for displaying the test state of the clock accuracy and the clock drift.
3. The method for testing the clock precision and the drift by using the satellite timekeeping is characterized by comprising the following steps of:
s1, receiving time information sent by a satellite, sending the time information to an FPGA (field programmable gate array), and analyzing the time information and 1pps timekeeping information through the FPGA;
s2, accessing a clock to be tested, receiving a command of a main control CPU, and analyzing a test time node and a test time length according to the time information;
s3, counting the working clock of the FPGA between the rising edge of each 1pps of timekeeping information and the rising edge of the clock to be tested, recording the frequency of the working clock of the FPGA as P0, and recording the working clock count value CNT of the test start time node and the working clock count value CNT' of the test end time node;
s4, sampling and counting rising edges of the clock to be tested between the test starting time node and the test ending time node, and recording the rising edges as DATA;
s5, calculating to obtain the theoretical frequency of the clock rising edge according to the test time node and the theoretical values of the number of the rising edges of the clock to be tested within the test time;
s6, calculating according to the frequency P0 of the working clock of the FPGA, the sampling number of the rising edge of the clock to be tested, the test time node, the working clock counting value CNT of the test starting time node and the working clock counting value CNT' of the test ending time node to obtain the test frequency of the rising edge of the clock;
s7, comparing the theoretical frequency of the clock rising edge with the testing frequency of the clock rising edge to obtain the precision of the clock to be tested;
s8, sampling a unit time node of a clock to be tested;
and S9, calculating according to the unit time node of the sampled clock to be tested and the precision of the clock to be tested for a plurality of times to obtain an aging curve, and obtaining the test state of the clock precision and the drift according to the aging curve.
4. The method as claimed in claim 3, wherein the theoretical frequency of the clock rising edge in step S5 is expressed as follows:
wherein, P represents the theoretical frequency of the clock rising edge, C represents the theoretical value of the number of the rising edges of the clock to be tested within the testing time span, T represents the testing starting time node, and T' represents the testing ending time node.
5. The method as claimed in claim 3, wherein the expression of the test frequency of the clock rising edge in step S6 is as follows:
C'＝DATA
wherein, P 'represents the clock rising edge test frequency, T represents the test start time node, T' represents the test end time node, CNT represents the working clock count value of the test start time node, CNT 'represents the count value of the test end time node, P0 represents the working frequency of the FPGA, and C' represents the rising edge sampling number of the clock to be tested.
6. The method according to claim 3, wherein the aging curve in step S9 has the following expression:
S＝P′ 1 ,P′ 2 ,...,P′ n
C′ n ＝DATA n
wherein S represents an aging curve, P' n Test frequency, C 'representing the number of n-th rising edges' n The number of rising edges of the nth clock to be tested is shown as an experimental value, P0 represents the working frequency of the FPGA, and CNT n Denotes an operation clock count value, CNT ', of an nth test start time node' n Count value, DATA, indicating the nth test end time node n And the experimental value of the number of the long rising edges of the nth clock to be tested during testing is shown.
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