CN104681510A - 用于嵌入半导体裸片的桥结构 - Google Patents
用于嵌入半导体裸片的桥结构 Download PDFInfo
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- CN104681510A CN104681510A CN201310644104.1A CN201310644104A CN104681510A CN 104681510 A CN104681510 A CN 104681510A CN 201310644104 A CN201310644104 A CN 201310644104A CN 104681510 A CN104681510 A CN 104681510A
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Abstract
本发明公开了一种半导体器件和其制造方法。该半导体器件包括安装、在基板的表面上的半导体裸片,例如控制器裸片。一个半导体桥也安装在基板上,半导体裸片适配在桥结构的底部表面中形成的沟槽之内。该桥结构可以由半导体晶圆形成为作用为机械间隔层的虚设桥结构、或同时作用为机械间隔层和集成电路半导体裸片的IC桥结构。存储器裸片也可以被安装在桥结构的顶上。
Description
背景技术
可携带消费电子产品需求的强烈增长带动了大容量存储器件的需求。非易失性的半导体存储器器件——例如快闪式存储卡——正在被广泛使用以满足始终增长的数字信息存储和交换的需要。它们的可携带、多功能以及稳固的设计,与其高可靠性和大容量一起,使这样的存储器件非常合适用于多种多样的电子设备,包括例如数码相机、数字音乐播放器、视频游戏机、PDA和蜂窝话。
虽然已知有多种封装结构,但是快闪式存储卡通常可以作为***级封装(SiP)或多芯片组件(MCM)来制造,其中较多的裸片(die)被安装和内部互联在较小的占地面积(footprint)的基板上。基板通常可以包括硬的、介电的、在一面或两面都蚀刻有导电层的基底(Base)。电连接被形成于裸片和(一个或多个)导电层之间,而(一个或多个)导电层提供了用于从裸片到主机设备的连接的电导线结构。一旦构成了裸片和基板之间的电连接,则该部件(assembly)被提供保护性封装的塑封化合物(Molding Compound)包住。
图1和图2(不包括图2的塑封化合物)示出了传统的半导体封装20的横截面侧视图和俯视图。典型的封装包括多个半导体裸片,诸如粘结到基板26上的快闪式存储器裸片22和控制器裸片24。在裸片制造过程中可以在半导体裸片22、24上形成于多个裸片焊盘(bond pad)28。同样地,可以在基板26上形成多个触点盘(contact pad)30。裸片22可以被粘结到基板26上,然后裸片24可以被安装在裸片22上。然后,所有的裸片都可以通过在各个裸片焊盘28和触点盘30之间粘结线焊32来被电耦合到基板。一旦构成所有电连接,裸片和线焊可以被包封在塑封化合物34中以密封该封装博美狗保护裸片和线焊。
为了最有效地使用封装占地面积,已知要么一个完整地冲抵另外一个、要么如图1和图2所示的偏移(Offset)地,将半导体裸片一个堆叠在另外一个顶上。在偏移配置中,一个裸片被堆叠在另外一个裸片的顶上,从而较低的裸片的焊盘被暴露。偏移配置提供了如下优点:可以方便地接入该堆叠中的每一个半导体裸片的焊盘。虽然仅在图1的堆叠中示出两个存储器裸片,但是可知在该堆叠中可提供更多的存储器裸片,诸如例如四个或八个存储器裸片。
为了在半导体封装中提高存储器容量同时保持或降低封装的总尺寸,存储器裸片的尺寸相比封装的总尺寸变大。因此,存储器裸片的占地面积通常几乎和基板的占地面积一样大。
控制器裸片24通常小于存储器裸片22。于是,控制器裸片24传统上被放置于存储器裸片堆叠的顶上。这样的结构有一些缺点。例如,很难形成从控制器裸片上的裸片焊盘往下到基板的多个线焊。已知在控制器裸片之下提供了***件(interposer)或重分布(redistribution)层从而构成从控制器裸片到***件,然后又从***层往下到基板的线焊。然而,这增加了半导体器件的制造的成本和复杂性。此外,从控制器裸片到基板的相对长的线焊长度减缓了半导体器件的操作。
附图说明
图1是包括以偏移关系堆叠的一对半导体裸片的传统半导体器件的现有技术的边缘视图。
图2是包括以覆盖关系堆叠并且通过间隔层分离的一对半导体裸片的传统半导体器件的现有技术的边缘视图。
图3是形成根据本发明的实施例的半导体裸片的流程图。
图4是根据本技术的第一实施例的制造半导体器件的一个阶段的透视图。
图5是根据本技术的第一实施例的制造半导体器件的另一个阶段的透视图。
图5A根据本技术的替代实施例的制造半导体器件的一个阶段的透视图。
图6是根据本技术的实施例的形成桥晶圆的流程图。
图7-9是根据本技术的实施例的包括沟槽的部分加工的晶圆的俯视图、透视图和仰视图。
图10-13是根据本技术的第一实施例的虚设桥(dummy bridge)结构的不同视图。
图14是根据本技术的实施例的桥结构的边缘视图。
图15是根据本技术的第一实施例的制造半导体器件的另一个阶段的透视图。
图16是根据本技术的第一实施例的制造半导体器件的另一个阶段的透视图。
图17是根据本技术的第一实施例的制造半导体器件的另一个阶段的透视图。
图18和19是根据本技术的第二实施例的形成IC桥结构的替代方法的流程图。
图20和21是根据本技术的实施例的包括沟槽的IC晶圆的俯视图和仰视图。
图22-25是根据本技术的第二实施例的IC桥结构的不同视图。
图26是根据本技术的第二实施例的制造半导体器件的一个阶段的透视图。
图27是根据本技术的第二实施例的制造半导体器件的另一个阶段的透视图。
图28是根据本技术的第二实施例的制造半导体器件的另一个阶段的透视图。
图29是根据本技术的第二实施例的制造半导体器件的另一个阶段的透视图。
图30是根据本技术的替代实施例的制造半导体器件的一个阶段的透视图。
图31是根据本技术的另一个替代实施例的制造半导体器件的一个阶段的透视图。
图32-33例示根据本技术的实施例的桥结构的另一个替代实施例的视图。
具体实施方式
现参考图3到33描述本技术,本技术在实施例中涉及到包括半导体裸片、例如安装在基板的表面上的控制器的半导体器件。一种桥结构也被安装在基板上,而半导体裸片适配于在桥结构的底部表面中形成的沟槽之内。所述桥结构可以从半导体晶圆形成和从半导体晶圆切割成两种不同类型的桥结构中的一种。
第一种桥结构,在此称为虚设桥结构,从半导体晶圆中形成并且作用为机械间隔层。在这个实施例中,半导体晶圆可以在一个主要表面中包括数行沟槽,而在相对的主要表面中没有集成电路。各个半导体裸片然后可以从晶圆上被切割成为虚设桥结构并被粘结到基板上。
第二种桥结构,在此称为IC桥结构,从半导体晶圆中形成并且同时作用为机械间隔层和集成电路半导体裸片两者。IC桥结构可以通过至少两种方法制造。在第一种方法中,在半导体晶圆的一个主要表面上加工集成电路,并且仅在与相对主要表面上的集成电路对准后才在该相对的主要表面中形成沟槽。在第二种方法中,在半导体晶圆的一个主要表面中形成沟槽,而仅仅在与相对的主要表面中的沟槽对准后才在该相对的主要表面上形成集成电路。要么以第一种要么以第二种方法形成的各个半导体裸片然后可以被从晶圆上切割(dice)为IC桥结构并被粘结到基板上。接下来将解释这些实施例的桥结构的另外的细节。
应该了解本发明可以以多种不同的方式来实施,而不应该被理解为被这里提出的实施例所限制。相反地,提供这些实施例从而这个公开变得彻底和完整并且将会完全地传达给那些在本领域的技术人员。实际上,本发明意图覆盖这些实施例的替代、修改和等效,所述实施例被包括在本发明的如同通过附加权利要求所定义的范围和精神之内。而且,在接下来的本发明的具体描述中,阐述数目众多的具体细节以提供本发明的彻底了解。然而,对于本领域的技术人员很清楚的是,本发明也可以在没有这些具体细节的情况下实践。
词语“顶部”和“底部”、“上部的(较高的)”和“下部的(较低的)”和“垂直”和“水平”在这里仅可以出于示例和例证的目的来使用,并不是意味着如此限制本发明的描述,因为所引用参考的词语可以在位置和方向上交换。同样,如同在这里使用的,词语“大体上(实质上)”和/或“大约”意味着所述具体尺寸和参数可能在对于给定应用的可接受的制造公差范围内的变化。在一个实施例中,可接受的制造公差是±.25%。
现参考图3、6、18和19的流程图以及图4-5、7-17和20-33的视图阐述本发明的一个实施例。尽管这些图示示出一个单独的半导体器件100,或其的一部分,应该了解该器件100可以与其它多个器件100一起在一个基板板子上被成批地加工以实现规模经济。基板板子上的半导体器件100的行和列的数目可以变化。
基板板子可以多个基板102(再次,如此的基板在图4-5中为了示例而示出)开始。基板102可以是多种不同芯片载体媒介,包括印刷电路板(PCB)、引线框架或载带自动键合(TAB)带。基板可以包括多个通孔(via)104、电引线106(electrical trace)和触点盘108。所述基板102可以包括更多的通孔104、引线106和盘108(其中仅仅有一部分在图中被编号),并且它们可能在与图中所示地不同的位置上。
参考图3的流程图,无源元件112可以在步骤200中被粘结到基板102。一个或多个无源元件可以包括例如一个或多个电容器、电阻器和/或电感器,虽然也可以构思其它元件。所示出的无源元件112(其中仅有一个在图中被编号)仅仅作为示例,并且其数字、类型和位置都可以在其它实施例中变化。所述无源元件112可以在基板102表面之上延伸。如此,它们可以被安装在下面阐述的存储器裸片堆叠的占地面积之外。替代地,无源元件可以被定位于基板102上以便适配在安装在如下面阐述的基板上的桥结构的沟槽之内。如图示,所述无源元件112可以适配在桥结构中的沟槽之内。
在步骤204,半导体裸片114可以被安装在基板102的表面上。如下面阐述的,所述半导体裸片114也可以被定位于基板102上以便在桥结构被安装于基板上时适配于桥结构中的沟槽之内。所述半导体裸片114可以是控制器ASIC。然而,裸片114可以是其它类型的半导体裸片,例如DRAM或NAND。
图5示出安装于基板102之上的半导体裸片114。所述半导体裸片114包括裸片焊盘116,其中之一例如在图5中被标记。所述裸片焊盘116可以通过在线焊步骤206中的线焊118被电耦合到基板102上的触点盘108。需要了解所述半导体裸片114可以使用其它工艺被电耦合到基板102上。例如,所述半导体裸片114可以是焊接在基板102的触点盘上的倒装芯片。作为另外的示例,导电引线可以通过在裸片焊盘和触点盘之间的已知的印刷工艺被印刷以便将半导体裸片114电耦合到基板102。
已示出的裸片焊盘116和线焊118的数量仅仅出于清晰性,需要了解可以在其它实施例中存在更多的触点盘108、裸片焊盘116和线焊118。而且,虽然图5示出的半导体裸片114仅仅在两面具有裸片焊盘和线焊,需要了解的是,半导体裸片114可以在其它实施例中在半导体裸片114的所有四面都具有裸片焊盘和线焊,例如如图5A所示。所述半导体裸片114替代地可以在其它示例中一面或者三面具有裸片焊盘116和线焊118。
根据本技术,在步骤208中,桥结构120可以紧邻着被安装到基板102上。所述桥结构120被形成具有底部表面中的沟槽。所述桥结构120可以被安装到基板102上,从而使得半导体裸片114(和可能的基板102的表面上的其它结构)位于在沟槽之内。本技术的一个特征是桥结构从半导体晶圆形成。此特征的一个优点在于,所述桥结构可以用和如下文阐述的安装在桥结构顶部的其它半导体裸片的材料一样的材料制成,从而避免了热失衡(Mismatch)。另外的优点在于,制造半导体器件100的生产工厂通常具有处理半导体晶圆的工具和工艺。因此,所述桥结构120从半导体晶圆的形成对于生产厂家来说涉及最小的额外成本和加工工序。
现参考图6-8,根据第一实施例的虚设桥结构120a可以从半导体晶圆300中形成。半导体晶圆300起始作为可以在步骤250中形成的晶圆材料的锭。在一个示例中,形成晶圆300的锭可以是由要么根据Czochralski(拉晶法)(CZ)工序要么根据浮区(floating zone)法(FZ)工序生长的单晶硅。然而,如下面所阐述的,在得到的桥结构纯粹是机械间隔层的实施例中,如图6所示,形成晶圆300的锭可以是多晶硅或任何多晶半导体材料以便降低这种虚设桥结构的材料的成本。
除硅以外,应该理解,晶圆300可以由任何其它半导体元素或化合物形成,包括而不限于IV族元素半导体、IV族化合物半导体、VI族元素半导体、III-V半导体、II-VI半导体、I-VII半导体、IV-VI半导体、V-VI半导体和II-V半导体。额外的,当晶圆300被用于形成图6中的实施例中的间隔层时,虚设桥结构120a可以是半导体元素或化合物之外的多种材料。
在步骤252中,这些半导体晶圆300可以从锭上被切割下来,并且在两个主要表面上被打磨以提供平滑的表面。晶圆300可以具有第一主要表面304(图9)和相对的第二主要表面305(图7)。在步骤256中,可以施加砂轮(grinding wheel)于第二主要表面305以便从背磨(backgrind)该晶圆300,例如从780μm到280μm,虽然这些厚度仅仅作为一种示例并且可以在不同的实施例中会变化。这一步骤以虚线示出,因为该步骤在实施例中可以被省略而晶圆300被保留在其被切割时的厚度。还可以想象的是,背后研磨步骤256在工序中稍后被执行,例如在如下阐述的沟槽形成步骤之后。
在步骤258中,沟槽302(其中一些在图7和8中被编号)被形成于晶圆300的第二主要表面305中。在实施例中,沟槽可以是6mm宽并且以平行的长度延伸穿过第二主要表面305。沟槽302彼此之间相互隔开,从而一旦晶圆被如下阐述的那样切割,每条沟槽302被定位于所产生的半导体裸片的底部表面中的相同位置。例如,在一个实施例中,所切割的桥结构120每一个都有12mm的宽度。在这样的示例中,沟槽302可以彼此间隔12mm(中心到中心),并且被形成以便位于桥结构的宽度的中心。因此,一个12mm宽的桥结构会有6mm宽的沟槽,沟槽的每侧有3mm。应该了解,这些尺寸仅仅是一种示例,其每一个在其它实施例中都可以变化。而且,尽管沟槽302在一个实施例中位于每个桥结构的中心,应该了解,沟槽302在其它实施例中也可以相反地在桥结构的宽度上更接近一个边缘或另外一个边缘。
沟槽302可以以到200μm的深度形成。应该了解的是,沟槽302可以被形成得更深或者更浅地,只要满足条件沟槽足够深以被定位于半导体裸片114和其上形成的任何线焊之上,而不会导致沟壁和半导体裸片/线焊之间的接触。
可以通过各种不同技术来形成沟槽302。在一个示例中,可以由锯条(saw blade)306(图8)执行“半锯开(half-cut)”到晶圆300的表面中来形成沟槽302;即,进入表面但是不彻底贯穿晶圆的厚度。图8所示的锯条形成了一些而非全部的沟槽302。在此示例中锯条306的厚度可以变化。在一个示例中,锯条306可以是60μm宽。这样的锯条可以锯100遍以便在晶圆300中形成6mm宽且均一深度的单条沟槽。那样的工艺可以被重复用于遍及晶圆300的宽度的所有沟槽。
应该了解的是,锯条的厚度在不同的实施例中可以是不同的。例如,锯条可以是1.0mm(6遍以便形成6mm宽且均一深度的沟槽),2.0mm(3遍以便形成6mm宽且均一深度的沟槽)或6.0mm(1遍以便形成6mm宽且均一深度的沟槽)。也可构思其它锯条厚度。
在另外的实施例中,可以在具有圆形磨铣钻头(milling bit)(未示出)的磨铣(milling)工艺中形成沟槽302。在锯条306沿着平行于晶圆300的第二主要表面305的旋转轴进行半锯开的地方,磨铣钻头沿着垂直于该第二主要表面305的旋转轴进行半锯开。磨铣钻头可以例如有6.0mm的直径和至少沟槽302的深度的厚度,从而可以由磨铣钻头的一遍来形成每一条沟槽302。在其它实施例中,磨铣钻头可以有更小的直径以便执行超过一遍来形成均一深度的单个沟槽。
在另外的实施例中,可以构思使用激光(未示出)来形成沟槽302。在一个这样的示例中,可以使用一个低功率CO2激光器烧蚀(ablate)一部分晶圆以进行第二主要表面305上的所希望的半锯开。激光器可以以一遍或多遍来形成每一条沟槽,取决于使用的激光光束的直径。
在另外的实施例中,可以在晶圆300的第二主要表面305中蚀刻沟槽302。可以以多种不同工艺来蚀刻沟槽,包括例如使用液体蚀刻剂、干式等离子蚀刻剂或蒸汽蚀刻剂。在一个示例中,一种光刻胶(未示出)被施加到遍及整个第二主要表面305。使用在下文中阐述的掩模对准方法中的一种,接下来,使用紫外线,使得第二主要表面305上的光刻胶(未示出)向对准的沟槽掩模(未示出)曝光。光刻胶(未示出)然后被显影,这导致沟槽掩模的光学图案被转移为光刻胶中的开窗(open window)。然后,晶圆300的整个第二主要表面305被曝光以进行选择性蚀刻,这种选择性蚀刻在第二主要表面305中切割沟槽而不影响到光刻胶。光刻胶在剥落(Stripping)工艺中被清除以获得第二主要表面305中的沟槽302。
在一个实施例中,用于蚀刻沟槽302的工艺可以是各向异性的蚀刻,其导致沟槽302具有直角的或近似直角的侧壁。在另外的实施例中,所述工序可以是各向同性的蚀刻,其导致沟槽302具有更圆形的侧壁。蚀刻剂的浓度和蚀刻剂在晶圆300上停留的时间都可以被控制以提供具有所希望的深度和尺寸的沟槽302。
如同上面提到的,在一个实施例中,沟槽302的深度可以是在到200μm之间。在一个示例中,可以一次以这个深度形成一条沟槽302。因此,在使用60μm宽的锯条来切割沟槽302的一个示例中,可以通过锯条在宽度方向上(width-wise)行进100遍来完全切割一条6mm的沟槽到所希望的深度。在另外的实施例中,构想每次切割(或激光或蚀刻工艺)仅仅到部分的深度。例如,在沟槽302深度为处,可以有三次分离的部分深度切割,第一次下到第二次下到第三次下到在另外的实施例中,形成完全深度的部分切割/激光/蚀刻的数目可以改变为高于或低于三次。
因此,在一个使用锯进行的6mm沟槽切割的示例中,其中在三次部分切割中形成该深度,可以一共进行300次切割以便形成该沟槽——跨越宽度(across the width)的第一组100次切割到第一部分深度,跨越宽度的第二组100次切割到第二部分深度,跨越宽度的第三组100次切割到第三部分深度。再次地,这些次数仅仅作为示例,也可以存在不同次数的宽度方向和部分深度切割。代替进行跨越宽度的连续切割、然后重复到新的深度,也可以通过连续地进行切割下到完全的深度,然后重复跨越沟槽的宽度,来形成沟槽302。
在关于图6的实施例中,晶圆300的第一主要表面304未被加工为包含集成电路。在这样的实施例中,在确定将沟槽定位在第二主要表面305上哪里时,可以不需要将第二主要表面305上的沟槽302与第一主要表面304对准。在这样的实施例中,可以如同上面阐述的那样形成沟槽,然后,以第二主要表面305朝上,晶圆300可以在步骤260中被切化(scribed)和被切割成单个的半导体裸片,每一个半导体裸片形成虚设桥结构120a。可以想象的是第一主要表面304可以包含这样的特征,即在形成沟槽302之前需要对准在第二主要表面305上的沟槽位置。在下文中描述用于将第二主要表面305上的沟槽与第一主要表面304上的特征对准的多种实施例。
在图6的实施例中,在切割之前,在晶圆300上没有形成集成电路,并且所完成的虚设桥结构120a作用为没有电功能的机械间隔层。图10和11示出包括沟槽302的完成的虚设桥结构120a的俯视图和俯视剖面图。图12和13示出包括沟槽302的完成的虚设桥结构120a的仰视图和仰视剖面图。图14示出在步骤208(图3)中被封装到基板102上之后的虚设桥结构120a的边缘视图。如图13所见,沟槽302定义了桥结构120a的较低表面中的轨道(rail)122a、122b。在一些实施例中,轨道122a、122b延伸达到桥结构120a的整个长度。可以通过粘合剂、例如轨道122a、122b上的裸片粘附膜(die attach film)将虚设桥结构120a粘结到基板102上。
图14也示出位于沟槽302之内的半导体裸片114。沟槽302和半导体裸片114的相对尺寸仅是示例之用,而可以不是按照比例画出的。在一个示例中,半导体裸片114可以有大约为5mm的宽度。随着线焊118从半导体裸片114的一条或多条边缘落下,半导体裸片114和线焊可以适配在具有如同上所述为6mm的宽度w的沟槽之内。这些尺寸都可以变化以提供足够大的沟槽以接纳半导体裸片114和线焊(如果存在)。
如同上面提到的,桥结构120的高度h1可以例如为大约280μm,而沟槽302的高度h2可以例如处于76μm到127μm的范围之内。这使得沟槽之上的桥结构的高度h3高出沟槽达153μm到204μm。这些尺寸中的每一个都是出于示例之用而可以在其它实施例中变化。半导体裸片114可以有46μm的厚度。粘附半导体裸片114的裸片粘附膜可以具有10μm的厚度,而粘附桥结构120的裸片粘附膜可以具有20μm的厚度。通过这些尺寸,在半导体裸片114之上、在沟槽之内还可以存在一个间隔h4,范围在117μm到168μm。这一间隔对于可能使用到的线焊是足够大的。这些尺寸在其它实施例中可以变化。例如,在其它实施例中,间隔h4可以是106μm。
再次参考图3的流程图和图15的透视视图,一个或多个半导体裸片140可以在步骤214中被堆叠到虚设桥结构120a的顶上。线焊桥结构120的步骤212是虚线示出的,因为这一步骤将在桥结构没有电子功能的实施例中被省略。如图16所示,可以以阶梯型结构堆叠半导体裸片140。虽然示出的是两个这样的半导体裸片140,但是在其它实施例中可以在裸片堆叠中有单个的半导体裸片140或多于两个的半导体裸片。半导体裸片140可以包括集成电路142,其作用为例如为存储器裸片和更优选NAND快闪式存储器裸片,但是也可构思其它类型的半导体裸片。
在步骤216中,半导体裸片140可以在已知的(使用例如线焊劈刀(Capillary)(未示出))线焊工艺中通过线焊144被线焊到基板102上的触点盘108。
在裸片堆叠被形成并且被线焊到基板102上的触点盘108之后,半导体器件100可以在步骤220中被装入塑封化合物150中,并且在步骤224中从板上被单片化(singulate),以形成图17所示的完成的半导体器件100。塑封化合物150可以是已知的环氧化物,例如从总部皆在日本的Sumitomo公司和Nitto Denko公司可得的。其后,器件100在步骤226中经过电测试和老化(burn in)测试。在一些实施例中,完成的半导体器件100可以可选地在步骤228中被装入盖子(未示出)中。
关于图6-17描述的虚设桥结构120a是间隔层,其从不带有集成电路的部分加工的晶圆形成。虚设桥结构120a允许半导体裸片114(和可能的其它元件)被安装到基板的该表面上和在其之上延伸,同时提供平滑的表面以供在其上安装存储器裸片堆叠。
然而,如同提及的,替代地,桥结构120可以是一个IC桥结构120b,其从带有集成电路的半导体晶圆形成。可以以至少两种方式制造这样的实施例。在第一种制造工序中,在沟槽302被形成于相对的第二主要表面305中之前,集成电路被形成于晶圆300的第一主要表面304上。参考图18的流程图和其后的图片描述这样的实施例。在第二种制造工序中,在集成电路被形成于相对的第一主要表面304中之前,沟槽302被形成于第二主要表面305中。参考图19的流程图和其后的图片描述这样的实施例。
现参考图18的流程图,可以从在步骤262中形成的锭(ingot)上切割晶圆300。形成晶圆300的锭在这个实施例中可以是根据CZ方法或根据FZ工艺生长而成的单晶硅。虽然硅是一种示例,但是所述锭更一般地说也可以由任意其它元素半导体或化合物、包括但不限于IV族元素半导体、IV族化合物半导体、VI族元素半导体、III-V半导体、II-VI半导体、I-VII半导体、IV-VI半导体、V-VI半导体和II-V半导体形成。
在步骤264中,半导体晶圆300可以从锭上切割并且在第一主要表面304(图20)和第二主要表面305(图21)上都被抛光以提供平滑的表面。在步骤266中,第一主要表面可以经受多种不同工艺步骤以在第一主要表面之上和之中形成集成电路。所述步骤可以包括以垂直和水平的划线308切划第一主要表面304以协助从晶圆300上切割各个半导体裸片。在一些实施例中,集成电路可以作为NAND快闪式存储器半导体裸片而操作,虽然可以构思其它类型的集成电路。
在步骤268中,施加砂轮(grinding wheel)于第二主要表面305以背后研磨晶圆300例如从780μm到280μm,虽然这些厚度仅仅作为一种示例并且在不同的实施例中可以变化。如上,这一步骤可以被省略或在晶圆300加工的稍后阶段中执行。
在步骤270中,布置在第二主要表面305中的沟槽302可以关于的形成于第一主要表面304中的各个集成电路对准。在一个示例中,第一主要表面304上的集成电路的位置关于表面304上的选定的点是已知的,而表面304上选定的点的位置关于相应的相对表面305上的选定的点是已知的。在这一情况下,通过将沟槽的位置对准到第二主要表面305上的选定的点,第二主要表面305上的沟槽302的位置可以被对准到第一主要表面304上的集成电路。
例如,晶圆300通常包括一条平线(Flat)310(图20-21)用于标识和导向用于加工的晶圆的晶体结构。所述横边310终止于被归类为***点(cleave points)的点,在那里晶圆300的圆形部分和平线310相接(meet)。第一主要表面304具有***点312a和312b,而第二主要表面305具有***点314a和314b。表面304上的***点312a对准表面305上的***点314a(它们被示出在图20和21的视图中关于彼此翻转,如同晶圆300在图21的视图中关于图20翻转)。同理适用于***点312b和314b。
可以相对于至少一个***点,例如***点312a,以已知的关系形成第一主要表面304上的集成电路的位置。在第一主要表面304上的***点312a相对于第二主要表面305上的***点314a的位置是已知的。因此,可以相对于***点314a的预定距离来设置在第二主要表面305上的沟槽302的位置,以便确保第二主要表面305上的沟槽302相对于第一主要表面304上的集成电路的对准。
在另外的实施例中,第二主要表面305朝上,可以使用IR(红外线)摄像头透过晶圆成像以便对齐第二主要表面上的沟槽位置和第一主要表面上的集成电路。红外线光线具有相对可见光的更长的波长,且具有更少的散射。它由此是可能从第二主要表面305成像第一主要表面304上的集成电路的特征。这通过与第一主要表面304上的集成电路的合适的对准来允许限定第二主要表面305中的沟槽的位置。这样的用于在晶圆的第一和第二主要表面之间对准的技术已知例如来源于Disco公司,其营业地点在日本东京。
应该了解的是,其它技术也可以被用于对准晶圆300的第一主要表面上的集成电路与晶圆300的第二主要表面上的既有的沟槽302,或对准第二主要表面上的沟槽302与第一主要表面上的既有的特征。此种工艺的其它示例见于美国专利No.5,530,552,题为“Double Sided Wafer,Alignment Technique”,公告于1996年6月25日,和美国专利No.8,283,256,题为“Methods of FormingMicrodevice Substrates Using Double-Sided Alignment Techniques”,公告于2012年10月9日。这两个专利在此处都被整体合并以供参考。
一旦沟槽的位置被合适地相对于第一主要表面的各个集成电路对准,可以在步骤274中在第二主要表面305中形成沟槽302,如同图21中的第二主要表面305的视图所示。可以以任意上述的实施例中一样的方式形成沟槽。在形成沟槽302之后,可以在步骤276中切划并且切割晶圆300成单独的半导体裸片。每一个被切割的IC桥结构120b可以作用为间隔层和如下阐述的集成电路半导体裸片。
图19描述了用于形成IC桥结构120b的一种替代的制造工艺。在步骤282中,可以从如上描述形成的锭切割晶圆300,并且晶圆300可以在步骤284中从如上描述形成的锭上被切割和被抛光。被切割的晶圆300可以在步骤286中经受背磨,虽然这一工艺可以被省略或在其它实施例的制造工艺中的稍后阶段执行。在步骤288中,可以根据任意以上描述的实施例在晶圆300的第二主要表面305上形成沟槽302。
在步骤290中,用于形成第一主要表面304上的集成电路的掩模(mask)可以相对于第二主要表面305上的沟槽302对准。可以使用任意以上描述的用于在第一和第二主要表面304、305之间对准的方法来执行这一对准。一旦集成电路的位置被设置为相对于沟槽对准中,可以在步骤394中在晶圆300的第一主要表面之中和之上形成集成电路。如上,集成电路可以形成NAND快闪式存储器,但是也可构思其它集成电路。在形成集成电路之后,在步骤396中可以在切化和切割晶圆300以创造多个半导体裸片。每一个半导体裸片可以是如下阐述的IC桥结构120b。
图22-25示出通过图18或19的工艺形成的IC桥结构120b的各种视图。所述IC桥结构120b可以是和虚设桥结构120a完全一样的,但是可以包括位于沟槽302相对的表面中的集成电路130,且可以包括裸片焊盘124(其中之一在图22和23中被编号)。如同虚设桥结构120a,IC桥结构120b可以被安装在基板102上,如图26所示在半导体裸片114之上。其后,在步骤212(图3)中可以通过如图27所示的线焊将IC桥结构120b线焊到基板102。
可以借助线焊144被添加和线焊附加的半导体裸片140,如图27和28所示以及如上描述。被添加的半导体裸片140的数目可以是多于或少于二。而且,由于在本实施例中IC桥结构120b自身可以是存储器裸片,因此在其它实施例中无需添加附加的半导体裸片。替代于在安装半导体裸片140之前线焊IC桥结构120b,可以先安装半导体裸片140,然后在同一工艺中线焊IC桥结构120b和半导体裸片140两者。
在裸片堆叠被形成且被线焊到基板102上的焊盘之后,器件100可以被装入塑封化合物150中(步骤220),并从板上被单片化(步骤224),以形成如图29所示的完成的半导体器件100。其后,器件100在步骤226中可以经过电测试和老化测试。在一些实施例中,完成的封装100可以可选地在步骤228中被装入盖子(未示出)中。
半导体器件100可以被用作LGA(触点陈列封装(land grid array))封装以便用作主机设备内的可移动存储器。在这样的实施例中,可以在基板102的较低表面(或下表面)上形成触指(contact finger)(未示出)用于在半导体器件100***主机设备之后与主机设备内的管脚相匹配。替代地,半导体器件100可以用作BGA(球栅阵列封装(ball grid array))封装以便永久地粘结到主机设备之内的印刷电路板上。在这样的实施例中,可以在基板102的较低表面上的触点盘上形成焊球(未示出)用于被焊接到主机设备的印刷电路板上。
在以上描述的实施例中,可以从部分加工或完全加工的半导体晶圆300中形成桥结构。应该了解的是,桥结构120可以在晶圆300被切割后的任何时间点从晶圆300切割,抛光和形成沟槽302。
桥结构120包括沟槽302允许例如是控制器的半导体裸片114被安装到基板102的表面上,同时提供大、平的表面用于安装附加的存储器裸片。
而且,从半导体晶圆形成桥结构提供另外的优点。例如,如同上面提到的,半导体器件制造工厂通常拥有处理和加工半导体晶圆的资源。用于吸住加工中的晶圆300的真空吸盘、用于施加裸片粘附膜到晶圆300的第二主要表面的设备、用于切割晶圆300成为各个桥结构120的晶圆切割设备和传送被分割的桥结构到基板102上的元件摘放机器人,都普遍存在于处理和加工晶圆的半导体器件制造工厂中。这使得对于工厂而言只需极少的额外成本即可方便地制造桥结构120。
而且,通过从半导体晶圆形成桥结构120,可以由与半导体裸片140同样的材料制成所述桥结构120。例如,半导体裸片140在运行时可能产生热量,这个热量可能导致桥结构120和半导体裸片140膨胀。如果桥结构120和半导体裸片140由同样材料制成,它们可以有同样的热膨胀系数。因此,当半导体加热桥结构以及桥结构之上的存储器裸片时,它们可以膨胀到相同的程度。应该了解的是,在使用虚设桥结构120a时,可以使用不同于半导体材料的材料。这些材料中的一些可以有与半导体材料一样或相似的热膨胀系数以预防热失衡(thermal mismatch)。
在以上的描述中,桥结构120是虚设桥结构120或是运行的IC桥结构。然而,在其它实施例中,桥结构120可以是具有集成电路的半导体裸片,但是不运行为电子元件。例如,可能出现半导体晶圆在形成集成电路后因为多种原因被判定为有缺陷。在这种情况下,代替抛弃晶圆,可以如同上面阐述的在晶圆的第二主要表面中形成沟槽302,并将晶圆分割成桥结构。这些桥结构可以包括集成电路,但是它们可以被用作不必被线焊到基板102的虚设桥结构。在另外的实施例中,在形成沟槽之前或之后,可以从有缺陷的晶圆的第一主要表面上刷掉集成电路,然后晶圆被分割成虚设桥结构。
在以上描述的实施例中,单个的半导体裸片114如控制器可以被安装在基板102上,然后被装入桥结构120的沟槽302之内。然而,应该了解的是,在其它实施例中,不同的半导体裸片(包括例如DRAM、NAND或其它更小的存储器裸片)和/或其它电子元件可以被安装到基板上和被定位在沟槽302之内。
另外,图30示出两片半导体裸片114、180可以被安装在沟槽302之内。在另外的实施例中,超过两片半导体裸片和/或其它电子元件可以被安装到基板上,并且当桥结构120被安装到基板上时,这些半导体裸片和/或其它电子元件被放置于沟槽302之内。
另外还应该了解的是,半导体裸片114可以在沟槽302之内有不同的尺寸。图4和5示例性地示出占据了沟槽302的相对大的部分的半导体裸片114的另外的实施例。
在以上描述的实施例中,沟槽302在桥结构120的相对的边缘之间延伸。然而,在另外的实施例中,如图32和33所示,沟槽302可以仅仅部分地在相对的边缘之间延伸,在一条边缘开口处而不在相对的边缘处开口。
总而言之,本技术的一个示例涉及到一种用于半导体器件的桥结构,所述桥结构包括:第一表面;相对于第一表面的第二表面;在第二主要表面中形成的沟槽;其中,形成桥结构的材料是源自包括单晶体半导体元素或化合物和多晶体半导体元素或化合物的组的材料。
在另外的示例中,本技术涉及到一种半导体器件,所述半导体器件包括:基板;安装于基板的表面的第一半导体裸片;和安装于基板的表面、位于第一半导体裸片之上的桥结构,所述桥结构包括毗邻基板的桥结构的表面中的沟槽,所述沟槽从桥结构的一条边缘至少部分地延伸到桥结构的相对的边缘,所述第一半导体裸片适配在桥结构中的沟槽之内。
在另一个示例中,本技术涉及到一种半导体器件,所述半导体器件包括:基板;直接安装于基板的表面的第一半导体裸片;直接安装于基板的表面、位于第一半导体裸片之上的桥结构,所述桥结构包括面对基板的桥结构的表面中的沟槽,所述沟槽在桥结构的相对的边缘之间延伸,所述第一半导体裸片适配在桥结构中的沟槽之内,所述桥结构包括源自部分加工的具有第一厚度的晶圆的预设间隔层;来自于具有比第一厚度薄的第二厚度的半导体晶圆的一个或多个第二半导体裸片的组。
前述的本发明的具体描述被提出是出于描述和图示的目的。并不是计划要变的详尽或限制本发明于所公开的精确形式。根据上面的教导的多种修改和变形都是可行的。所描述的实施例被选中以便最佳地阐述本发明的原理和其实际应用从而使本领域的其它技术人员能够最佳地利用本发明到多种实施例和利用本发明进行修改以适应认真考虑的特殊用途。本发明的范围由关于此而附加的权利要求定义。
Claims (20)
1.一种用于半导体器件的桥结构,所述桥结构包括:
第一表面;
和第一表面相对的第二表面;和
在第二主要表面中形成的沟槽;
其中形成桥结构的材料源自包含单晶半导体元素或化合物和多晶半导体元素或化合物的组。
2.根据权利要求1所述的桥结构,其中形成桥结构的材料是源自包含IV族元素半导体、IV族化合物半导体、VI族元素半导体、III-V半导体、II-VI半导体、I-VII半导体、IV-VI半导体、V-VI半导体和II-V半导体的组的材料。
3.根据权利要求1所述的桥结构,其中所述桥结构是源自半导体晶圆的半导体裸片。
4.根据权利要求1所述的桥结构,其中所述桥结构包括第一表面中的集成电路。
5.根据权利要求4所述的桥结构,其中所述集成电路作用为快闪式存储器。
6.根据权利要求1所述的桥结构,其中所述桥结构不包括集成电路。
7.根据权利要求1所述的桥结构,还包括彼此相对并且每一个在第一和第二表面之间延伸的第一和第二边缘,第二表面中的沟槽从第一边缘延伸到第二边缘。
8.一种半导体器件,包括:
基板;
安装在基板的表面的第一半导体裸片;和
安装在基板的表面、在所述第一半导体裸片之上的桥结构,所述桥结构包括毗邻基板的桥结构的第一表面中的沟槽,所述沟槽从桥结构的边缘至少部分地延伸到桥结构的相对的边缘,第一半导体裸片适配于桥结构中的沟槽之内。
9.根据权利要求8所述的半导体器件,还包括安装在桥结构的顶上并且被电连接到基板上的一个或多个半导体裸片的组。
10.根据权利要求8所述的半导体器件,其中所述桥结构是由源自包含单晶半导体元素或化合物和多晶半导体元素或化合物的组的材料形成。
11.根据权利要求8所述的半导体器件,其中所述桥结构是由源自IV族元素半导体、IV族化合物半导体、VI族元素半导体、III-V半导体、II-VI半导体、I-VII半导体、IV-VI半导体、V-VI半导体和II-V半导体的组的材料形成。
12.根据权利要求8所述的半导体器件,其中所述桥结构是半导体裸片。
13.根据权利要求8所述的半导体器件,其中所述桥结构还包括和第一表面相对的第二表面,所述第二表面中具有集成电路。
14.一种半导体器件,包括:
基板;
直接安装在基板的表面的第一半导体裸片;和
直接安装在基板的表面的、在所述第一半导体裸片之上的桥结构,所述桥结构包括面对基板的桥结构的表面中的沟槽,所述沟槽在桥结构的相对的边缘之间延伸,第一半导体裸片适配于桥结构中的沟槽之内,所述桥结构包括来自部分加工的具有第一厚度的晶圆的虚设间隔层;和
来自具有比第一厚度薄的第二厚度的半导体晶圆的一个或多个第二半导体裸片的组。
15.根据权利要求14所述的半导体器件,其中形成桥结构的材料是源自包含单晶半导体元素或化合物和多晶半导体元素或化合物的组的材料。
16.根据权利要求14所述的半导体器件,其中形成桥结构的材料是源自包含IV族元素半导体、IV族化合物半导体、VI族元素半导体、III-V半导体、II-VI半导体、I-VII半导体、IV-VI半导体、V-VI半导体和II-V半导体的组的材料。
17.根据权利要求14所述的半导体器件,其中所述桥结构是源自半导体晶圆的半导体裸片。
18.根据权利要求14所述的半导体器件,其中所述桥结构包括在第一表面中的集成电路。
19.根据权利要求18所述的半导体器件,其中所述集成电路作用为快闪式存储器。
20.根据权利要求14所述的半导体器件,其中所述桥结构不包括集成电路。
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US20170179101A1 (en) | 2017-06-22 |
TW201528501A (zh) | 2015-07-16 |
US20150155247A1 (en) | 2015-06-04 |
TWI620313B (zh) | 2018-04-01 |
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