CN104681405B - The acquisition methods of electrically matched symmetric circuit - Google Patents
The acquisition methods of electrically matched symmetric circuit Download PDFInfo
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- CN104681405B CN104681405B CN201310616533.8A CN201310616533A CN104681405B CN 104681405 B CN104681405 B CN 104681405B CN 201310616533 A CN201310616533 A CN 201310616533A CN 104681405 B CN104681405 B CN 104681405B
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Abstract
The present invention provides the acquisition methods of two kinds of matched symmetric circuits of electrical property.First method is when carrying out laser thermal anneal to the wafer with symmetric circuit, so that laser beam parallel wafer surface, and the angular range for controlling the direction of laser beam and the crystal orientation of the wafer is 60 degree to 90 degree.When second method is the grid oxic horizon for the grid oxic horizon and peripheral circuit region to form logic circuit area, the oxide layer of consistency of thickness is first formed in the crystal column surface of logic circuit area and peripheral circuit region, then the peripheral circuit region is covered, the oxide layer of wet process removal logic circuit area, in the wet process removal process, the angular range between the flow direction and the symmetry axis of the symmetric circuit of corrosive liquid is 0 degree to 30 degree.Above scheme can improve the electrical of symmetric circuit and mismatch.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to the acquisition methods of electrically matched symmetric circuit.
Background technique
In semiconductor processing, some devices need to be arranged to symmetrical structure to complete some functions, with the above function
The circuit of device composition is symmetric circuit.
In the prior art, realize that the performance of each device is complete in production symmetric circuit technique due to the precision of manufacturing process
It is exactly the same relatively difficult, for these reasons, cause the electrical of the symmetric circuit of production to mismatch, this makes symmetric circuit in reality
Border is unable to control using middle electrical property.
In view of the above-mentioned problems, the prior art generally uses compensation circuit to improve above-mentioned electrical mismatch problem.So
And this will cause increasing for circuit devcie, failure rate increases.
In view of this, the present invention provides the acquisition methods of two kinds of matched symmetric circuits of new electrical property, from technological angle pair
The above problem is improved.
Summary of the invention
Problems solved by the invention is the electrical mismatch problem for improving symmetric circuit.
To solve the above problems, the present invention provides the acquisition methods of two kinds of matched symmetric circuits of electrical property, first method
Include:
Laser thermal anneal is carried out to the wafer with symmetric circuit, wherein laser beam parallel wafer surface, and laser beam
The angular range of the crystal orientation of direction and the wafer is 60 degree to 90 degree.
Optionally, the angle of the crystal orientation of the direction of the laser beam and the wafer is 90 degree.
Optionally, the symmetric circuit is located at the logic circuit area of wafer, and the wafer also has peripheral circuit region, described
The transistor gate oxidated layer thickness of peripheral circuit region is greater than the thickness of grid oxide layer of the transistor of logic circuit area；It is described to obtain
Take method further include: in the grid oxic horizon of the grid oxic horizon and peripheral circuit region that form logic circuit area, first in logic
Circuit region and the crystal column surface of peripheral circuit region form the oxide layer of consistency of thickness, then cover the peripheral circuit region, wet process
The oxide layer for removing logic circuit area, in the wet process removal process, the flow direction and pair of the symmetric circuit of corrosive liquid
Angular range between axis is referred to as 0 degree to 30 degree.
Optionally, the folder in the wet process removal process, between the flow direction and the symmetry axis of the symmetric circuit of corrosive liquid
Angle is 0 degree.
Optionally, the symmetric circuit is binary channels D/A converting circuit or current mirror.
Optionally, when the symmetric circuit is current mirror, the current mirror is more times of amplifications, current source transistor and more
Dummy argument is set between a current-copying transistor.
In addition, the present invention also provides the acquisition methods of another electrically matched symmetric circuit, the symmetric circuit position
In the logic circuit area of wafer, the wafer also has peripheral circuit region, the transistor gate oxide layer of the peripheral circuit region
Thickness is greater than the thickness of grid oxide layer of the transistor of logic circuit area；The acquisition methods include: to form logic circuit area
Grid oxic horizon and peripheral circuit region grid oxic horizon when, first logic circuit area and peripheral circuit region crystal column surface shape
At the oxide layer of consistency of thickness, the peripheral circuit region is then covered, wet process removes the oxide layer of logic circuit area, described
In wet process removal process, the angular range between the flow direction and the symmetry axis of the symmetric circuit of corrosive liquid is 0 degree to 30 degree.
Optionally, the folder in the wet process removal process, between the flow direction and the symmetry axis of the symmetric circuit of corrosive liquid
Angle is 0 degree.
Optionally, the symmetric circuit is binary channels D/A converting circuit or current mirror.
Optionally, when the symmetric circuit is current mirror, the current mirror is more times of amplifications.
Compared with prior art, during technical solution of the present invention has the advantage that 1) transistor fabrication, many places are related to
And thermal annealing, such as the activation in source, drain region Doped ions, the release etc. of metal interconnection structure thermal stress, the study found that hot edge
The rate of heat transfer in the crystal orientation direction of wafer (such as monocrystalline silicon or monocrystalline germanium) is greater than the rate of heat transfer along other directions, present invention benefit
With above-mentioned rule, when carrying out laser thermal anneal to the wafer with symmetric circuit, so that laser beam parallel wafer surface, and control
The angular range of the crystal orientation of the direction of controlling laser beam and the wafer is 60 degree to 90 degree, in this way, avoiding in wafer crystal orientation
It is excessive to state heat diffusion vector component, to realize that crystal column surface is heated evenly, each device of symmetric circuit is heated properly, performance
Obtain impartial promotion.
2) in optinal plan, the angle of the crystal orientation of the direction of the laser beam and the wafer is 90 degree, and such scheme makes
Obtaining the above-mentioned heat diffusion vector component in wafer crystal orientation is 0, further realizes crystal column surface and is heated evenly, thus symmetric circuit
Each device is heated properly, and performance obtains impartial promotion.
3) in optinal plan, in addition to control crystal column surface is heated evenly, a kind of scheme is also provided: specifically, a certain chip
It realizes certain function, generally in addition to the logic circuit area where symmetric circuit, also needs cooperation input/output circuitry, it is above-mentioned defeated
Region where entering output circuit is peripheral circuit region, and in general, the transistor of peripheral circuit region is high voltage transistor, because
And the thickness of grid oxide layer of the transistor of peripheral circuit region is greater than the thickness of grid oxide layer of the transistor of logic circuit area,
I.e. crystal column surface need to form the grid oxic horizon (Dual gate oxide) of two kinds of thickness.The gate oxidation of above two thickness
A kind of forming method of layer are as follows: first the crystal column surface in logic circuit area and peripheral circuit region forms the oxidation of a layer thickness equalization
Then layer removes the oxide layer of logic circuit area, retains the oxide layer of peripheral circuit region, then, then in logic circuit area and outside
The crystal column surface for enclosing circuit region forms the oxide layer of a layer thickness equalization, in this way, since the oxide layer of peripheral circuit region is two layers
The superposition of oxidated layer thickness, logic circuit area are only formed by the thickness of oxide layer for the second time, thus, it is above-mentioned to form logic
The grid oxic horizon of circuit region and peripheral circuit region, wherein the thickness of the grid oxic horizon of peripheral circuit region is larger.However, grinding
Discovery is studied carefully, due to using fleet plough groove isolation structure (STI) to be isolated between each transistor in logic circuit area, in fleet plough groove isolation structure
Material be generally the oxide of insulating effect, thus when removing the oxide layer of logic circuit area, can to the shallow trench every
There is certain corrosion from structure, form groove；If the flow direction of corrosive liquid is along the symmetry axis of vertical symmetry circuit at this time, due to
The presence of STI etch back trenches, can be to the wafer substrate for being used to form source of a transistor and being used to form for another transistor
The wafer substrate of leakage applies compression, or is used for shape to the wafer substrate for being used to form leakage of a transistor and another transistor
The wafer substrate of Cheng Yuan applies compression, after this causes two transistor to make, source and drain unbalanced stress of respective transistor etc..
This programme utilizes above-mentioned rule, in wet process removal process, between the flow direction and the symmetry axis of the symmetric circuit of control corrosion rate liquid
Angular range be 0 degree to 30 degree.In this way, avoiding the two transistor of symmetric circuit in the symmetrical axis direction of vertical symmetry circuit
Above-mentioned compression vector component is excessive, to realize that the two transistor source of symmetric circuit, drain region stress are impartial, performance obtains equalization
It is promoted.
4) in optinal plan, for 3) optinal plan, between the flow direction and the symmetry axis of the symmetric circuit of corrosive liquid
Angle is 0 degree.In this way, making the two transistor of symmetric circuit above-mentioned compression arrow in the symmetrical axis direction of vertical symmetry circuit
Measuring component is 0, further such that the two transistor source of symmetric circuit, drain region stress equalization, to realize the electricity of symmetric circuit
Performance obtains impartial promotion.
5) in optinal plan, above-mentioned symmetric circuit can be binary channels D/A converting circuit, or current mirror.
6) in optinal plan, for the current mirror in 5) optinal plan, which is more times of amplifications.In other words, simultaneously
To three and its above transistor carries out thermal anneal process or corrosive liquid processing, is not limited to simultaneously carry out two transistors
State processing.In addition, dummy argument is arranged between current source transistor and multiple current-copying transistors, so that source transistor, electric current are multiple
In thermal annealing process, impartial degree is influenced transistor processed by other transistors around.
7) above-mentioned 3) optinal plan is used alone, and can also play so that the electric property of symmetric circuit obtains impartial promotion
Effect.
Detailed description of the invention
Fig. 1 is that the apparatus structure in the acquisition methods of the matched symmetric circuit of electrical property provided by one embodiment of the present invention shows
It is intended to；
Fig. 2 be by the source of binary channels D/A converting circuit, drain region Doped ions activation for, using Fig. 1 shown device
The experiment results figure of progress；
Fig. 3 is the structural schematic diagram of another symmetric circuit；
Fig. 4 to fig. 6 is the signal of the acquisition methods for the matched symmetric circuit of electrical property that another embodiment of the present invention provides
Figure；
Fig. 7 is by taking binary channels D/A converting circuit as an example, using the matched symmetrical electricity of electrical property of another embodiment offer
The experiment results figure that the acquisition methods on road carry out.
Specific embodiment
During transistor fabrication, many places are related to thermal annealing, such as the activation in source, drain region Doped ions, metal mutually link
The release etc. of structure thermal stress, the study found that rate of heat transfer of the heat along the crystal orientation direction of wafer (such as monocrystalline silicon or monocrystalline germanium)
Greater than the rate of heat transfer along other directions, the present invention utilizes above-mentioned rule, is carrying out laser heat to the wafer with symmetric circuit
When annealing, so that laser beam parallel wafer surface, and the direction of control laser beam and the angular range of the crystal orientation of the wafer are
60 degree to 90 degree, in this way, avoiding the above-mentioned heat diffusion vector component in wafer crystal orientation excessive, to realize that crystal column surface is heated
Uniformly, each device of symmetric circuit is heated properly, and performance obtains impartial promotion.
In addition, a certain chip will realize certain function, generally in addition to the logic circuit area where symmetric circuit, also need to cooperate
Input/output circuitry, the region where above-mentioned imput output circuit are peripheral circuit region, in general, the crystalline substance of peripheral circuit region
Body pipe is high voltage transistor, thus, the thickness of grid oxide layer of the transistor of peripheral circuit region is greater than the crystal of logic circuit area
The thickness of grid oxide layer of pipe, i.e. crystal column surface need to form the grid oxic horizon (Dual gate oxide) of two kinds of thickness.It is above-mentioned
A kind of forming method of the grid oxic horizon of two kinds of thickness are as follows: first the crystal column surface in logic circuit area and peripheral circuit region is formed
Then the oxide layer of a layer thickness equalization removes the oxide layer of logic circuit area, retains the oxide layer of peripheral circuit region, then,
The crystal column surface in logic circuit area and peripheral circuit region forms the oxide layer of a layer thickness equalization again, in this way, due to peripheral electricity
The oxide layer in road area is the superposition of two layers of oxidated layer thickness, and logic circuit area is only formed by the thickness of oxide layer for the second time,
Thus, the above-mentioned grid oxic horizon for foring logic circuit area and peripheral circuit region, wherein the grid oxic horizon of peripheral circuit region
Thickness it is larger.However, the study found that due between each transistor in logic circuit area use fleet plough groove isolation structure (STI) every
From the material in fleet plough groove isolation structure has been generally the oxide of insulating effect, thus the oxidation in removal logic circuit area
When layer, there can be certain corrosion to the fleet plough groove isolation structure, form groove；If pair of the corrosive liquid along vertical symmetry circuit at this time
Claim axis when flowing to, it, can the wafer substrate for being used to form source to a transistor and another crystalline substance due to the presence of STI etch back trenches
The wafer substrate for being used to form leakage of body pipe applies compression, or to the wafer substrate for being used to form leakage of a transistor with it is another
The wafer substrate for being used to form source of transistor applies compression, after this causes two transistor to make, respective transistor
Source and drain unbalanced stress etc..This programme utilizes above-mentioned rule, in wet process removal process, the flow direction of control corrosion rate liquid and the symmetrical electricity
Angular range between the symmetry axis on road is 0 degree to 30 degree.In this way, avoiding the two transistor of symmetric circuit in vertical symmetry circuit
Symmetrical axis direction on above-mentioned compression vector component it is excessive, to realize that the two transistor source of symmetric circuit, drain region stress are equal
Deng performance obtains impartial promotion.
Above two method can be used alone, and can also use simultaneously, can all improve the electrical matching of symmetric circuit
Energy.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 show the apparatus structure signal in the acquisition methods of the matched symmetric circuit of electrical property of one embodiment offer
Figure.Shown in referring to Fig.1, acquisition methods include: to carry out laser thermal anneal to the wafer 1 with symmetric circuit, wherein laser beam 2
1 surface of parallel wafer, and the angle α range of the crystal orientation 11 of the direction of laser beam 2 and the wafer 1 is 60 degree to 90 degree.
The electrical matching principle that above-mentioned laser thermal annealing method can improve symmetric circuit is as follows: heat is along wafer 1(such as monocrystalline
Silicon or monocrystalline germanium) 11 direction of crystal orientation rate of heat transfer be greater than along other directions rate of heat transfer, using above-mentioned rule, to tool
When thering is the wafer 1 of symmetric circuit to carry out laser thermal anneal, so that 2 parallel wafer surface of laser beam, and control the direction of laser beam 2
Angle α with the crystal orientation 11 of the wafer 1 is more avoided that the above-mentioned heat diffusion vector component in wafer crystal orientation closer to 90 degree
Excessive, heat is largely or entirely along the direction of diffusion rate equalization, substantially uniform, thus the symmetrical electricity so that crystal column surface is heated
Each device in road is heated properly, and electric property can obtain impartial promotion.
Specifically, the symmetric circuit in above-mentioned wafer 1 is binary channels D/A converting circuit, such as binary channels is respectively I logical
Road and the channel Q, two channels have common area.
Above-mentioned laser thermal anneal can releasing for source, the activation of drain region Doped ions or metal interconnection structure thermal stress
Put etc..
Fig. 2 be by the source of binary channels D/A converting circuit, drain region Doped ions activation for, the experimental verification knot of progress
Fruit figure.Wherein, the electrical matching test method of binary channels D/A converting circuit are as follows: same electricity is applied to the channel I and the channel Q
Pressure tests the respective output electric current in two channels.The calculation method of electrical matching rate are as follows: the channel 1-(I exports the output of the channel electric current-Q
Electric current)/the channel Q output electric current.It can be seen that the angle α of the crystal orientation 11 in the direction and wafer 1 with laser beam 2 gradually
Increase, the electrical matching performance of binary channels D/A converting circuit gradually gets a promotion, and reaches peak at 90 degree.Wherein, α range is
Between 60 degree to 90 degree, relative to other angles, two channel electrical Performance Match degree are higher, can be used as improvement symmetric circuit
Laser thermal anneal optimized angle.
In addition to binary channels D/A converting circuit shown in FIG. 1, current mirror that symmetric circuit can also be as shown in Figure 3.The electricity
Stream mirror is generally more times of amplifications, and a current source transistor 31, four current-copying transistors 32 are shown in Fig. 3, thus is 4
Amplify again.In other words, while to three and its above transistor carries out the laser thermal anneal processing of above scheme, is not limited to same
When above-mentioned processing are carried out to two transistors.In addition, may be used also between current source transistor 31 and multiple current-copying transistors 32
Dummy argument 33(dummy is arranged) so that source transistor 31, current-copying transistor 32 be in thermal annealing process, impartial degree by
The influence of the other transistors of surrounding.
The setting position of above-mentioned dummy argument 33 is preferably so that adjacent source transistor 31, dummy argument 33, each current replication crystal
The distance between pipe 32 is all equal.
In implementation process, the distance of the 2 preferred distance wafer of laser beam on 1 surface of parallel wafer is 1-1.4 meters.It is above-mentioned away from
From combining the angle of laser beam 2 to control, the electrical matching performance of symmetric circuit can be further promoted.
In addition to above-mentioned laser heat treatment method, the present invention also provides another schemes, to improve the electrical property of symmetric circuit
Matching performance.
Specifically, sectional view as shown in Figure 4 and top view shown in fig. 5, the symmetric circuit are located at the logic of wafer 1
Circuit region I, the wafer 1 also have peripheral circuit region II, and the transistor gate oxidated layer thickness of the peripheral circuit region II is big
In the thickness of grid oxide layer of the transistor of logic circuit area I；The acquisition methods include: in the grid for forming logic circuit area I
When the grid oxic horizon of pole oxide layer and peripheral circuit region II, first on 1 surface of wafer of logic circuit area I and peripheral circuit region II
The oxide layer 4 for forming consistency of thickness, then covers the peripheral circuit region II, and wet process removes the oxidation of logic circuit area I
Layer 4, in the wet process removal process, the angle β range of corrosive liquid flowed between 5 and the symmetry axis 6 of the symmetric circuit is 0
It spends to 30 degree.
Above-mentioned control corrosion rate liquid stream to 5 can improve symmetric circuit electrical matching principle it is as follows: a certain chip will realize one
Determine function, generally in addition to the logic circuit area I where symmetric circuit, also needs cooperation input/output circuitry, above-mentioned input and output electricity
Region where road is peripheral circuit region II, and in general, the transistor of peripheral circuit region II is high voltage transistor, thus, outside
Enclose the transistor of circuit region II thickness of grid oxide layer be greater than logic circuit area I transistor thickness of grid oxide layer, i.e.,
1 surface of wafer need to form the grid oxic horizon of two kinds of thickness.A kind of forming method of the grid oxic horizon of above two thickness are as follows:
First the crystal column surface in logic circuit area I and peripheral circuit region II forms the oxide layer 4 of a layer thickness equalization；Then logic is removed
The oxide layer 4 of circuit region I, retains the oxide layer 4 of peripheral circuit region II, and above-mentioned removal step passes through the oxygen in peripheral circuit region II
Change covering photoresist etc. on layer 4 to be protected, then sprays into corrosive liquid (such as HF acid) wet etching on 1 surface of wafer and realize；
And then (do not scheme in the oxide layer that 1 surface of wafer of logic circuit area I and peripheral circuit region II forms a layer thickness equalization
Show), in this way, due to the superposition that the oxide layer of peripheral circuit region II is two layers of oxidated layer thickness, only second of logic circuit area I
It is formed by the thickness of oxide layer, thus, the above-mentioned grid oxic horizon for foring logic circuit area I Yu peripheral circuit region II,
In, the thickness of the grid oxic horizon of peripheral circuit region II is larger.However, the transistor of logic circuit area I is symmetrical set with structure
At symmetric circuit, i.e. the symmetry axis both sides at least partly device of symmetric circuit is completely identical in structure transistor, thus one
The source electrode of the transistor and source electrode of another transistor is adjacent or the drain electrode and the drain electrode phase of another transistor of transistor
It is adjacent.
The study found that due to using fleet plough groove isolation structure 7(STI between each transistor in logic circuit area I) isolation, shallow ridges
Material in recess isolating structure 7 has been generally the oxide of insulating effect, thus when removing the oxide layer 4 of logic circuit area I,
There can be certain corrosion to the fleet plough groove isolation structure I, form groove 71, as shown in Figure 6；If flowing to for corrosive liquid 5 is at this time
When along the symmetry axis 6 of vertical symmetry circuit, due to the presence of STI etch back trenches 71, source can be used to form to a transistor
Pole 12(may be drain electrode) 1 substrate of wafer and another transistor be used to form drain electrode 13(may be source electrode) wafer
1 substrate applies compression；When flow to 5 it is reversed when, can to a transistor be used to form drain electrode 14(may be source electrode) crystalline substance
Circle 1 substrate and another transistor be used to form source electrode 15(may be drain electrode) 1 substrate of wafer apply compression, this is caused
After two transistor makes, source-drain electrode unbalanced stress of respective transistor etc..This programme utilizes above-mentioned rule, and wet process removed
The angle β of Cheng Zhong, control corrosion rate liquid flowed between 5 and the symmetry axis 6 of the symmetric circuit is as small as possible, to reduce as far as possible
Compression vector component of the two transistor source, drain electrode of symmetric circuit on 6 direction of symmetry axis of vertical symmetry circuit, thus real
The two transistor source of existing symmetric circuit, drain stress are impartial, its performance is made to obtain impartial promotion.
To verify above scheme, by taking symmetric circuit is binary channels D/A converting circuit as an example, inventor makes on a wafer
1700 parallel symmetric circuits of above-mentioned symmetrical axis direction are made, control corrosion rate liquid flows to 5 folders of symmetry axis 6 with symmetric circuit
Angle beta is respectively 45 degree, and 90 degree, 0 degree, random four kinds of situations, electrical matching performance test experiments result is respectively along Fig. 7 from a left side
To shown in right sequence.Wherein, being gradually lower from well to poor gray value by electrical matching performance degree, (white is 255, and black is
0), i.e., color gradually deepens.Wherein, the electrical matching test method of binary channels D/A converting circuit are as follows: to the channel I and the channel Q
Apply same voltage, tests the respective output electric current in two channels.The calculation method of electrical matching rate are as follows: the channel 1-(I output electricity
The channel stream-Q exports electric current)/the channel Q output electric current.Electrical matching rate is higher, and electrical matching performance is better.As can be seen that using
When to flow to 5 with the 6 angle β of symmetry axis of symmetric circuit be 0 degree processing symmetric circuit of corrosive liquid, the electrical matching of the result counted
Performance is best, and undesirable symmetric circuit is minimum.Experiment is found, in specific implementation process, the range of above-mentioned angle β is 0
It spends to 30 degree, the electrical matching performance requirement of symmetric circuit can be substantially conformed to.
It is understood that above-mentioned control corrosion rate liquid stream to method can be used for this symmetric circuit of current mirror, institute
When to state current mirror be more times of amplifications, current source transistor and each current-copying transistor are in symmetrically.Due to current source transistor
It is parallel with the symmetry axis that each current-copying transistor is formed, thus can be simultaneously to three and its above transistor carries out
Corrosive liquid processing is not limited to carry out above-mentioned processing to two transistors simultaneously.
In one embodiment, be used in combination above-mentioned control corrosion rate liquid stream to scheme processing symmetric circuit grid oxic horizon
With the corner dimension between the beam direction and wafer crystal orientation in control laser thermal anneal.Above two method is without successively suitable
Sequence can be selected according to process requirement.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (9)
1. a kind of acquisition methods of the matched symmetric circuit of electrical property characterized by comprising to the wafer with symmetric circuit into
Row laser thermal anneal, wherein laser beam parallel wafer surface, and the angular range of the crystal orientation of the direction of laser beam and the wafer
It is 60 degree to 90 degree；
The symmetric circuit is located at the logic circuit area of wafer, and the wafer also has peripheral circuit region, the peripheral circuit region
Transistor gate oxidated layer thickness be greater than logic circuit area transistor thickness of grid oxide layer；The acquisition methods also wrap
It includes: in the grid oxic horizon of the grid oxic horizon and peripheral circuit region that form logic circuit area, first in logic circuit area and outside
The crystal column surface for enclosing circuit region forms the oxide layer of consistency of thickness, then covers the peripheral circuit region, and wet process removes logic electricity
The oxide layer in road area, in the wet process removal process, between the flow direction and the symmetry axis of the symmetric circuit of corrosive liquid
Angular range is 0 degree to 30 degree；Then, a thickness is formed in the crystal column surface of the logic circuit area and the peripheral circuit region
Spend impartial oxide layer.
2. the acquisition methods of the matched symmetric circuit of electrical property according to claim 1, which is characterized in that the laser beam
The angle of the crystal orientation of direction and the wafer is 90 degree.
3. the acquisition methods of the matched symmetric circuit of electrical property according to claim 1, which is characterized in that the wet process removal
In the process, the angle between the flow direction and the symmetry axis of the symmetric circuit of corrosive liquid is 0 degree.
4. the acquisition methods of the matched symmetric circuit of electrical property according to claim 1, which is characterized in that the symmetric circuit
For binary channels D/A converting circuit or current mirror.
5. the acquisition methods of the matched symmetric circuit of electrical property according to claim 4, which is characterized in that when the symmetrical electricity
When road is current mirror, the current mirror is more times of amplifications, is arranged between current source transistor and multiple current-copying transistors mute
Member.
6. a kind of acquisition methods of the matched symmetric circuit of electrical property, which is characterized in that the symmetric circuit is located at the logic of wafer
Circuit region, the wafer also have peripheral circuit region, and the transistor gate oxidated layer thickness of the peripheral circuit region is greater than logic
The thickness of grid oxide layer of the transistor of circuit region；The acquisition methods include: in the grid oxic horizon for forming logic circuit area
When with the grid oxic horizon of peripheral circuit region, consistency of thickness first is formed in the crystal column surface of logic circuit area and peripheral circuit region
Oxide layer, then covers the peripheral circuit region, and wet process removes the oxide layer of logic circuit area, the wet process removal process
In, the angular range between the flow direction and the symmetry axis of the symmetric circuit of corrosive liquid is 0 degree to 30 degree；Then, it is patrolled described
Volume circuit region and the crystal column surface of the peripheral circuit region form the oxide layer of a layer thickness equalization.
7. the acquisition methods of the matched symmetric circuit of electrical property according to claim 6, which is characterized in that the wet process removal
In the process, the angle between the flow direction and the symmetry axis of the symmetric circuit of corrosive liquid is 0 degree.
8. the acquisition methods of the matched symmetric circuit of electrical property according to claim 6 or 7, which is characterized in that described symmetrical
Circuit is binary channels D/A converting circuit or current mirror.
9. the acquisition methods of the matched symmetric circuit of electrical property according to claim 8, which is characterized in that when the symmetrical electricity
When road is current mirror, the current mirror is more times of amplifications.
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| CN102315108A (en) * | 2011-09-15 | 2012-01-11 | 清华大学 | Laser annealing method used for complex structure semiconductor device |
| JP2013074246A (en) * | 2011-09-29 | 2013-04-22 | Sumitomo Heavy Ind Ltd | Laser annealing device, laser annealing method, and stage |
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