CN104639141B - A kind of switching circuit and terminal with the circuit - Google Patents
A kind of switching circuit and terminal with the circuit Download PDFInfo
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- CN104639141B CN104639141B CN201510098023.5A CN201510098023A CN104639141B CN 104639141 B CN104639141 B CN 104639141B CN 201510098023 A CN201510098023 A CN 201510098023A CN 104639141 B CN104639141 B CN 104639141B
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Abstract
The invention discloses a kind of switching circuit and terminals with the circuit, wherein the switching circuit, including:First current potential holding circuit, switch key K1, delay circuit and the second current potential holding circuit;Described first current potential holding circuit one end is connected with the switch key K1 endpoints 1, and the other end is connected with the second current potential holding circuit;The switch key K1 endpoints 2 are connected with described delay circuit one end;The delay circuit other end is connected with the second current potential holding circuit other end.Technical scheme of the present invention realizes switching function by hardware switch circuit structure, coordinates without MCU, realizes that switching function additional input output pin, the MCU design costs of reduction save board design space to save MCU.
Description
Technical field
The present invention relates to power electronics field, more particularly to a kind of switching circuit and terminal with the circuit.
Background technology
With the continuous development of science and technology, more and more wearable smart electronics products appear in daily life and work as
In, change everybody daily life.Such as:Electronics bracelet in wearable smart electronics product, needs in the design process
Meet under the conditions of space layout as small as possible, realizes powerful function support.
In this way, being designed in inventor in wearable smart electronics product process, find at least exist in the prior art such as
Lower problem:
The power on/off function that existing wearable smart electronics product uses is substantially by controlling the general of chip MCU
Input/output (General Purpose Input Output, abbreviation GPIO) is realized, is achieved in that by primary booting, long
By shutdown.In this way, it is necessary to MCU configures additional input/output pin to realize, to increase the design cost of MCU, with
And additional design space.
Invention content
In view of the above problems, it is proposed that the present invention overcoming the above problem in order to provide one kind or solves at least partly
Problem is stated, the technical proposal of the invention is realized in this way:
On the one hand, the present invention provides a kind of switching circuits, including:First current potential holding circuit, switch key K1, delay
Circuit and the second current potential holding circuit;
Described first current potential holding circuit one end is connected with the switch key K1 endpoints 1, the other end and second electricity
Position holding circuit is connected;
The switch key K1 endpoints 2 are connected with described delay circuit one end;
The delay circuit other end is connected with the second current potential holding circuit other end.
Preferably, the first current potential holding circuit includes:First switch pipe Q1, second switch pipe Q2, first resistor R1,
Second resistance R2, the 6th resistance R6;
The first switch pipe Q1 emitters are connected with the one end the first resistor R1, the first switch pipe Q1 collectors
Respectively with the one end the 6th resistance R6, the second switch pipe Q2 base stages be connected;The first switch pipe Q1 base stages with it is described
Second current potential holding circuit is connected;
Another termination powers of first resistor R1;
The 6th resistance R6 other ends ground connection;
The second switch pipe Q2 collectors respectively with the one end the second resistance R2,1 phase of switch key K1 endpoints
Even;The second switch pipe Q2 emitters ground connection;
Another termination powers of second resistance R2.
Preferably, the delay circuit includes:First capacitance C1 and 3rd resistor R3;
Respectively with the switch key K1 endpoints 2, the one end the resistance R3 is connected for described one end first capacitance C1;Described one
The capacitance C1 other ends are grounded;
Another termination the second current potential holding circuits of 3rd resistor R3.
Preferably, the second current potential holding circuit includes:4th resistance R4, the 5th resistance R5, the 7th resistance R7, the 8th
Resistance R8, phase inverter U1, third switching tube Q3, the 4th switching tube Q4, the 5th switching tube Q5;
For the 4th switching tube Q4 base stages respectively with the one end the 3rd resistor R3, the one end the 7th resistance R7 is described
Third switching tube Q3 collectors are connected;The 4th switching tube Q4 collectors respectively with the one end the 4th resistance R4, described
Five switching tube Q5 base stages are connected;The 4th switching tube Q4 emitters ground connection;
The 7th resistance R7 other ends ground connection;
Another termination powers of the 4th resistance R4;
The 5th switching tube Q5 collectors are respectively with the one end the 5th resistance R5, and control exports and the phase inverter
U1 positive terminals are connected;The 5th switching tube Q5 emitters ground connection;
Another termination powers of the 5th resistance R5;
The phase inverter U1 negative pole ends respectively with the first switch pipe Q1 base stages, the third switching tube Q3 base stage phases
Even;
The third switching tube Q3 emitters are connected with the one end the 8th resistance R8;
Another termination powers of the 8th resistance R8.
Preferably, the 6th resistance R6 and the 7th resistance R7 is pull down resistor.
On the other hand, the present invention provides a kind of terminals, including:Any one switching circuit as described above.
Wearable electricity has can be realized without MCU cooperations in the switching circuit that technical scheme of the present invention is built by hardware
The switching function of sub- product, to save MCU realize switching function additional input output pin, the MCU design costs of reduction,
Save board design space.
Description of the drawings
Fig. 1 is a kind of switching circuit structure schematic diagram provided in an embodiment of the present invention;
Fig. 2 is a kind of switching circuit figure provided in an embodiment of the present invention;
Fig. 3 is a kind of terminal structure schematic diagram provided in an embodiment of the present invention.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
If Fig. 1 is to show a kind of switching circuit provided in an embodiment of the present invention;The circuit includes:First current potential keeps electricity
Road, switch key K1, delay circuit and the second current potential holding circuit;
Described first current potential holding circuit one end is connected with the switch key K1 endpoints 1, the other end and second electricity
Position holding circuit is connected;
The switch key K1 endpoints 2 are connected with described delay circuit one end;
The delay circuit other end is connected with the second current potential holding circuit other end.
Based on above example, as shown in Fig. 2, being a kind of switching circuit provided in an embodiment of the present invention;The circuit includes:
First current potential holding circuit, switch key K1, delay circuit and the second current potential holding circuit;
The first current potential holding circuit includes:First switch pipe Q1, second switch pipe Q2, first resistor R1, the second electricity
Hinder R2, the 6th resistance R6;
The first switch pipe Q1 emitters are connected with the one end the first resistor R1, the first switch pipe Q1 collectors
Respectively with the one end the 6th resistance R6, the second switch pipe Q2 base stages be connected;The first switch pipe Q1 base stages with it is described
Second current potential holding circuit is connected;
Another termination powers of first resistor R1;
The 6th resistance R6 other ends ground connection;
The second switch pipe Q2 collectors respectively with the one end the second resistance R2,1 phase of switch key K1 endpoints
Even;The second switch pipe Q2 emitters ground connection;
Another termination powers of second resistance R2.
The delay circuit includes:First capacitance C1 and 3rd resistor R3;
Respectively with the switch key K1 endpoints 2, the one end the resistance R3 is connected for described one end first capacitance C1;Described one
The capacitance C1 other ends are grounded;
Another termination the second current potential holding circuits of 3rd resistor R3.
The second current potential holding circuit includes:4th resistance R4, the 5th resistance R5, the 7th resistance R7, the 8th resistance R8,
Phase inverter U1, third switching tube Q3, the 4th switching tube Q4, the 5th switching tube Q5;
For the 4th switching tube Q4 base stages respectively with the one end the 3rd resistor R3, the one end the 7th resistance R7 is described
Third switching tube Q3 collectors are connected;The 4th switching tube Q4 collectors respectively with the one end the 4th resistance R4, described
Five switching tube Q5 base stages are connected;The 4th switching tube Q4 emitters ground connection;
The 7th resistance R7 other ends ground connection;
Another termination powers of the 4th resistance R4;
The 5th switching tube Q5 collectors are respectively with the one end the 5th resistance R5, and control exports and the phase inverter
U1 positive terminals are connected;The 5th switching tube Q5 emitters ground connection;
Another termination powers of the 5th resistance R5;
The phase inverter U1 negative pole ends respectively with the first switch pipe Q1 base stages, the third switching tube Q3 base stage phases
Even;
The third switching tube Q3 emitters are connected with the one end the 8th resistance R8;
Another termination powers of the 8th resistance R8.
Preferably, the 6th resistance R6 and the 7th resistance R7 is pull down resistor.
It is PNP triode with the switching tube Q1, Q3 that divide into the present embodiment;Q2, Q4, Q5 are NPN triode;First capacitance
C1 forms delay circuit with 3rd resistor R3;The first capacitance C1 is mainly energy storage effect;Resistance R6, R7 are pull down resistors,
Original state is provided;The realization principle of the present embodiment is described in detail below:
Original state, switch key K1 are off, and switching tube Q4 base stages are due to the 7th resistance R7 drop-downs
Low level, the switching tube Q4 current collections extremely high level, the switching tube Q5 base stages are high level, the switching tube Q5 conductings,
Control output is low level.
The switching tube Q3 base stages are high level after the phase inverter U1 is reversed, the switching tube Q3 cut-offs.
The switching tube Q1 base stages are switching tube Q1 cut-offs described in high level, and the switching tube Q2 base stages are due to the described 6th
Resistance R6 drop-downs are low level.Since the second resistance R2 is pulled upward to high level.The switching tube Q2 collectors output is height
Level.
Switch key K1 endpoints 1 are high level in this way, and endpoint 2 is low level
It is unclamped after pressing switch key K1 for the first time, endpoint 2 and 1 transient switching of endpoint of switch key.Endpoint 2 is high electricity
Flat, then the first capacitance C1 chargings provide the switching tube Q4 base stage high level after 3rd resistor R3 delays,
The switching tube Q4 conductings, the switching tube Q4 collectors export switching tube Q5 cut-offs described in low level, and collector output is height
Level, control output are also high level.
Meanwhile phase inverter U1 reversely exports low level afterwards, the switching tube Q3 conductings, the switching tube Q3 emits extremely high
Level.The high level of the switching tube Q4 base stages is maintained in this way.
The switching tube Q1 base stages are low level simultaneously, and the switching tube Q1 conductings, the switching tube Q2 base stages are high electricity
Flat, the switching tube Q2 conductings, the switching tube Q2 collectors output is low level, and the switch key K1 endpoints 1 are low electricity
It is flat.
It is unclamped after pressing switch key K1 again, endpoint 2 and 1 transient switching of endpoint of switch key K1.Due to for the first time
Button aft terminal 1 is low level, and endpoint 2 becomes low level, then the 3rd resistor R3 is passed through in the first capacitance C1 electric discharges
It is low level to draw the switching tube Q4 base stages after delay, the switching tube Q4 cut-offs, and the switching tube Q4 collectors output is high
Level.The switching tube Q5 conductings, collector output are low level, and control output is also low level.
Meanwhile the phase inverter U1 reversely exports high level, the switching tube Q3 cut-offs, the switching tube Q3 emitters afterwards
For low level.In this way due to the drop-down of the 7th resistance R7, the low level of the switching tube Q4 base stages is maintained.
The switching tube Q1 base stages are high level simultaneously, and the switching tube Q1 cut-offs, the switching tube Q2 base stages are low electricity
Flat, the switching tube Q2 cut-offs, the switching tube Q2 collectors output is high level, and switch key K1 endpoints 2 are low level.
By above-mentioned principle analysis, pushing button control output state successively can alternately be switched on for low and high level to realize
The function of shutdown.
It should be noted that the switching tube is not limited solely to triode, can also be metal-oxide-semiconductor etc., other may be implemented
The device of switching function.
As shown in figure 3, being a kind of terminal provided in an embodiment of the present invention;The terminal includes:Any one is opened as described above
Powered-down road.
It should be noted that switching circuit provided in an embodiment of the present invention is built using a kind of pure hardware, it is not necessarily to MCU
The switching circuit of cooperation can not only save the GPIO quantity of MCU, reduce the pin of MCU as far as possible, in this way to reduce
The cost of MCU, while also saving the space of product.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the scope of the present invention.It is all
Any modification, equivalent replacement, improvement and so within the spirit and principles in the present invention, are all contained in protection scope of the present invention
It is interior.
Claims (6)
1. a kind of switching circuit, which is characterized in that including:First current potential holding circuit, switch key K1, delay circuit and second
Current potential holding circuit;
Described first current potential holding circuit one end is connected with the switch key K1 endpoints 1, and the other end is protected with second current potential
Circuit is held to be connected;
The switch key K1 endpoints 2 are connected with described delay circuit one end;
The delay circuit other end is connected with the second current potential holding circuit other end;
The second current potential holding circuit includes:4th resistance R4, the 5th resistance R5, the 7th resistance R7, the 8th resistance R8, reverse phase
Device U1, third switching tube Q3, the 4th switching tube Q4, the 5th switching tube Q5;
The base stage of the 4th switching tube Q4 is connect with the delay circuit;The 4th switching tube Q4 base stages are respectively with described
Seven one end resistance R7, the third switching tube Q3 collectors are connected;The 4th switching tube Q4 collectors are respectively with the described 4th
The one end resistance R4, the 5th switching tube Q5 base stages are connected;The 4th switching tube Q4 emitters ground connection;
The 7th resistance R7 other ends ground connection;
Another termination powers of the 4th resistance R4;
The 5th switching tube Q5 collectors are respectively with the one end the 5th resistance R5, and control output and the phase inverter U1 are just
It is extreme to be connected;The 5th switching tube Q5 emitters ground connection;
Another termination powers of the 5th resistance R5;
The phase inverter U1 negative pole ends are connect with the first current potential holding circuit;The phase inverter U1 negative pole ends and the third
Switching tube Q3 base stages are connected;
The third switching tube Q3 emitters are connected with the one end the 8th resistance R8;
Another termination powers of the 8th resistance R8;
The delay circuit includes:First capacitance C1 and 3rd resistor R3;
Respectively with the switch key K1 endpoints 2, the one end the resistance R3 is connected for described one end first capacitance C1;One capacitance
The C1 other ends are grounded;
Another termination the second current potential holding circuits of 3rd resistor R3.
2. switching circuit according to claim 1, which is characterized in that the first current potential holding circuit includes:First opens
Close pipe Q1, second switch pipe Q2, first resistor R1, second resistance R2, the 6th resistance R6;
The first switch pipe Q1 emitters are connected with the one end the first resistor R1, the first switch pipe Q1 collectors difference
With the one end the 6th resistance R6, the second switch pipe Q2 base stages are connected;The first switch pipe Q1 base stages and described second
Current potential holding circuit is connected;
Another termination powers of first resistor R1;
The 6th resistance R6 other ends ground connection;
The second switch pipe Q2 collectors respectively with the one end the second resistance R2, the switch key K1 endpoints 1 be connected;Institute
State second switch pipe Q2 emitters ground connection;
Another termination powers of second resistance R2.
3. switching circuit according to claim 2, which is characterized in that the 6th resistance R6 and the 7th resistance R7 are
Pull down resistor.
4. a kind of terminal, which is characterized in that including:Switching circuit;The switching circuit includes:First current potential holding circuit, is opened
Close button K1, delay circuit and the second current potential holding circuit;
Described first current potential holding circuit one end is connected with the switch key K1 endpoints 1, and the other end is protected with second current potential
Circuit is held to be connected;
The switch key K1 endpoints 2 are connected with described delay circuit one end;
The delay circuit other end is connected with the second current potential holding circuit other end;
The second current potential holding circuit includes:4th resistance R4, the 5th resistance R5, the 7th resistance R7, the 8th resistance R8, reverse phase
Device U1, third switching tube Q3, the 4th switching tube Q4, the 5th switching tube Q5;
The base stage of the 4th switching tube Q4 is connect with the delay circuit;The 4th switching tube Q4 base stages are respectively with described
Seven one end resistance R7, the third switching tube Q3 collectors are connected;The 4th switching tube Q4 collectors are respectively with the described 4th
The one end resistance R4, the 5th switching tube Q5 base stages are connected;The 4th switching tube Q4 emitters ground connection;
The 7th resistance R7 other ends ground connection;
Another termination powers of the 4th resistance R4;
The 5th switching tube Q5 collectors are respectively with the one end the 5th resistance R5, and control output and the phase inverter U1 are just
It is extreme to be connected;The 5th switching tube Q5 emitters ground connection;
Another termination powers of the 5th resistance R5;
The phase inverter U1 negative pole ends are connect with the first current potential holding circuit;The phase inverter U1 negative pole ends and the third
Switching tube Q3 base stages are connected;
The third switching tube Q3 emitters are connected with the one end the 8th resistance R8;
Another termination powers of the 8th resistance R8;
The delay circuit includes:First capacitance C1 and 3rd resistor R3;
Respectively with the switch key K1 endpoints 2, the one end the resistance R3 is connected for described one end first capacitance C1;One capacitance
The C1 other ends are grounded;
Another termination the second current potential holding circuits of 3rd resistor R3.
5. terminal according to claim 4, which is characterized in that the first current potential holding circuit includes:First switch pipe
Q1, second switch pipe Q2, first resistor R1, second resistance R2, the 6th resistance R6;
The first switch pipe Q1 emitters are connected with the one end the first resistor R1, the first switch pipe Q1 collectors difference
With the one end the 6th resistance R6, the second switch pipe Q2 base stages are connected;The first switch pipe Q1 base stages and described second
Current potential holding circuit is connected;
Another termination powers of first resistor R1;
The 6th resistance R6 other ends ground connection;
The second switch pipe Q2 collectors respectively with the one end the second resistance R2, the switch key K1 endpoints 1 be connected;Institute
State second switch pipe Q2 emitters ground connection;
Another termination powers of second resistance R2.
6. terminal according to claim 5, which is characterized in that the 6th resistance R6 and the 7th resistance R7 is drop-down
Resistance.
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CN201510098023.5A CN104639141B (en) | 2015-03-05 | 2015-03-05 | A kind of switching circuit and terminal with the circuit |
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CN201510098023.5A CN104639141B (en) | 2015-03-05 | 2015-03-05 | A kind of switching circuit and terminal with the circuit |
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CN104639141A CN104639141A (en) | 2015-05-20 |
CN104639141B true CN104639141B (en) | 2018-07-31 |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08223017A (en) * | 1995-02-15 | 1996-08-30 | Nippondenso Co Ltd | Power-on and power-off reset device |
CN102332898A (en) * | 2011-08-17 | 2012-01-25 | 深圳市英唐数码电器有限公司 | Switching circuit with zero standby power consumption |
CN102508536A (en) * | 2011-10-28 | 2012-06-20 | 惠而邦电子衡器(昆山)有限公司 | One-button startup and shutdown circuit in embedded system and control method thereof |
CN202551001U (en) * | 2012-04-26 | 2012-11-21 | 深圳市禹欣鑫电子有限公司 | Electronic switching circuit |
CN102929161A (en) * | 2012-10-18 | 2013-02-13 | 台衡精密测控(昆山)股份有限公司 | Full hardware startup and shutdown circuit |
CN204517782U (en) * | 2015-03-05 | 2015-07-29 | 青岛歌尔声学科技有限公司 | A kind of switching circuit and there is the terminal of this circuit |
-
2015
- 2015-03-05 CN CN201510098023.5A patent/CN104639141B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08223017A (en) * | 1995-02-15 | 1996-08-30 | Nippondenso Co Ltd | Power-on and power-off reset device |
CN102332898A (en) * | 2011-08-17 | 2012-01-25 | 深圳市英唐数码电器有限公司 | Switching circuit with zero standby power consumption |
CN102508536A (en) * | 2011-10-28 | 2012-06-20 | 惠而邦电子衡器(昆山)有限公司 | One-button startup and shutdown circuit in embedded system and control method thereof |
CN202551001U (en) * | 2012-04-26 | 2012-11-21 | 深圳市禹欣鑫电子有限公司 | Electronic switching circuit |
CN102929161A (en) * | 2012-10-18 | 2013-02-13 | 台衡精密测控(昆山)股份有限公司 | Full hardware startup and shutdown circuit |
CN204517782U (en) * | 2015-03-05 | 2015-07-29 | 青岛歌尔声学科技有限公司 | A kind of switching circuit and there is the terminal of this circuit |
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CN104639141A (en) | 2015-05-20 |
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