CN208015698U

CN208015698U - It is a kind of to realize the clock switch circuit steadily switched

Info

Publication number: CN208015698U
Application number: CN201820232482.7U
Authority: CN
Inventors: 孙永明
Original assignee: Changsha Tak Yang Microelectronics Co Ltd
Current assignee: Changsha Tak Yang Microelectronics Co Ltd
Priority date: 2018-02-09
Filing date: 2018-02-09
Publication date: 2018-10-26
Anticipated expiration: 2028-02-09

Abstract

The utility model discloses a kind of clock switch circuits realized and steadily switched, including clock signal clk-SEL, clock signal clk -0, clock signal clk -1, clock signal clk-O and door F1 and door F2 and door F3 and door F4 or door F5 and door F6 and door F7 and door F8, trigger T1, trigger T2, trigger T3 and trigger T4.The beneficial effects of the utility model are：The utility model provides a kind of clock switch circuit that the realization of innovation steadily switches to realize the steady switching for being switched to another out of phase different frequency clock from a clock, to prevent the generation of clock bur, and then ensure the stability of clock switching, and then the stability of entire flogic system is improved, and then reach the requirement of steady output signal.

Description

It is a kind of to realize the clock switch circuit steadily switched

Technical field

The utility model is related to clock switch circuit fields, it particularly relates to which a kind of realizing that the clock steadily switched is cut Change circuit.

Background technology

In integrated circuit design, clock switch circuit is a circuit often used, and is switched to from a clock The clock of another out of phase different frequency, common circuit is exactly the MUX units of an alternative, as shown in figure 3, generally Clock switch circuit structure, the problem of this circuit is to will produce unnecessary clock bur, and jagged clock is usual Serious injury can be generated to entire flogic system, as shown in figure 4, issuable clock bur schematic diagram.

For the problems in the relevant technologies, currently no effective solution has been proposed.

Utility model content

For the problems in the relevant technologies, the utility model proposes a kind of clock switch circuit realized and steadily switched, with Overcome the above-mentioned technical problem present in existing the relevant technologies.

What the technical solution of the utility model was realized in：

It is a kind of to realize the clock switch circuit steadily switched, including clock signal clk-SEL, clock signal clk -0, clock Signal CLK-1, clock signal clk-O and door F1 and door F2 and door F3 and door F4 or door F5 and door F6 and door F7 and door F8, trigger T1, trigger T2, trigger T3 and trigger T4, wherein the clock signal clk-SEL respectively with it is described with The input terminal of door F1 and it is described connect with the second input terminal of door F6, the output end and described and door F2 first with door F1 Input terminal connects, described to be connect with the second input terminal of door F2 with the output end QN4 of the trigger T4, described defeated with door F2 Outlet is connect with the input terminal D1 of the trigger T1, the input terminal with the trigger T1 respectively of the clock signal clk -0 CLK1, it is described with the input terminal of door F3 and it is described connect with the second input terminal of door F4, the output end Q1 of the trigger T1 with The input terminal D2 connections of the trigger T2, it is described to be connect with the output end of door F3 with the input terminal CLK2 of the trigger T2, The output end Q2 of the trigger T2 is connect with the first input end with door F4, the output end QN2 of the trigger T2 with The first input end with door F6 is connect, described to be connect with the output end of door F4 with described or door F5 first input end, institute It states or the output end of door F5 is connect with the clock signal clk-O, the output end with door F6 is defeated with the trigger T3's Enter D3 is held to connect, the clock signal clk -1 respectively with the input terminal CLK3 of the trigger T3, the input terminal with door F7 And it is described connect with the second input terminal of door F8, the input terminal D4 of the output end Q3 of the trigger T3 and the trigger T4 connect Connect, it is described to be connect with the output end of door F7 with the input terminal CLK4 of the trigger T4, the output end Q4 of the trigger T4 with The first input end with door F8 is connect, described to be connect with the output end of door F8 with described or door F5 the second input terminal.

Further, the output end Q4 of the output end Q2 of the trigger T2 and trigger T4 exports clock respectively Signal CLK-EN.

Further, the trigger T1 and the trigger T2, the trigger T3 and the trigger T4 are T-type Trigger.

The beneficial effects of the utility model are：The utility model provides a kind of clock switch circuit realized and steadily switched The steady switching that another out of phase different frequency clock is switched to from a clock is realized, to prevent clock bur It generates, and then ensures the stability of clock switching, and then improve the stability of entire flogic system, and then reach steady output letter Number requirement.

Description of the drawings

In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only the utility model Some embodiments for those of ordinary skill in the art without creative efforts, can also be according to this A little attached drawings obtain other attached drawings.

Fig. 1 is a kind of schematic diagram for realizing the clock switch circuit steadily switched according to the utility model embodiment；

Fig. 2 is a kind of waveform signal for realizing the clock switch circuit steadily switched according to the utility model embodiment Figure；

Fig. 3 is general clock switch circuit structural schematic diagram；

Fig. 4 is general clock switch circuit structural modes schematic diagram.

Specific implementation mode

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, the every other embodiment that those of ordinary skill in the art are obtained all belongs to In the range of the utility model protection.

Embodiment according to the present utility model provides a kind of clock switch circuit realized and steadily switched.

As shown in Figs. 1-2, the clock switch circuit steadily switched according to the realization of the utility model embodiment, including clock Signal CLK-SEL, clock signal clk -0, clock signal clk -1, clock signal clk-O, with door F1, with door F2, with door F3, with Door F4 or door F5 and door F6 and door F7 and door F8, trigger T1, trigger T2, trigger T3 and trigger T4, wherein institute State clock signal clk-SEL respectively with it is described with the input terminal of door F1 and it is described connect with the second input terminal of door F6, it is described with The output end of door F1 is connect with the first input end with door F2, second input terminal with door F2 and the trigger T4 Output end QN4 connections, described to be connect with the output end of door F2 with the input terminal D1 of the trigger T1, the clock signal CLK-0 is inputted with the input terminal CLK1 of the trigger T1, described and door F3 the input terminal and described and door F4 second respectively End connection, the output end Q1 of the trigger T1 are connect with the input terminal D2 of the trigger T2, the output end with door F3 It is connect with the input terminal CLK2 of the trigger T2, the output end Q2 of the trigger T2 and the first input end with door F4 Connection, the output end QN2 of the trigger T2 connect with the first input end with door F6, described and door F4 output end and Described or door F5 first input end connection, described or door F5 output end are connect with the clock signal clk-O, described and door The output end of F6 is connect with the input terminal D3 of the trigger T3, and the clock signal clk -1 is respectively with the trigger T3's Input terminal CLK3, it is described with the input terminal of door F7 and it is described connect with the second input terminal of door F8, the output of the trigger T3 End Q3 is connect with the input terminal D4 of the trigger T4, the input terminal CLK4 with the output end and the trigger T4 of door F7 Connection, the output end Q4 of the trigger T4 connect with the first input end with door F8, described and door F8 output end and Described or door F5 the second input terminal connection.

In one embodiment, the output end Q4 of the output end Q2 of the trigger T2 and trigger T4 is defeated respectively Go out clock signal clk-EN.

In one embodiment, the trigger T1 and the trigger T2, the trigger T3 and the trigger T4 It is toggle flip-flop.

In conclusion by means of the above-mentioned technical proposal of the utility model, the utility model provides a kind of realize steadily The clock switch circuit of switching is switched to the steady switching of another out of phase different frequency clock to realize from a clock, To prevent the generation of clock bur, and then ensure the stability of clock switching, and then improve the stability of entire flogic system, And then reach the requirement of steady output signal.

The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this Within the spirit and principle of utility model, any modification, equivalent replacement, improvement and so on should be included in the utility model Protection domain within.

Claims

1. a kind of realizing the clock switch circuit steadily switched, which is characterized in that including clock signal clk-SEL, clock signal CLK-0, clock signal clk -1, clock signal clk-O and door F1 and door F2 and door F3 and door F4 or door F5 and door F6, With door F7 and door F8, trigger T1, trigger T2, trigger T3 and trigger T4, wherein the clock signal clk-SEL points Not with it is described with the input terminal of door F1 and it is described connect with the second input terminal of door F6, the output end with door F1 with it is described with The first input end connection of door F2, it is described to be connect with the second input terminal of door F2 with the output end QN4 of the trigger T4, it is described Connect with the output end of door F2 with the input terminal D1 of the trigger T1, the clock signal clk -0 respectively with the trigger The input terminal CLK1 of T1, it is described with the input terminal of door F3 and it is described connect with the second input terminal of door F4, the trigger T1's Output end Q1 is connect with the input terminal D2 of the trigger T2, the input terminal with the output end and the trigger T2 of door F3 CLK2 connections, the output end Q2 of the trigger T2 are connect with the first input end with door F4, and the trigger T2's is defeated Outlet QN2 is connect with the first input end with door F6, and the output end with door F4 is inputted with described or door F5 first End connection, described or door F5 output end are connect with the clock signal clk-O, the output end with door F6 and the triggering The input terminal D3 connections of device T3, the clock signal clk -1 respectively with the input terminal CLK3 of the trigger T3, described with door F7 Input terminal and it is described connect with the second input terminal of door F8, the output end Q3 of the trigger T3 is defeated with the trigger T4's Enter D4 is held to connect, described to connect with the output end of door F7 with the input terminal CLK4 of the trigger T4, the trigger T4's is defeated Outlet Q4 is connect with the first input end with door F8, the output end with door F8 and described or door F5 the second input terminal Connection.

2. a kind of the clock switch circuit steadily switched is realized according to claim 1, which is characterized in that the trigger The output end Q4 of the output end Q2 of the T2 and trigger T4 exports clock signal clk-EN respectively.

3. a kind of the clock switch circuit steadily switched is realized according to claim 1, which is characterized in that the trigger T1 and the trigger T2, the trigger T3 and the trigger T4 are toggle flip-flop.