CN104579366B - High speed QC-LDPC encoder in WPAN based on three class pipeline - Google Patents

Abstract

The present invention provides the high speed QC-LDPC encoder in a kind of WPAN based on three class pipeline, the encoder include after the multiplier of 1 sparse matrix and vector, 1 I type to after iterative circuit and 1 II type to iterative circuit.The multiplier of sparse matrix and vector realizes the multiplying of sparse matrix and vector, to interative computation after all realizing after I type and II type to iterative circuit.Entire cataloged procedure is divided into 3 level production lines.1/2 code rate high speed QC-LDPC encoder has many advantages, such as that structure is simple, at low cost, handling capacity is big in WPAN system provided by the invention.

Description

High speed QC-LDPC encoder in WPAN based on three class pipeline

Technical field

The present invention relates to field of channel coding, in particular to the high speed QC- based on three class pipeline in a kind of WPAN system LDPC encoder.

Background technique

Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The life of QC-LDPC code All it is the array being made of circular matrix at matrix G and check matrix H, has the characteristics that stages cycle, therefore referred to as QC-LDPC Code.The first trip of circular matrix is footline ring shift right 1 as a result, remaining each row is all the knot of its lastrow ring shift right 1 Fruit, therefore, circular matrix are characterized by its first trip completely.In general, the first trip of circular matrix is referred to as its generator polynomial.

Communication system generallys use the QC-LDPC code of system form, and the left-half of generator matrix G is a unit square Battle array, right half part is by e × c b × b rank circular matrix G_i,jThe array that (0≤i < e, e≤j < t, t=e+c) is constituted, following institute Show:

Wherein, I is b × b rank unit matrix, and 0 is b × b rank full null matrix.Continuous b row and the b column of G are known respectively as block Capable and block column.By formula (1) it is found that G has e block row and t block column.WPAN standard uses a kind of QC-LDPC code of code rate η=1/2, For the code, t=32, e=16, c=16, b=21.

The existing solution of 1/2 code rate QC-LDPC encoder is added based on 16 I type shift registers in WPAN standard The serial encoder of accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) circuit.By 16 The serial encoder that SRAA-I circuit is constituted completes coding within 336 clock cycle.672 registers of program needs, 336 two inputs and door and 336 two input XOR gates, it is also necessary to the generator polynomial of 5376 bit ROM storage circular matrix. There are two disadvantages for the program: first is that needing a large amount of memories, leading to circuit cost height；Second is that serial input information bit, coding Speed is slow.

Summary of the invention

The existing implementation of 1/2 code rate QC-LDPC encoder is lacked there are at high cost, coding rate is slow in WPAN system Point, for these technical problems, the present invention provides a kind of high speed QC-LDPC encoder based on three class pipeline.

As shown in Fig. 2, the high speed QC-LDPC encoder in WPAN system based on three class pipeline is mainly made of 3 parts: After the multiplier of sparse matrix and vector, I type to after iterative circuit and II type to iterative circuit.3 steps of cataloged procedure point are completed: the 1 step calculates vector f and w using the multiplier of sparse matrix and vector；Step 2 calculates vector q to iterative circuit using after I type And x, so as to find out vector p is partially verified_x=x；Step 3 calculates vector y to iterative circuit using after II type, and y and vector q are different Or obtain part verification vector p_y, to obtain verification vector p=(p_x,p_y)。

1/2 code rate high speed QC-LDPC coder structure is simple in WPAN system provided by the invention, is not necessarily to memory, energy Coding rate is significantly improved, to reduce cost, improves handling capacity.

It can be further understood by following detailed description and accompanying drawings about advantage of the invention and method.

Detailed description of the invention

Fig. 1 is the structural schematic diagram of near lower triangular check matrix after ranks exchange；

Fig. 2 is the QC-LDPC cataloged procedure based on three class pipeline；

Fig. 3 is the multiplier of sparse matrix and vector；

Fig. 4 gives the connection relationship of each multi input XOR gate and register in the multiplier of sparse matrix and vector；

Fig. 5 is after I type to iterative circuit；

Fig. 6 gives block position and its ring shift right digit in matrix Q where nonzero circle matrix；

Fig. 7 is after II type to iterative circuit；

Fig. 8 gives block position and its ring shift right digit in matrix Y where nonzero circle matrix；

Hardware resource needed for Fig. 9 summarizes each coding step of encoder and entire cataloged procedure and processing time.

Specific embodiment

Presently preferred embodiments of the present invention is elaborated with reference to the accompanying drawing, so that advantages and features of the invention can be more It is easy to be readily appreciated by one skilled in the art, apparent is explicitly defined to be made to protection scope of the present invention.

The row weight and column heavy phase of circular matrix are same, are denoted as w.If w=0, which is full null matrix.If W=1, then the circular matrix is replaceable, referred to as permutation matrix, it can be by several positions of unit matrix I ring shift right It obtains.The check matrix H of QC-LDPC code is by c × t b × b rank circular matrix H_j,k(1≤j≤c, 1≤k≤t, t=e+c) The following array constituted:

Under normal conditions, any circular matrix in check matrix H is either full null matrix (w=0) or is displacement square Battle array (w=1).Enable circular matrix H_j,kFirst trip g_j,k=(g_j,k,1,g_j,k,2,…,g_j,k,b) it is its generator polynomial, wherein g_j,k,m =0 or 1 (1≤m≤b).Because H is sparse, g_j,kOnly 1 ' 1 ', even without ' 1 '.

For the QC-LDPC code of 1/2 code rate in WPAN system, corresponding preceding 16 pieces of column of H are information vector a, latter 16 pieces Arranging corresponding is verification vector p.With b bit for one section, information vector a is divided into 16 sections, i.e. a=(a₁,a₂,…,a₁₆)；School It tests vector p and is divided into 16 sections, i.e. p=(p₁,p₂,…,p₁₆)。

Capable exchange and column swap operation are carried out to check matrix H, are converted near lower triangular shape H_ALT, such as Fig. 1 institute Show.The process of ranks exchange is as follows: step 1, carries out block column exchange, and preceding 18 pieces of column remain stationary, rear 14 pieces of column rearrangement, it Respectively correspond original the 31st, 30,25,28,19,20,29,32,23,22,27,26,24,21 pieces column；Step 2, to all The exchange of block traveling row block row, they respectively correspond original the 5th, 7,14,16,4,1,6,8,11,10,13,15,12,9,3,2 pieces Row；Step 3, by 16 pieces of rows permutation matrix difference ring shift right 7,10,10,4,9,5,19,17,4,4,5,19,12,4, 20,7.

In Fig. 1, the unit of all matrixes is all b=21 bit rather than 1 bit.A is followed by 14 × 16 b × b ranks Ring matrix is constituted, and B is made of 14 × 2 b × b rank circular matrixes, and T is made of 14 × 14 b × b rank circular matrixes, and C is It is made of 2 × 16 b × b rank circular matrixes, D is made of 2 × 2 b × b rank circular matrixes, and E is by 2 × 14 b × b ranks Circular matrix is constituted.T is lower triangular matrix, and u=2 reflects check matrix H_ALTWith the degree of closeness of lower triangular matrix.In Fig. 1 In, matrix A and C corresponding informance vector a, matrix B and the corresponding a part of D verify vector p_x=(p₁,p₂), matrix T and E are then corresponded to Remaining verification vector p_y=(p₃,p₄,…,p₁₆).P=(p_x,p_y).Above-mentioned matrix and vector meet following relationship:

p_x ^Τ=Φ (ET^-1Aa^Τ+Ca^Τ) (3)

p_y ^Τ=T^-1(Aa^Τ+Bp_x ^Τ) (4)

Wherein, Φ=(ET^-1B+D)^-1, subscript^ΤWith^-1Respectively indicate transposition and inverse.It is well known that circular matrix it is inverse, multiply Product and be still circular matrix.Therefore, Φ is also the array being made of circular matrix.

When Φ is equal to unit matrix, i.e. Φ=I, formula (3) can be reduced to p_x ^Τ=ET^-1Aa^Τ+Ca^Τ.Enable f^T=Aa^T, q^T= T^–1f^T, w^T=Ca^T, x^T=Eq^T+w^T, p_x ^T=x^T, y^T=T^–1Bp_x ^TAnd p_y ^T=q^T+y^T.Vector f and w can be calculated by following formula:

Wherein,

q^T=T^–1f^TAnd x^T=Eq^T+w^TIt may make up following matrix equality:

Wherein,

Once p is calculated_x, y^T=T^–1Bp_x ^TIt can be rewritten as:

[B T][p_x y]^Τ=Y [p_x y]^Τ=0 (9)

Wherein,

Y=[B T] (10)

Because Q and Y are lower triangular matrix as T, the y in [q x] and formula (9) in formula (7) be can be used The calculation of backward iteration.

F is related to the multiplication of sparse matrix and vector, and Q and Y be related to after to iterative calculation.From the above discussion, it can provide A kind of QC-LDPC cataloged procedure based on three class pipeline, as shown in Figure 2.

Enable f=(f₁,f₂,…,f₁₄) and w=(f₁₅,f₁₆), then [f w]=(f₁,f₂,…,f₁₆).By formula (5) it is found that f_j It is the jth block row and a of matrix F^TProduct, i.e.,

Wherein, 1≤i≤16,1≤j≤16.f_jThe n-th bit f_j,n(1≤n≤b) is

Wherein, subscript^rs(n–1)With^ls(n–1)Respectively indicate ring shift right n -1 and ring shift left n -1.Since any circulation Matrix generator polynomial g_j,iOnly a small amount of ' 1 ' even complete zero, then the inner product in formula (12) can be by posting ring shift left The tap of storage is summed to realize, the multiplier of sparse matrix as shown in Figure 3 and vector.The multiplier of sparse matrix and vector By 32 b bit register R_1,1,R_1,2,…,R_1,32With 16 multi input XOR gate X_1,1,X_1,2,…,X_1,16Composition.Register R_1,1,R_1,2,…,R_1,16For loading and ring shift left message segment a₁,a₂,…,a₁₆, register R_1,17,R_1,18,…,R_1,32For Store the array section f of [f w]₁,f₂,…,f₁₆.All circular matrixes that partially connected in Fig. 3 depends in matrix F generate more Item formula.If g_j,i,m=1 (1≤m≤b), then message segment a_iM bit be connected to XOR gate X_1,j.Therefore, register R_1,i All taps depend on the nonzero element positions of all circular matrix generator polynomials in i-th piece of matrix F column, and it is how defeated Enter XOR gate X_1,jInput depend on all circular matrix generator polynomials in matrix F jth block row nonzero element institute it is in place It sets.Fig. 4 gives the connection relationship of each multi input XOR gate and register in the multiplier of sparse matrix and vector.Since F In all circular matrix generator polynomials share α=64 ' 1 ', then the multiplier of sparse matrix and vector need using (α-c)=48 two input XOR gates calculate f simultaneously_1,n,f_2,n,…,f_16,n.F and w can have been calculated within 21 clock cycle Finish.The step of calculating vector f and w using the multiplier of sparse matrix and vector is as follows:

Step 1 inputs message segment a₁,a₂,…,a₁₆, they are stored in register R respectively_1,1,R_1,2,…,R_1,16In；

Step 2, register R_1,1,R_1,2,…,R_1,16Ring shift left 1 time simultaneously, XOR gate X_1,1,X_1,2,…,X_1,16Respectively will Exclusive or result is moved to left into register R_1,17,R_1,18,…,R_1,32In；

Step 3 repeats step 2 b times, after the completion, register R_1,17,R_1,18,…,R_1,32The content of storage is vector respectively Section f₁,f₂,…,f₁₆, they constitute vector f and w.

Formula (7) imply after to iterative operation, it is necessary to solve vector q and x paragraph by paragraph.Define [q x]=(q₁,q₂,…, q₁₆), and it is initialized as complete zero.Firstly, q₁Exactly equal to f₁.Secondly, q₂It is the 2nd piece of row and vector [q x] of matrix Q^TProduct with f₂2 He of mould.Then, q₃It is the 3rd piece of row and vector [q x] of matrix Q^TProduct and f₃2 He of mould.It repeats the above process, until Q is calculated₁₆Until, to iterative circuit after I type as shown in Figure 5.To iterative circuit by 16 b bit register R after I type_2,1, R_2,2,…,R_2,16With 15 multi input modulo 2 adder A_2,2,A_2,3,…,A_2,16Composition.

To calculate q_jFor (1≤j≤16).Nonzero circle matrix in check matrix H is usually the circulation of unit matrix Move to right version.Assuming that having N number of nonzero circle matrix in the jth block row of matrix Q, their ring shift right digit is s respectively_j,k1, s_j,k2,…,s_j,kN(1≤k1,k2,…,kN<j).Then,

Because of N very little, formula (13) can be by a multi input modulo 2 adder to input ring shift left in 1 clock It calculates and finishes in period.Therefore, calculate vector [q x] needs 16 clock cycle altogether.Since sharing β=38 non-zero in matrix Q Circular matrix, then being needed to iterative circuit using (β-c) b=462 two input XOR gate after I type.

Matrix Q is by 16 × 16 b × b rank circular matrix Q_j,kThe array that (1≤j≤16,1≤k≤16) are constituted.Non-zero Circular matrix Q_j,kRing shift right digit relative to b × b rank unit matrix is s_j,k, 0≤s_j,k<b.For ease of description, complete zero follows Ring matrix is denoted as s relative to the ring shift right digit of b × b rank circular matrix_j,k='-'.In Fig. 5, nonzero circle matrix Q_j,k Corresponding array section q_kBy ring shift left s_j,kMulti input modulo 2 adder A is sent into behind position_2,jIn with array section f_jXOR operation is carried out, The corresponding array section of complete zero circular matrix is not involved in XOR operation, A_2,jCalculated result be q_j, it is stored in register R_2,jIn.Fig. 6 Give the block position in matrix Q where nonzero circle matrix and its ring shift right digit.It is calculated using after I type to iterative circuit The step of vector q and x, is as follows:

Step 1, input vector section f₁, by array section q₁=f₁It is stored in register R_2,1In；

Step 2, input vector section f_j, nonzero circle matrix Q_j,kCorresponding array section q_kBy ring shift left s_j,kIt is sent into behind position Multi input modulo 2 adder A_2,jIn with array section f_jCarry out XOR operation, exclusive or result q_jIt is stored into register R_2,jIn, wherein 2 ≤ j≤16,1≤k < j, 0≤s_j,k<21；

Step 3 is incremented by the value for changing j for step-length with 1, repeats step 2 15 times, finally, register R_2,1,R_2,2,…, R_2,16Storage is array section q respectively₁,q₂,…,q₁₆, they constitute vector q and x.

Formula (9) also imply after to iterative operation, it is necessary to solve vector y paragraph by paragraph.Define y=(y₁,y₂,…,y₁₄), and just Beginning turns to complete zero.Firstly, y₁It is the 1st piece of row and vector [p of matrix Y_x y]^TProduct.Secondly, y₂Be matrix Y the 2nd piece of row with Vector [p_x y]^TProduct.It repeats the above process, until having calculated y₁₄Until, to iterative circuit after II type as shown in Figure 7.II type Backward iterative circuit is by 16 b bit register R_3,1,R_3,2,…,R_3,16With 14 multi input modulo 2 adder A_3,1,A_3,2,…, A_3,14Composition.Calculate vector y needs 14 clock cycle altogether.Since nonzero circle matrix in ξ=38 is shared in matrix Y, then II It is needed to iterative circuit using (ξ -2c+2u) b=210 two input XOR gate after type.Matrix Y is recycled by 14 × 16 b × b ranks Matrix Y_j,kThe array that (1≤j≤14,1≤k≤16) are constituted.Nonzero circle matrix Y_j,kRelative to following for b × b rank unit matrix It is s that ring, which moves to right digit,_j,k, 0≤s_j,k<b.Fig. 8 gives block position and its ring shift right in matrix Y where nonzero circle matrix Digit.It is as follows using the step of calculating vector y to iterative circuit after II type:

Step 1, input validation section p₁And p₂, they are stored in register R respectively_3,15And R_3,16In；

Step 2, nonzero circle matrix Y_j,kCorresponding array section p_kOr y_kBy ring shift left s_j,kMulti input mould 2 is sent into behind position Adder A_3,jMiddle carry out XOR operation, exclusive or result y_jIt is stored into register R_3,jIn, wherein 1≤j≤14,1≤k < 2+j, 0 ≤s_j,k<21；

Step 3 is incremented by the value for changing j for step-length with 1, repeats step 2 14 times, finally, register R_3,1,R_3,2,…, R_3,14Storage is array section y respectively₁,y₂,…,y₁₄, they constitute vector y.

The high speed QC-LDPC coding method based on three class pipeline that the present invention provides a kind of, suitable for WPAN system 1/2 code rate QC-LDPC code, coding step is described as follows:

Step 1 calculates vector f and w using the multiplier of sparse matrix and vector；

Step 2 calculates vector q and x to iterative circuit using after I type, so as to find out vector p is partially verified_x=x；

Step 3 obtains part verification vector p using vector y, y and vector q exclusive or is calculated to iterative circuit after II type_y, from And obtain verification vector p=(p_x,p_y)。

When hardware resource consumption needed for Fig. 9 summarizes each coding step of encoder and entire cataloged procedure and processing Between.

From Fig. 9, it is not difficult to find out that, when assembly line is full of, entire cataloged procedure needs max (t-c+b, c)=37 clock weeks altogether Phase, less than 336 clock cycle needed for the serial encoding method based on 16 SRAA-I circuits.After the former coding rate is 9 times of person.

In WPAN standard the existing solution of 1/2 code rate QC-LDPC encoder need 672 registers, 336 it is two defeated Enter and door and 336 two input XOR gates, it is also necessary to the generator polynomial of 5376 bit ROM storage circular matrix.And it is of the invention 1344 registers, 0 two inputs and door and 720 two input XOR gates are needed, ROM is not necessarily to.

To sum up, compared with traditional serial SRAA method, the present invention has coding rate fast, excellent without memory etc. Point.

One of the above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, Anyone skilled in the art within the technical scope disclosed by the invention, the change that can be expected without creative work Change or replace, should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with claims Defined by subject to protection scope.

Claims (3)

1. the high speed QC-LDPC encoder in a kind of WPAN based on three class pipeline, the check matrix H of 1/2 code rate QC-LDPC code It is the array being made of c × t b × b rank circular matrix, wherein c=16, t=32, b=21, e=t-c=16, check matrix H is transformed near lower triangular shape by ranks exchange, can be divided into 6 submatrixs,A is by 14 × 16 B × b rank circular matrix is constituted, and B is made of 14 × 2 b × b rank circular matrixes, and T is by 14 × 14 b × b rank circular matrixes It constitutes, C is made of 2 × 16 b × b rank circular matrixes, and D is made of 2 × 2 b × b rank circular matrixes, and E is by 2 × 14 A b × b rank circular matrix is constituted, Φ=(ET^-1B+D)^-1It is 42 × 42 rank unit matrixs, wherein subscript^ΤWith^-1It respectively indicates and turns It sets and inverse,It is by 16 × 16 b × b rank circular matrix Q_j,kIt constitutes, wherein I is unit matrix, and 0 is full zero moment Battle array, 1≤j≤16,1≤k≤16, nonzero circle matrix Q_j,kRing shift right digit relative to b × b rank unit matrix is s_j,k, Wherein, 0≤s_j,k<b, Y=[B T] are by 14 × 16 b × b rank circular matrix Y_j,kIt constitutes, wherein 1≤j≤14,1≤k≤ 16, nonzero circle matrix Y_j,kRing shift right digit relative to b × b rank unit matrix is s_j,k, wherein 0≤s_j,k<b, A and C The corresponding a part verification vector p of corresponding informance vector a, matrix B and D_x, matrix T and E then correspond to remaining verification vector p_y, verification Vector p=(p_x,p_y), with b bit for one section, information vector a is divided into 16 sections, i.e. a=(a₁,a₂,…,a₁₆), verify vector P is divided into 16 sections, i.e. p=(p₁,p₂,…,p₁₆), p_x=(p₁,p₂), p_y=(p₃,p₄,…,p₁₆), vector f is divided into 14 Section, i.e. f=(f₁,f₂,…,f₁₄), vector w is divided into 2 sections, i.e. w=(f₁₅,f₁₆), [f w]=(f₁,f₂,…,f₁₆), vector Q is divided into 14 sections, i.e. q=(q₁,q₂,…,q₁₄), vector x is divided into 2 sections, i.e. x=(q₁₅,q₁₆), [q x]=(q₁, q₂,…,q₁₆), vector y is divided into 14 sections, i.e. y=(y₁,y₂,…,y₁₄), which is characterized in that the encoder includes following Component:

The multiplier of sparse matrix and vector, by 32 b bit register R_1,1,R_1,2,…,R_1,32With 16 multi input XOR gates X_1,1,X_1,2,…,X_1,16Composition, for calculating vector f and w；

To iterative circuit after I type, by 16 b bit register R_2,1,R_2,2,…,R_2,16With 15 multi input modulo 2 adder A_2,2, A_2,3,…,A_2,16Composition, for calculating vector q and x, so as to find out vector p is partially verified_x=x；

To iterative circuit after II type, by 16 b bit register R_3,1,R_3,2,…,R_3,16With 14 multi input modulo 2 adder A_3,1, A_3,2,…,A_3,14Composition obtains part verification vector p for calculating vector y, y and vector q exclusive or_y, to obtain verification vector p =(p_x,p_y)；

It is as follows that the multiplier of the sparse matrix and vector calculates the step of vector f and w:

Step 1 inputs message segment a₁,a₂,…,a₁₆, they are stored in register R respectively_1,1,R_1,2,…,R_1,16In；

Step 2, register R_1,1,R_1,2,…,R_1,16Ring shift left 1 time simultaneously, pass through partially connected to XOR gate X later_1,1, X_1,2,…,X_1,16, XOR gate X_1,1,X_1,2,…,X_1,16Exclusive or result is moved to left into register R respectively_1,17,R_1,18,…,R_1,32In；

Step 3 repeats step 2 b times, after the completion, register R_1,17,R_1,18,…,R_1,32The content of storage is array section f respectively₁, f₂,…,f₁₆, they constitute vector f and w；

Wherein, partially connected depends on all circular matrix generator polynomials in matrix F, register R_1,iAll taps take The nonzero element position of all circular matrix generator polynomials certainly in i-th piece of matrix F column, and multi input XOR gate X_1,j Input depend on matrix F jth block row in all circular matrix generator polynomials nonzero element position, wherein 1≤i ≤ 16,1≤j≤16,

The step of calculating vector q and x to iterative circuit after the I type is as follows:

Step 1, input vector section f₁, by array section q₁=f₁It is stored in register R_2,1In；

Step 2, input vector section f_j, nonzero circle matrix Q_j,kCorresponding array section q_kBy ring shift left s_j,kIt how defeated is sent into behind position Enter modulo 2 adder A_2,jIn with array section f_jCarry out XOR operation, exclusive or result q_jIt is stored into register R_2,jIn, wherein 2≤j≤ 16,1≤k < j, 0≤s_j,k<21；

Step 3 is incremented by the value for changing j for step-length with 1, repeats step 2 15 times, finally, register R_2,1,R_2,2,…,R_2,16It deposits Storage is array section q respectively₁,q₂,…,q₁₆, they constitute vector q and x；

The step of calculating vector y to iterative circuit after the II type is as follows:

Step 1, input validation section p₁And p₂, they are stored in register R respectively_3,15And R_3,16In；

Step 2, nonzero circle matrix Y_j,kCorresponding array section p_kOr y_kBy ring shift left s_j,kMulti input nodulo-2 addition is sent into behind position Device A_3,jMiddle carry out XOR operation, exclusive or result y_jIt is stored into register R_3,jIn, wherein 1≤j≤14,1≤k < 2+j, 0≤s_j,k <21；

Step 3 is incremented by the value for changing j for step-length with 1, repeats step 2 14 times, finally, register R_3,1,R_3,2,…,R_3,14It deposits Storage is array section y respectively₁,y₂,…,y₁₄, they constitute vector y.

2. the high speed QC-LDPC encoder in a kind of WPAN according to claim 1 based on three class pipeline, feature exist In the process of the ranks exchange is as follows:

Step 1 carries out block column exchange, and preceding 18 pieces of column remain stationary, and rear 14 pieces of column are resequenced, they respectively correspond original the 31,30,25,28,19,20,29,32,23,22,27,26,24,21 pieces of column；

Step 2 exchanges all pieces of traveling row block rows, they respectively correspond original the 5th, 7,14,16,4,1,6,8,11,10, 13,15,12,9,3,2 pieces of rows；

Step 3, by 16 pieces of rows permutation matrix difference ring shift right 7,10,10,4,9,5,19,17,4,4,5,19,12,4, 20,7.

3. the high speed QC-LDPC coding method in a kind of WPAN based on three class pipeline, the verification square of 1/2 code rate QC-LDPC code Battle array H is the array being made of c × t b × b rank circular matrix, wherein c=16, t=32, b=21, e=t-c=16, verification Matrix H is transformed near lower triangular shape by ranks exchange, can be divided into 6 submatrixs,A be by 14 × 16 b × b rank circular matrixes are constituted, and B is made of 14 × 2 b × b rank circular matrixes, and T is recycled by 14 × 14 b × b ranks Matrix is constituted, and C is made of 2 × 16 b × b rank circular matrixes, and D is made of 2 × 2 b × b rank circular matrixes, and E is by 2 × 14 b × b rank circular matrixes are constituted, Φ=(ET^-1B+D)^-1It is 42 × 42 rank unit matrixs, wherein subscript^ΤWith^-1Table respectively Show transposition and inverse,It is by 16 × 16 b × b rank circular matrix Q_j,kIt constitutes, wherein I is unit matrix, and 0 is complete zero Matrix, 1≤j≤16,1≤k≤16, nonzero circle matrix Q_j,kRing shift right digit relative to b × b rank unit matrix is s_j,k, wherein 0≤s_j,k<b, Y=[B T] are by 14 × 16 b × b rank circular matrix Y_j,kIt constitutes, wherein 1≤j≤14,1≤ K≤16, nonzero circle matrix Y_j,kRing shift right digit relative to b × b rank unit matrix is s_j,k, wherein 0≤s_j,k<b, A With C corresponding informance vector a, matrix B and the corresponding a part verification vector p of D_x, matrix T and E then correspond to remaining verification vector p_y, Verify vector p=(p_x,p_y), with b bit for one section, information vector a is divided into 16 sections, i.e. a=(a₁,a₂,…,a₁₆), verification Vector p is divided into 16 sections, i.e. p=(p₁,p₂,…,p₁₆), p_x=(p₁,p₂), p_y=(p₃,p₄,…,p₁₆), vector f is divided It is 14 sections, i.e. f=(f₁,f₂,…,f₁₄), vector w is divided into 2 sections, i.e. w=(f₁₅,f₁₆), [f w]=(f₁,f₂,…,f₁₆), Vector q is divided into 14 sections, i.e. q=(q₁,q₂,…,q₁₄), vector x is divided into 2 sections, i.e. x=(q₁₅,q₁₆), [q x]= (q₁,q₂,…,q₁₆), vector y is divided into 14 sections, i.e. y=(y₁,y₂,…,y₁₄), which is characterized in that the coding method includes Following steps:

Step 1 calculates vector f and w using the multiplier of sparse matrix and vector；

Step 2 calculates vector q and x to iterative circuit using after I type, so as to find out vector p is partially verified_x=x；

Step 3 obtains part verification vector p using vector y, y and vector q exclusive or is calculated to iterative circuit after II type_y, thus To verification vector p=(p_x,p_y)。