CN106788457A - Second part is input into the cumulative LDPC encoder for moving to left parallel in DTMB - Google Patents

Abstract

The invention provides the QC LDPC encoders based on two-level pipeline in a kind of DTMB, the encoder includes 1 sparse matrix with the multiplier and 1 vector of vector and the multiplier of high-density matrix.Sparse matrix realizes the multiplying of sparse matrix and vector with the multiplier of vector, and the vectorial multiplier with high-density matrix moves to left mechanism using part parallel input is cumulative, realizes the vectorial multiplying with high-density matrix.Whole cataloged procedure is divided into 2 level production lines.4/5 code check QC LDPC encoders have the advantages that low cost, handling capacity are big in the DTMB systems that the present invention is provided.

Description

Second part is input into the cumulative LDPC encoder for moving to left parallel in DTMB

Technical field

The present invention relates to field of channel coding, second part is input into cumulative moving to left parallel in more particularly to a kind of DTMB systems QC-LDPC encoders.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.QC-LDPC yards of life All it is the array being made up of circular matrix into matrix G and check matrix H, the characteristics of with stages cycle, therefore is referred to as QC-LDPC Code.The first trip of circular matrix is the result of footline ring shift right 1, and remaining each row is all the knot of its lastrow ring shift right 1 Really, therefore, circular matrix is characterized by its first trip completely.Generally, the first trip of circular matrix is referred to as its generator polynomial.

DTMB standards employ QC-LDPC yards of system form, and the left-half of its generator matrix G is a unit square Battle array, right half part is by e × c b × b rank circular matrixes G_i,j(1≤i≤e,e<J≤t, t=e+c) constitute array, it is as follows It is shown：

Wherein, I is b × b rank unit matrixs, and 0 is b × b rank full null matrix.Continuous b rows and the b row of G are known respectively as block Row and block row.From formula (1), G has e blocks row and t blocks to arrange.DTMB standards employ QC-LDPC yards of a kind of code check η=4/5, For the code, t=59, e=48, c=11, b=127.

The existing solution of 4/5 code check QC-LDPC encoders is added based on c I type shift register in DTMB standards The serial encoder of accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) circuit.By c The serial encoder that SRAA-I circuits are constituted, completes coding within e × b clock cycle.The program needs 2 × c × b deposit Device, c × b two inputs and door and c × b two input XOR gate, in addition it is also necessary to which e × c × b bits ROM stores the life of circular matrix Into multinomial.The program has two shortcomings：One is to need a large amount of memories, causes circuit cost high；Two is serial input information Bit, coding rate is slow.

The content of the invention

In DTMB systems the existing implementation of 4/5 code check QC-LDPC encoders exist high cost, coding rate it is slow lack Point, for these technical problems, the invention provides a kind of QC-LDPC encoders based on two-level pipeline.

As shown in figure 1, the QC-LDPC encoders based on two-level pipeline are mainly made up of 2 parts in DTMB systems：It is sparse Matrix and the multiplier and vector of vector and the multiplier of high-density matrix.2 steps of cataloged procedure point are completed：1st step, using sparse Matrix calculates vector s with the multiplier of vector；2nd step, verification vector p is calculated using vector with the multiplier of high-density matrix.

Can be further understood by following detailed description and accompanying drawings with method on advantage of the invention.

Brief description of the drawings

Fig. 1 is the QC-LDPC cataloged procedures based on two-level pipeline；

Fig. 2 is the multiplier of sparse matrix and vector；

Fig. 3 is the functional block diagram of the multiply-add shift register MASR circuits of parallel input；

Fig. 4 is a kind of vector for moving to left that added up based on part parallel input being made up of the MASR circuits of c parallel input With high-density matrix multiplier；

Fig. 5 summarize each coding step of encoder and whole cataloged procedure needed for hardware resource and process time.

Specific embodiment

Presently preferred embodiments of the present invention is elaborated below in conjunction with the accompanying drawings, so that advantages and features of the invention can be more It is easy to be readily appreciated by one skilled in the art, apparent is clearly defined so as to be made to protection scope of the present invention.

The row weight and row heavy phase of circular matrix are same, are denoted as w.If w=0, then the circular matrix is full null matrix.If W=1, then the circular matrix is replaceable, referred to as permutation matrix, and it can be by some positions of unit matrix I ring shift rights Obtain.QC-LDPC yards of check matrix H is by c × t b × b rank circular matrixes H_j,k(1≤j≤c, 1≤k≤t, t=e+c) The following array for constituting：

Under normal circumstances, any circular matrix in check matrix H is either full null matrix (w=0) or is displacement square Battle array (w=1).Make circular matrix H_j,kFirst trip h_j,k=(h_j,k,1,h_j,k,2,…,h_j,k,b) it is its generator polynomial, wherein h_j,k,m =0 or 1 (1≤m≤b).Because H is sparse, h_j,kOnly 1 ' 1 ', even without ' 1 '.

It is information vector a that the preceding e blocks row of H are corresponding, and it is verification vector p, code word v=(a, p) that rear c blocks row are corresponding.With b Bit is one section, and information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e)；Verification vector p is divided into c sections, i.e. p= (p₁,p₂,…,p_c).The matrix that the preceding e blocks row and rear c blocks row of H are constituted is denoted as C and D respectively, then

H=[C D] (3)

C is made up of c × e b × b rank circular matrix, and D is made up of c × c b × b rank circular matrix.By formula (3) and Code word v=(a, p) substitutes into Hv^T=0, arrangement can be obtained

p^T=Φ^TCa^T (4)

Wherein, Φ^T=D^–1, subscript^TWith^–1Transposition and inverse of a matrix are represented respectively, and D must full rank.It is well known that Cyclic Moment The inverse, product of battle array and be still circular matrix.Therefore, Φ is also the array being made up of circular matrix.But, although matrix D is Sparse, but Φ is generally no longer sparse but highdensity.

Make s^T=Ca^TAnd p^T=Φ^Ts^T, then p=s Φ.The multiplication that s is related to sparse matrix and vector is calculated using C, Φ is used Calculate the multiplication that p is related to vector and high-density matrix.From the above discussion, a kind of QC- based on two-level pipeline can be given LDPC cataloged procedures, as shown in Figure 1.

Make s=(s₁,s₂,…,s_c), then s_j ^TIt is the jth block row and a of Matrix C^TProduct, i.e.,

Wherein, 1≤i≤e, 1≤j≤c.s_jThe n-th bit s_j,n(1≤n≤b) is

Wherein, subscript rs (n -1) and ls (n -1) represent ring shift right n -1 and ring shift left n -1 respectively.Since appointing One circular matrix generator polynomial h_j,iOnly a small amount of ' 1 ' even complete zero, then the inner product in formula (6) can be by circulation Move to left the tap summation of register to realize, sparse matrix and vectorial multiplier as shown in Figure 2.Sparse matrix and vector Multiplier is by t b bit registers R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition.Deposit Device R_1,1,R_1,2,…,R_1,eFor loading and ring shift left message segment a₁,a₂,…,a_e, register R_1,e+1,R_1,e+2,…,R_1,tWith In the array section s of storage s₁,s₂,…,s_c.All circular matrixes generation that partially connected in Fig. 2 is depended in Matrix C is multinomial Formula.If h_j,i,m=1 (1≤m≤b), then message segment a_iM bits be connected to XOR gate X_1,j.Therefore, register R_1,i's All taps depend on the nonzero element position of all circular matrix generator polynomials in i-th piece of Matrix C row, and multi input XOR gate X_1,jInput depending on all circular matrix generator polynomials in Matrix C jth block row nonzero element position. If total α ' 1 ' of all circular matrix generator polynomials in C, then sparse matrix is needed to use with the multiplier of vector (α-c) individual two inputs XOR gate calculates s simultaneously_1,n,s_2,n,…,s_c,n.S can be calculated within b clock cycle and finished.Using sparse The step of matrix calculates vector s with the multiplier of vector is as follows：

1st step, input message segment a₁,a₂,…,a_e, they are stored in register R respectively_1,1,R_1,2,…,R_1,eIn；

2nd step, register R_1,1,R_1,2,…,R_1,eRing shift left 1 time, XOR gate X simultaneously_1,1,X_1,2,…,X_1,cRespectively will XOR result is moved to left into register R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 times, after the completion of, register R_1,e+1,R_1,e+2,…,R_1,tThe content of storage be respectively to Amount section s₁,s₂,…,s_c, they constitute vectorial s.

p^T=Φ^Ts^TIt is equivalent to p=s Φ.Φ is by c × c b × b rank circular matrixes Φ_j,u(1≤j≤c,1≤u≤c) The array of composition.Make circular matrix Φ_j,uFirst trip g_j,uIt is its generator polynomial.From p=s Φ, u sections of verification vector is full Foot

p_u=s₁Φ_1,u+s₂Φ_2,u+…+s_jΦ_j,u+…+s_cΦ_c,u (7)

Make generator polynomial g_j,u=(g_j,u,1,g_j,u,2,…,g_j,u,b), then Φ_j,uCan be considered unit matrix ring shift right version This weighted sum, i.e.,

Φ_j,u=g_j,u,1I^r(0)+g_j,u,2I^r(1)+…+g_j,u,bI^r(b-1)(8) wherein, Subscript r () represents ring shift right.So, jth on the right of formula (7) equal sign is deployable is

Since by s_jRing shift right n be equivalent to by it ring shift left b-n, i.e.,So formula (9) can change It is written as

Formula (10) is the process of a-multiply-add-move to left-store, and it realizes the multiply-add shift register with parallel input (Multiplier-Adder-Shift-Register, MASR) circuit.Fig. 3 is the functional block diagram of the MASR circuits of parallel input, Vectorial s sends into the circuit parallel with b bits as one section.When with the MASR circuits of parallel input to verification section p_u(1≤u≤c) enters During row coding, generator polynomial look-up table prestores all generator polynomials of the u blocks row of matrix Φ, shift register quilt Reset initialization.When arriving the 1st clock cycle, array section s₁Move into circuit, the 1st of generator polynomial look-up table output Φ the The generator polynomial Φ of block row, u blocks row_1,uThe 0th bit g_1,u,1, and with array section s₁Carry out scalar multiplication, product g_1,u,1s₁ The mould 2 of content 0 with shift register adds, and g_1,u,1s₁Result (the 0+g of ring shift left 1_1,u,1s₁)^l(1)It is stored back to shift LD Device.When arriving the 2nd clock cycle, generator polynomial look-up table output Φ_1,uThe 2nd bit g_1,u,2, and with array section s₁ Carry out scalar multiplication, product g_1,u,2s₁With the content (0+g of shift register_1,u,1s₁)^l(1)Mould 2 adds, and (0+g_1,u,1s₁)^l(1)+ g_1,u,2s₁The result ((0+g of ring shift left 1_1,u,1s₁)^l(1)+g_1,u,2s₁)^l(1)It is stored back to shift register.Above-mentioned-multiply-add-move to left- Storing process proceeds down.At the end of b-th clock cycle, shift register storage is part and s₁Φ_1,u, this It is array section s₁To p_uContribution.When arriving the b+1 clock cycle, array section s₂Circuit is moved into, above-mentioned-multiply-add-left side is repeated Shifting-storing process.When generator polynomial look-up table has exported Φ_2,uLast bit g_2,u,bWhen, accumulator storage is portion Divide and s₁Φ_1,u+s₂Φ_2,u.Said process is repeated, circuit is moved into until whole vector s is all parallel.Now, accumulator is stored It is verification section p_u。

Fig. 4 gives a kind of vector for moving to left that added up based on part parallel input being made up of the MASR of c parallel input With high-density matrix multiplier, posted by generator polynomial look-up table, b binary multiplier, b binary adder and displacement Four kinds of functional module compositions of storage.Generator polynomial look-up table L₁,L₂,…,L_cPrestore matrix Φ the 1,2nd respectively ..., in c blocks row All circular matrix generator polynomials.Generator polynomial look-up table L₁,L₂,…,L_cThe generator polynomial bit of output respectively with Array section s_j(1≤j≤c) carries out scalar multiplication, and this c scalar multiplication is respectively by b binary multiplier M₁,M₂,…,M_cIt is complete Into.B binary multiplier M₁,M₂,…,M_cProduct respectively with shift register R₁,R₂,…,R_cContent be added, this c Nodulo-2 addition is respectively by b binary adder A₁,A₂,…,A_cComplete.B binary adder A₁,A₂,…,A_cAnd quilt Result after ring shift left 1 is stored in shift register R respectively₁,R₂,…,R_c。

Generator polynomial look-up table L₁,L₂,…,L_cCircular matrix generator polynomial in storage matrix Φ.Generator polynomial Look-up table L₁~L_cThe all generator polynomials in 1~c blocks row of storage Φ, for any block row, store the 1st successively respectively, 2 ..., the corresponding generator polynomial of c block rows.Generator polynomial look-up table L₁~L_cThe bit of Serial output generator polynomial.

The step of calculating verification vector p with the multiplier of high-density matrix using vector is as follows：

1st step, resets shift register R₁,R₂,…,R_c；

2nd step, input vector section s_j(1≤j≤c)；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ jth block rows ..., c blocks row Generator polynomial bit, these generator polynomial bits are respectively by b binary multiplier M₁,M₂,…,M_cWith array section s_jCarry out scalar multiplication, b binary multiplier M₁,M₂,…,M_cProduct respectively by b binary adder A₁,A₂,…,A_c With shift register R₁,R₂,…,R_cContent be added, b binary adder A₁,A₂,…,A_cAnd by after ring shift left 1 Result be stored in shift register R respectively₁,R₂,…,R_c；

4th step, repeats the 3rd step b-1 times；

5th step, with 1 for step-length is incremented by the value for changing j, repeats the 2nd~4 step c-1 times, until whole vector s has been input into Finish, now, shift register R₁,R₂,…,R_cStorage is respectively verification section p₁,p₂,…,p_c, they constitute verification vector p =(p₁,p₂,…,p_c)。

The invention provides a kind of QC-LDPC coding methods based on two-level pipeline, it is adaptable in DTMB systems 4/5 Code check QC-LDPC yards, its coding step is described as follows：

1st step, vector s is calculated using sparse matrix with the multiplier of vector；

2nd step, verification vector p is calculated using vector with the multiplier of high-density matrix.

Fig. 5 summarize each coding step of encoder and whole cataloged procedure needed for hardware resource consumption and treatment when Between.

It is not difficult to find out from Fig. 5, when streamline is full of, whole cataloged procedure needs max (t-c+b, cb)=cb clock week altogether Phase, less than based on the e × b clock cycle needed for the c serial encoding method of SRAA-I circuits.For in DTMB standards 4/5 Code check QC-LDPC encoders, coding rate of the invention is 4 times of the latter.

The existing solution of 4/5 code check QC-LDPC encoders needs e × c × b bit ROM in DTMB standards, and this hair It is bright to need c²B bits ROM.The present invention needs less ROM, is the 1/4 of existing solution.

As fully visible, for 4/5 code check QC-LDPC encoders in DTMB standards, compared with traditional serial SRAA methods, this Invention has the advantages that coding rate is fast, memory consumption lacks.

The above, one of specific embodiment only of the invention, but protection scope of the present invention is not limited thereto, Any those of ordinary skill in the art disclosed herein technical scope in, the change that can be expected without creative work Change or replace, should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with claims The protection domain for being limited is defined.

Claims (4)

1. QC-LDPC encoders based on two-level pipeline in a kind of DTMB, 4/5 code check QC-LDPC yards of check matrix H be by The array that c × t b × b ranks circular matrix is constituted, wherein, c=11, t=59, b=127, e=t-c=48, check matrix H can 2 submatrixs, H=[C D] are divided into, C is made up of c × e b × b rank circular matrix, D is circulated by c × c b × b rank Matrix is constituted, Φ^T=D^–1, wherein, subscript^TWith^-1Transposition and inverse, Matrix C corresponding informance vector a, matrix D correspondence school are represented respectively Vectorial p is tested, is one section with b bits, information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e), verification vector p is divided Be c sections, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s are divided into c sections, i.e. s=(s₁,s₂,…,s_c), it is special Levy and be, the encoder is included with lower component：

Sparse matrix and vectorial multiplier, by t b bit registers R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition, for calculating vectorial s；

Vector and the multiplier of high-density matrix, move to left mechanism based on part parallel input is cumulative, by generator polynomial look-up table, B binary multiplier, b binary adder and shift register composition, for calculating verification vector p, generator polynomial Look-up table L₁,L₂,…,L_cPrestore matrix Φ the 1,2nd respectively ..., all circular matrix generator polynomials in c blocks row；Generation is more Item formula look-up table L₁,L₂,…,L_cThe generator polynomial bit of output respectively with array section s_jScalar multiplication is carried out, this c scalar multiplication Method is respectively by b binary multiplier M₁,M₂,…,M_cComplete；B binary multiplier M₁,M₂,…,M_cProduct respectively with Shift register R₁,R₂,…,R_cContent be added, this c nodulo-2 addition is respectively by b binary adder A₁,A₂,…,A_c Complete；B binary adder A₁,A₂,…,A_cAnd shift register R is stored in by the result after ring shift left 1 respectively₁, R₂,…,R_c, wherein, 1≤j≤c.

2. the QC-LDPC encoders of two-level pipeline are based in a kind of DTMB according to claim 1, it is characterised in that The step of sparse matrix calculates vector s with the multiplier of vector is as follows：

1st step, input message segment a₁,a₂,…,a_e, they are stored in register R respectively_1,1,R_1,2,…,R_1,eIn；

2nd step, register R_1,1,R_1,2,…,R_1,eRing shift left 1 time, XOR gate X simultaneously_1,1,X_1,2,…,X_1,cRespectively by XOR Result is moved to left into register R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 times, after the completion of, register R_1,e+1,R_1,e+2,…,R_1,tThe content of storage is respectively array section s₁,s₂,…,s_c, they constitute vectorial s.

3. the QC-LDPC encoders of two-level pipeline are based in a kind of DTMB according to claim 1, it is characterised in that The step of vector calculates verification vector p with the multiplier of high-density matrix is as follows：

1st step, resets shift register R₁,R₂,…,R_c；

2nd step, input vector section s_j, wherein, 1≤j≤c；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ jth block rows ..., the life of c blocks row Into multinomial bit, these generator polynomial bits are respectively by b binary multiplier M₁,M₂,…,M_cWith array section s_jEnter Row scalar multiplication, b binary multiplier M₁,M₂,…,M_cProduct respectively by b binary adder A₁,A₂,…,A_cWith shifting Bit register R₁,R₂,…,R_cContent be added, b binary adder A₁,A₂,…,A_cAnd by the knot after ring shift left 1 Fruit is stored in shift register R respectively₁,R₂,…,R_c；

4th step, repeats the 3rd step b-1 times；

5th step, with 1 for step-length is incremented by the value for changing j, repeats the 2nd~4 step c-1 times, until whole vector s inputs are finished, this When, shift register R₁,R₂,…,R_cStorage is respectively verification section p₁,p₂,…,p_c, they constitute verification vector p=(p₁, p₂,…,p_c)。

4. the QC-LDPC coding methods based on two-level pipeline in a kind of DTMB, 4/5 code check QC-LDPC yards of check matrix H is The array being made up of c × t b × b rank circular matrix, wherein, c=11, t=59, b=127, e=t-c=48, check matrix H 2 submatrixs, H=[C D] can be divided into, C is made up of c × e b × b rank circular matrix, and D is followed by c × c b × b rank Ring matrix is constituted, Φ^T=D^–1, wherein, subscript^TWith^-1Transposition and inverse, Matrix C corresponding informance vector a, matrix D correspondence are represented respectively Verification vector p, is one section with b bits, and information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e), verification vector p by etc. It is divided into c sections, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s are divided into c sections, i.e. s=(s₁,s₂,…,s_c), its It is characterised by, the coding method is comprised the following steps：

1st step, vector s is calculated using sparse matrix with the multiplier of vector；

2nd step, verification vector p is calculated using vector with the multiplier of high-density matrix.