CN104579365A - High-speed QC-LDPC (quasi-cyclic low-density parity-check) encoder based on four-level assembly lines - Google Patents

Abstract

The invention provides a high-speed QC-LDPC (quasi-cyclic low-density parity-check) encoder based on four-level assembly lines. The encoder comprises a multiplier for sparse matrixes and vectors, an I-type backward iterative circuit, a multiplier for high-density matrixes and vectors and an II-type backward iterative circuit. The multiplier for the sparse matrixes and vectors is used for multiplication of the sparse matrixes and vectors, the multiplier for the high-density matrixes and vectors is used for multiplication of the high-density matrixes and vectors, and each of the I-type backward iterative circuit and the II-type backward iterative circuit is used for backward iterative operation. The whole encoding process is divided into the four-level assembly lines. The high-speed QC-LDPC encoder has the advantages of simple structure, low cost, high throughput capacity and the like.

Description

Based on the high speed QC-LDPC encoder of four level production lines

Technical field

The present invention relates to field of channel coding, particularly in a kind of communication system based on the high speed QC-LDPC encoder of four level production lines.

Background technology

Code is one of efficient channel coding technology to low-density checksum (Low-Density Parity-Check, LDPC), and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The generator matrix G of QC-LDPC code and check matrix H are all the arrays be made up of circular matrix, have the feature of stages cycle, therefore are called as QC-LDPC code.The first trip of circular matrix is the result of footline ring shift right 1, and all the other each provisional capitals are results of its lastrow ring shift right 1, and therefore, circular matrix is characterized by its first trip completely.Usually, the first trip of circular matrix is called as its generator polynomial.

Communication system adopts the QC-LDPC code of system form usually, and the left-half of its generator matrix G is a unit matrix, and right half part is by e × c b × b rank circular matrix G _i,jthe array that (0≤i<e, e≤j<t, t=e+c) is formed, as follows:

Wherein, I is b × b rank unit matrixs, and 0 is the full null matrix in b × b rank.The continuous b of G capable and b row are called as the capable and block row of block respectively.From formula (1), G has e block capable and t block row.

At present, what QC-LDPC code extensively adopted is the serial encoder adding accumulator (Type-IShift-Register-Adder-Accumulator, SRAA-I) circuit based on c I type shift register.The serial encoder be made up of c SRAA-I circuit, completes coding within e × b clock cycle.The program needs 2 × c × b register, c × b two inputs to input XOR gate with door and c × b individual two, also needs e × c × b bit ROM to store the generator polynomial of circular matrix.The program has two shortcomings: one is need a large amount of memory, causes circuit cost high; Two is serial input information bits, and coding rate is slow.

Summary of the invention

In communication system there is the shortcoming that cost is high, coding rate is slow in the existing implementation of QC-LDPC encoder, for these technical problems, the invention provides a kind of high speed QC-LDPC encoder based on four level production lines.

As shown in Figure 2, the high speed QC-LDPC encoder based on four level production lines in communication system forms primarily of 4 parts: sparse matrix and the multiplier of vector, after I type after iterative circuit, high-density matrix and vectorial multiplier and II type to iterative circuit.Cataloged procedure divides 4 steps to complete: the 1st step, uses sparse matrix and vectorial multiplier compute vector f and w; 2nd step, to iterative circuit compute vector q and x after use I type; 3rd step, uses high-density matrix to verify vectorial p with the multiplier calculating section of vector _x; 4th step, obtains part to iterative circuit compute vector y, y and vectorial q XOR after using II type and verifies vectorial p _y, thus obtain verifying vectorial p=(p _x, p _y).

High speed QC-LDPC coder structure provided by the invention is simple, under the condition significantly improving coding rate, can reduce memory, thus reduces costs, improve throughput.

Be further understood by detailed description and accompanying drawings below about advantage of the present invention and method.

Accompanying drawing explanation

Fig. 1 is the structural representation of near lower triangular check matrix after ranks exchange;

Fig. 2 is the QC-LDPC cataloged procedure based on four level production lines;

Fig. 3 is the functional block diagram of ring shift left accumulator RLA circuit;

Fig. 4 is the multiplier of a kind of high-density matrix and the vector be made up of u RLA circuit;

Fig. 5 is sparse matrix and vectorial multiplier;

Fig. 6 is to iterative circuit after I type;

Fig. 7 is to iterative circuit after II type;

Fig. 8 summarizes each coding step of encoder and the hardware resource needed for whole cataloged procedure and processing time.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment of the present invention is elaborated, can be easier to make advantages and features of the invention be readily appreciated by one skilled in the art, thus more explicit defining is made to protection scope of the present invention.

The row of circular matrix is heavy identical with column weight, is denoted as w.If w=0, so this circular matrix is full null matrix.If w=1, so this circular matrix is replaceable, is called permutation matrix, and it is by obtaining the some positions of unit matrix I ring shift right.The check matrix H of QC-LDPC code is by c × t b × b rank circular matrix H _j,kthe following array that (1≤j≤c, 1≤k≤t, t=e+c) is formed:

Under normal circumstances, the arbitrary circular matrix in check matrix H is full null matrix (w=0) or is permutation matrix (w=1).Make circular matrix H _j,kfirst trip g _j,k=(g _{j, k, 1}, g _{j, k, 2}..., g _{j, k, b}) be its generator polynomial, wherein g _{j, k, m}=0 or 1 (1≤m≤b).Because H is sparse, so g _j,konly have 1 ' 1 ', even there is no ' 1 '.

That the front e block row of H are corresponding is information vector a, and that rear c block row are corresponding is the vectorial p of verification.Be one section with b bit, information vector a is divided into e section, i.e. a=(a ₁, a ₂..., a _e); Verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c).

Check matrix H is gone and exchanges and row swap operation, be converted near lower triangular shape H _aLT, as shown in Figure 1.In FIG, the unit of all matrixes is all b bit instead of 1 bit.A is made up of (c-u) × e b × b rank circular matrix, B is made up of (c-u) × u b × b rank circular matrix, T is made up of (c-u) × (c-u) individual b × b rank circular matrix, C is made up of u × e b × b rank circular matrix, D is made up of u × u b × b rank circular matrix, and E is made up of u × (c-u) individual b × b rank circular matrix.T is lower triangular matrix, and u reflects check matrix H _aLTwith the degree of closeness of lower triangular matrix.In FIG, matrix A and C corresponding informance vector a, matrix B and the vectorial p of the corresponding part verification of D _x=(p ₁, p ₂..., p _u), matrix T and E be corresponding remaining verification vector p then _y=(p _u+1, p _u+2..., p _c).p＝(p _x,p _y)。Above-mentioned matrix and vector meet following relation:

p _x ^Τ＝Φ(ET ^-1Aa ^Τ+Ca ^Τ) (3)

p _y ^Τ＝T ^-1(Aa ^Τ+Bp _x ^Τ) (4)

Wherein, Φ=(ET ^-1b+D) ^-1, subscript ^Τwith ^-1represent transposition and inverse respectively.As everyone knows, circular matrix inverse, product and remain circular matrix.Therefore, Φ is also the array be made up of circular matrix.Although matrix E, T, B and D are sparse matrixes, Φ is no longer sparse but highdensity under normal circumstances.

Make f ^t=Aa ^t, q ^t=T ^{– 1}f ^t, w ^t=Ca ^t, x ^t=Eq ^t+ w ^t, p _x ^t=Φ x ^t, y ^t=T ^{– 1}bp _x ^tand p _y ^t=q ^t+ y ^t.Vector f and w can be calculated by following formula:

${\left[\begin{array}{cc}f& w\end{array}\right]}^T=\left[\begin{array}{c}A\\ C\end{array}\right]a^T={\mathrm{Fa}}^T---\left(5\right)$

Wherein,

$F=\left[\begin{array}{c}A\\ C\end{array}\right]---\left(6\right)$

Q ^t=T ^{– 1}f ^tand x ^t=Eq ^t+ w ^tcan matrix equality be constructed as follows:

$\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]{\left[\begin{array}{cc}q& x\end{array}\right]}^T=Q{\left[\begin{array}{cc}q& x\end{array}\right]}^T={\left[\begin{array}{cc}f& w\end{array}\right]}^T---\left(7\right)$

Wherein,

$Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]---\left(8\right)$

Once calculate p _x, y ^t=T ^{– 1}bp _x ^tcan be rewritten as:

[B T][p _xy] ^Τ＝Y[p _xy] ^Τ＝0 (9)

Wherein,

Y＝[B T] (10)

Because Q is the same with Y and T is all lower triangular matrix, so [the q x] in formula (7) and the y in formula (9) can adopt the account form of backward iteration.

Φ relates to high-density matrix and vectorial multiplication, and F relates to sparse matrix and vectorial multiplication, and Q and Y relates to backward iterative computation.Based on the above discussion, a kind of QC-LDPC cataloged procedure based on four level production lines can be provided, as shown in Figure 2.

P _x ^t=Φ x ^tbe equivalent to p _x=x Φ ^t.Make x=(x ₁, x ₂..., x _{u × b}).Definition u bit vectors s _n=(x _n, x _n+b..., x _{n+ (u-1) × b}), wherein 1≤n≤b.Make Φ _j(1≤j≤u) is by Φ ^tjth block row in u × b rank matrix of forming of all circular matrix generator polynomials.Then have

p _j＝(…((0+s ₁Φ _j) ^ls(1)+s ₂Φ _j) ^ls(1)+…+s _bΦ _j) ^ls(1)(11)

Wherein, subscript ^{ls (1)}represent ring shift left 1.

A kind of ring shift left accumulator (Rotate-Left-Accumulator, RLA) circuit can be obtained, as shown in Figure 3 by formula (11).The index of look-up table is u bit vectors s _n, look-up table L _jthe u bit vectors that prior storage is variable and fixing Φ _jinstitute's likely product, therefore need 2 ^uthe read-only memory (Read-Only Memory, ROM) of b bit.B bit register R ₁, R ₂..., R _ube respectively used to the array section x cushioning vector x ₁, x ₂..., x _u, b bit register R _u+jfor storing p _xverification section p _j.1 RLA circuit counting vector p _jneed b clock cycle.

Since u is very little, so use u RLA circuit to calculate p simultaneously _x=(p ₁, p ₂..., p _u) be a kind of reasonable plan, high-density matrix as shown in Figure 4 and vectorial multiplier.High-density matrix and vectorial multiplier are by u look-up table L ₁, L ₂..., L _u, a 2u b bit register R _3,1, R _3,2..., R _3,2uxOR gate X is inputted with u b position two _3,1, X _3,2..., X _{3, u}composition.Look-up table L ₁, L ₂..., L _ustore variable u bit vectors and fixing matrix Φ respectively ₁, Φ ₂..., Φ _uinstitute's likely product, register R _3,1, R _3,2..., R _{3, u}be respectively used to the array section x cushioning vector x ₁, x ₂..., x _u, register R _{3, u+1}, R _{3, u+2}..., R _3,2ube respectively used to store p _xverification section p ₁, p ₂..., p _u.U RLA circuit need use ub two input XOR gate, 2 ^urOM and 2ub register of ub bit.U RLA circuit counting vector p _xneed b clock cycle.Use high-density matrix and vectorial multiplier compute vector p _xstep as follows:

1st step, resets register R _{3, u+1}, R _{3, u+2}..., R _3,2u, input vector section x ₁, x ₂..., x _u, by them respectively stored in register R _3,1, R _3,2..., R _{3, u}in;

2nd step, register R _3,1, R _3,2..., R _{3, u}ring shift left 1 time simultaneously, XOR gate X _3,1, X _3,2..., X _{3, u}respectively to look-up table L ₁, L ₂..., L _uoutput and register R _{3, u+1}, R _{3, u+2}..., R _3,2ucontent carry out XOR, XOR result is recycled to move to left after 1 time deposits back register R respectively _{3, u+1}, R _{3, u+2}..., R _3,2u;

3rd step, repeats the 2nd step b time, after completing, and register R _{3, u+1}, R _{3, u+2}..., R _3,2uthe content stored is verification section p respectively ₁, p ₂..., p _u, they constitute part and verify vectorial p _x.

Make f=(f ₁, f ₂..., f _{c – u}) and w=(f _{c – u+1}, f _{c – u+2}..., f _c), then [f w]=(f ₁, f ₂..., f _c).From formula (5), f _jthe capable and a of the jth block of matrix F ^tproduct, namely

$f_j=H_{j,1}{a}_1^T+H_{j,2}{a}_2^T+...+H_{j,i}{a}_i^T+...+H_{j,e}{a}_e^T---\left(12\right)$

Wherein, 1≤i≤e, 1≤j≤c.F _jthe n-th bit f _j,n(1≤n≤b) is

$\begin{array}{c}{f}_{j,n}=g_{j,1}^{\mathrm{rs}(n-1)}{a}_1+g_{j,2}^{\mathrm{rs}(n-1)}{a}_2+...+g_{j,i}^{\mathrm{rs}(n-1)}{a}_i+...+g_{j,e}^{\mathrm{rs}(n-1)}{a}_e\\ =g_{j,1}{a}_1^{\mathrm{ls}(n-1)}+g_{j,2}{a}_2^{\mathrm{ls}(n-1)}+...+g_{j,i}{a}_i^{\mathrm{ls}(n-1)}+...+g_{j,e}{a}_e^{\mathrm{ls}(n-1)}\end{array}---\left(13\right)$

Wherein, subscript ^{rs (n – 1)}with ^{ls (n – 1)}represent ring shift right n – 1 and ring shift left n – 1 respectively.Since arbitrary circular matrix generator polynomial g _j,ionly have a small amount of ' 1 ' or even complete zero, the inner product so in formula (13) realizes by suing for peace to the tap of ring shift left register, sparse matrix as shown in Figure 5 and vectorial multiplier.Sparse matrix and vectorial multiplier are by t b bit register R _1,1, R _1,2..., R _{1, t}with c multi input XOR gate X _1,1, X _1,2..., X _{1, c}composition.Register R _1,1, R _1,2..., R _{1, e}for loading and ring shift left message segment a ₁, a ₂..., a _e, register R _{1, e+1}, R _{1, e+2}..., R _{1, t}for storing the array section f of [f w] ₁, f ₂..., f _c.Partially connected in Fig. 5 depends on all circular matrix generator polynomials in matrix F.If g _{j, i, m}=1 (1≤m≤b), so message segment a _im bit be connected to XOR gate X _{1, j}.Therefore, register R _{1, i}all taps depend on the nonzero element position of all circular matrix generator polynomials in matrix F i-th piece row, and multi input XOR gate X _{1, j}input depend on matrix F jth block capable in the nonzero element position of all circular matrix generator polynomials.If all circular matrix generator polynomials in F have α ' 1 ', so sparse matrix needs to use (α – c with the multiplier of vector) individual two input XOR gate and calculate f simultaneously _{1, n}, f _{2, n}..., f _c,n.F and w can calculate complete within b clock cycle.Use sparse matrix as follows with the step of vectorial multiplier compute vector f and w:

1st step, input message segment a ₁, a ₂..., a _e, by them respectively stored in register R _1,1, R _1,2..., R _{1, e}in;

2nd step, register R _1,1, R _1,2..., R _{1, e}ring shift left 1 time simultaneously, XOR gate X _1,1, X _1,2..., X _{1, c}respectively XOR result is moved to left into register R _{1, e+1}, R _{1, e+2}..., R _{1, t}in;

3rd step, repeats the 2nd step b time, after completing, and register R _{1, e+1}, R _{1, e+2}..., R _{1, t}the content stored is array section f respectively ₁, f ₂..., f _c, they constitute vector f and w.

Formula (7) implies backward iterative operation, must solve vectorial q and x piecemeal.Definition [q x]=(q ₁, q ₂..., q _c), and be initialized as complete zero.First, q ₁just f is equaled ₁.Secondly, q ₂the 2nd piece of row of matrix Q and vector [q x] ^tlong-pending and f ₂mould 2 He.Then, q ₃the 3rd piece of row of matrix Q and vector [q x] ^tlong-pending and f ₃mould 2 He.Repeat said process, until calculated q _ctill, to iterative circuit after I type as shown in Figure 6.After I type to iterative circuit by c b bit register R _2,1, R _2,2..., R _{2, c}with c-1 multi input modulo 2 adder A _2,2, A _2,3..., A _{2, c}composition.

To calculate q _j(1≤j≤c) is example.The ring shift right version of the normally unit matrix of the nonzero circle matrix in check matrix H.Have N number of nonzero circle matrix during the jth block of hypothesis matrix Q is capable, their ring shift right figure place is s respectively _{j, k1}, s _{j, k2}..., s _{j, kN}(1≤k1, k2 ..., kN<j).Then,

$\begin{array}{c}{q}_j=f_j+I^{\mathrm{rs}\left(s_{j,k+1}\right)}{q}_{k1}+I^{\mathrm{rs}\left(s_{j,k2}\right)}{q}_{k2}+...+I^{\mathrm{rs}\left(s_{j,\mathrm{kN}}\right)}{q}_{\mathrm{kN}}\\ =f_j+q_{k1}^{\mathrm{ls}\left(s_{j,k1}\right)}+q_{k2}^{\mathrm{ls}\left(s_{j,k2}\right)}+...+q_{\mathrm{kN}}^{\mathrm{ls}\left(s_{j,\mathrm{kN}}\right)}\end{array}---\left(14\right)$

Because N is very little, so formula (14) can calculate complete to the multi input modulo 2 adder of input ring shift left by one within 1 clock cycle.Therefore, compute vector [q x] needs c clock cycle altogether.Total β nonzero circle matrix in hypothesis matrix Q, so needs to use (β – c) b two input XOR gate to iterative circuit after I type.

Matrix Q is by c × c b × b rank circular matrix Q _j,kthe array that (1≤j≤c, 1≤k≤c) is formed.Nonzero circle matrix Q _j,ks relative to the ring shift right figure place of b × b rank unit matrix _j,k, 0≤s _j,k<b.For ease of describing, complete zero circular matrix is denoted as s relative to the ring shift right figure place of b × b rank circular matrix _j,k='-'.In figure 6, nonzero circle matrix Q _j,kcorresponding array section q _kbe recycled the s that moves to left _j,kmulti input modulo 2 adder A is sent into behind position _{2, j}in with array section f _jcarry out XOR, the array section that complete zero circular matrix is corresponding does not participate in XOR, A _{2, j}result of calculation be q _j, stored in register R _{2, j}in.Step to iterative circuit compute vector q and x after use I type is as follows:

1st step, input vector section f ₁, by array section q ₁=f ₁stored in register R _2,1in;

2nd step, input vector section f _j, nonzero circle matrix Q _j,kcorresponding array section q _kbe recycled the s that moves to left _j,kmulti input modulo 2 adder A is sent into behind position _{2, j}in with array section f _jcarry out XOR, XOR result q _jbe stored into register R _{2, j}in, wherein, 2≤j≤c, 1≤k<j, 0≤s _j,k<b;

3rd step, with 1 for step-length increases progressively the value changing j, repeats the 2nd step c-1 time, finally, and register R _2,1, R _2,2..., R _{2, c}that store is array section q respectively ₁, q ₂..., q _c, they constitute vectorial q and x.

Formula (9) also implies backward iterative operation, must solve vectorial y piecemeal.Definition y=(y ₁, y ₂..., y _{c – u}), and be initialized as complete zero.First, y ₁the 1st piece of row of matrix Y and vector [p _xy] ^tlong-pending.Secondly, y ₂the 2nd piece of row of matrix Y and vector [p _xy] ^tlong-pending.Repeat said process, until calculated y _{c – u}till, to iterative circuit after II type as shown in Figure 7.After II type to iterative circuit by c b bit register R _4,1, R _4,2..., R _{4, c}with c-u multi input modulo 2 adder A _4,1, A _4,2..., A _{4, c-u}composition.Compute vector y needs altogether (c – u) the individual clock cycle.Total ξ nonzero circle matrix in hypothesis matrix Y, so needs to use (ξ – 2c+2u) b two input XOR gate to iterative circuit after II type.Matrix Y is by (c-u) × c b × b rank circular matrix Y _j,kthe array that (1≤j≤c-u, 1≤k≤c) is formed.Nonzero circle matrix Y _j,ks relative to the ring shift right figure place of b × b rank unit matrix _j,k, 0≤s _j,k<b.Step to iterative circuit compute vector y after use II type is as follows:

1st step, input validation section p ₁, p ₂..., p _u, by them respectively stored in register R _{4, c-u+1}, R _{4, c-u+2}..., R _{4, c}in;

2nd step, nonzero circle matrix Y _j,kcorresponding array section p _kor y _kbe recycled the s that moves to left _j,kmulti input modulo 2 adder A is sent into behind position _{4, j}in carry out XOR, XOR result y _jbe stored into register R _{4, j}in, wherein, 1≤j≤c-u, 1≤k<u+j, 0≤s _j,k<b;

3rd step, with 1 for step-length increases progressively the value changing j, repeats the 2nd step c-u time, finally, and register R _4,1, R _4,2..., R _{4, c-u}that store is array section y respectively ₁, y ₂..., y _c-u, they constitute vectorial y.

The invention provides a kind of high speed QC-LDPC coding method based on four level production lines, be applicable to the QC-LDPC code in communication system, its coding step is described below:

1st step, uses sparse matrix and vectorial multiplier compute vector f and w;

2nd step, to iterative circuit compute vector q and x after use I type;

3rd step, uses high-density matrix to verify vectorial p with the multiplier calculating section of vector _x;

4th step, obtains part to iterative circuit compute vector y, y and vectorial q XOR after using II type and verifies vectorial p _y, thus obtain verifying vectorial p=(p _x, p _y).

Fig. 8 summarizes each coding step of encoder and the hardware resource consumption needed for whole cataloged procedure and processing time.

Be not difficult to find out from Fig. 8, when streamline is full of, whole cataloged procedure needs max (t – c+b, c, u+b) the individual clock cycle altogether, much smaller than e × b the clock cycle needed for the serial encoding method based on c SRAA-I circuit.

In communication system, the existing solution of QC-LDPC encoder needs e × c × b bit ROM, and the present invention needs 2 ^uub bit ROM.Because u is usually very little, so 2 ^uub is much smaller than e × c × b.

As fully visible, compared with traditional serial SRAA method, the present invention has the advantages such as coding rate is fast, memory consumption is few.

The above; be only one of the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the technical scope disclosed by the present invention; the change can expected without creative work or replacement, all should be encompassed within protection scope of the present invention.Therefore, the protection range that protection scope of the present invention should limit with claims is as the criterion.

Claims (6)

1. the high speed QC-LDPC encoder based on four level production lines, the check matrix H of QC-LDPC code is the array be made up of c × t b × b rank circular matrix, wherein, c, t and b are all positive integer, t=e+c, check matrix H is exchanged by ranks and is transformed near lower triangular shape, can be divided into 6 submatrixs $H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right],$ A is made up of (c-u) × e b × b rank circular matrix, B is made up of (c-u) × u b × b rank circular matrix, lower triangular matrix T is made up of (c-u) × (c-u) individual b × b rank circular matrix, C is made up of u × e b × b rank circular matrix, D is made up of u × u b × b rank circular matrix, and E is made up of u × (c-u) individual b × b rank circular matrix, wherein, u is positive integer, Φ=(ET ^-1b+D) ^-1be made up of u × u b × b rank circular matrix, Φ _jby Φ ^tjth block row in u × b rank matrix of forming of all circular matrix generator polynomials, wherein, subscript ^Τwith ^-1represent transposition and inverse respectively, 1≤j≤u, $Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]$ By c × c b × b rank circular matrix Q _j,kform, wherein, I is unit matrix, and 0 is full null matrix, 1≤j≤c, 1≤k≤c, nonzero circle matrix Q _j,ks relative to the ring shift right figure place of b × b rank unit matrix _j,k, wherein, 0≤s _j,k<b, Y=[B T] are by (c-u) × c b × b rank circular matrix Y _j,kform, wherein, 1≤j≤c-u, 1≤k≤c, nonzero circle matrix Y _j,ks relative to the ring shift right figure place of b × b rank unit matrix _j,k, wherein, 0≤s _j,k<b, A and C corresponding informance vector a, matrix B and the vectorial p of the corresponding part verification of D _x, matrix T and E be corresponding remaining verification vector p then _y, verify vectorial p=(p _x, p _y), be one section with b bit, information vector a is divided into e section, i.e. a=(a ₁, a ₂..., a _e), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), p _x=(p ₁, p ₂..., p _u), p _y=(p _u+1, p _u+2..., p _c), vector f is divided into c-u section, i.e. f=(f ₁, f ₂..., f _{c – u}), vectorial w is divided into u section, i.e. w=(f _{c – u+1}, f _{c – u+2}..., f _c), [f w]=(f ₁, f ₂..., f _c), vectorial q is divided into c-u section, i.e. q=(q ₁, q ₂..., q _{c – u}), vector x is divided into u section, i.e. x=(q _{c – u+1}, q _{c – u+2}..., q _c), [q x]=(q ₁, q ₂..., q _c), vectorial y is divided into c-u section, i.e. y=(y ₁, y ₂..., y _{c – u}), it is characterized in that, described encoder comprises following parts:

Sparse matrix and vectorial multiplier, by t b bit register R _1,1, R _1,2..., R _{1, t}with c multi input XOR gate X _1,1, X _1,2..., X _{1, c}composition, for compute vector f and w;

To iterative circuit after I type, by c b bit register R _2,1, R _2,2..., R _{2, c}with c-1 multi input modulo 2 adder A _2,2, A _2,3..., A _{2, c}composition, for compute vector q and x;

High-density matrix and vectorial multiplier, by u look-up table L ₁, L ₂..., L _u, a 2u b bit register R _3,1, R _3,2..., R _3,2uxOR gate X is inputted with u b position two _3,1, X _3,2..., X _{3, u}composition, verifies vectorial p for calculating section _x, look-up table L ₁, L ₂..., L _ustore variable u bit vectors and fixing matrix Φ respectively ₁, Φ ₂..., Φ _uinstitute's likely product;

To iterative circuit after II type, by c b bit register R _4,1, R _4,2..., R _{4, c}with c-u multi input modulo 2 adder A _4,1, A _4,2..., A _{4, c-u}composition, obtains part for compute vector y, y and vectorial q XOR and verifies vectorial p _y, thus obtain verifying vectorial p=(p _x, p _y).

2. a kind of high speed QC-LDPC encoder based on four level production lines according to claim 1, is characterized in that, described sparse matrix is as follows with the step of vectorial multiplier compute vector f and w:

1st step, input message segment a ₁, a ₂..., a _e, by them respectively stored in register R _1,1, R _1,2..., R _{1, e}in;

2nd step, register R _1,1, R _1,2..., R _{1, e}ring shift left 1 time simultaneously, XOR gate X _1,1, X _1,2..., X _{1, c}respectively XOR result is moved to left into register R _{1, e+1}, R _{1, e+2}..., R _{1, t}in;

3rd step, repeats the 2nd step b time, after completing, and register R _{1, e+1}, R _{1, e+2}..., R _{1, t}the content stored is array section f respectively ₁, f ₂..., f _c, they constitute vector f and w.

3. a kind of high speed QC-LDPC encoder based on four level production lines according to claim 1, it is characterized in that, the step to iterative circuit compute vector q and x after described I type is as follows:

1st step, input vector section f ₁, by array section q ₁=f ₁stored in register R _2,1in;

2nd step, input vector section f _j, nonzero circle matrix Q _j,kcorresponding array section q _kbe recycled the s that moves to left _j,kmulti input modulo 2 adder A is sent into behind position _{2, j}in with array section f _jcarry out XOR, XOR result q _jbe stored into register R _{2, j}in, wherein, 2≤j≤c, 1≤k<j, 0≤s _j,k<b;

3rd step, with 1 for step-length increases progressively the value changing j, repeats the 2nd step c-1 time, finally, and register R _2,1, R _2,2..., R _{2, c}that store is array section q respectively ₁, q ₂..., q _c, they constitute vectorial q and x.

4. a kind of high speed QC-LDPC encoder based on four level production lines according to claim 1, is characterized in that, described high-density matrix and vectorial multiplier compute vector p _xstep as follows:

1st step, resets register R _{3, u+1}, R _{3, u+2}..., R _3,2u, input vector section x ₁, x ₂..., x _u, by them respectively stored in register R _3,1, R _3,2..., R _{3, u}in;

2nd step, register R _3,1, R _3,2..., R _{3, u}ring shift left 1 time simultaneously, XOR gate X _3,1, X _3,2..., X _{3, u}respectively to look-up table L ₁, L ₂..., L _uoutput and register R _{3, u+1}, R _{3, u+2}..., R _3,2ucontent carry out XOR, XOR result is recycled to move to left after 1 time deposits back register R respectively _{3, u+1}, R _{3, u+2}..., R _3,2u;

3rd step, repeats the 2nd step b time, after completing, and register R _{3, u+1}, R _{3, u+2}..., R _3,2uthe content stored is verification section p respectively ₁, p ₂..., p _u, they constitute part and verify vectorial p _x.

5. a kind of high speed QC-LDPC encoder based on four level production lines according to claim 1, it is characterized in that, the step to iterative circuit compute vector y after described II type is as follows:

1st step, input validation section p ₁, p ₂..., p _u, by them respectively stored in register R _{4, c-u+1}, R _{4, c-u+2}..., R _{4, c}in;

2nd step, nonzero circle matrix Y _j,kcorresponding array section p _kor y _kbe recycled the s that moves to left _j,kmulti input modulo 2 adder A is sent into behind position _{4, j}in carry out XOR, XOR result y _jbe stored into register R _{4, j}in, wherein, 1≤j≤c-u, 1≤k<u+j, 0≤s _j,k<b;

3rd step, with 1 for step-length increases progressively the value changing j, repeats the 2nd step c-u time, finally, and register R _4,1, R _4,2..., R _{4, c-u}that store is array section y respectively ₁, y ₂..., y _c-u, they constitute vectorial y.

6. the high speed QC-LDPC coding method based on four level production lines, the check matrix H of QC-LDPC code is the array be made up of c × t b × b rank circular matrix, wherein, c, t and b are all positive integer, t=e+c, check matrix H is exchanged by ranks and is transformed near lower triangular shape, can be divided into 6 submatrixs $H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right],$ A is made up of (c-u) × e b × b rank circular matrix, B is made up of (c-u) × u b × b rank circular matrix, lower triangular matrix T is made up of (c-u) × (c-u) individual b × b rank circular matrix, C is made up of u × e b × b rank circular matrix, D is made up of u × u b × b rank circular matrix, and E is made up of u × (c-u) individual b × b rank circular matrix, wherein, u is positive integer, Φ=(ET ^-1b+D) ^-1be made up of u × u b × b rank circular matrix, Φ _jby Φ ^tjth block row in u × b rank matrix of forming of all circular matrix generator polynomials, wherein, subscript ^Τwith ^-1represent transposition and inverse respectively, 1≤j≤u, $Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]$ By c × c b × b rank circular matrix Q _j,kform, wherein, I is unit matrix, and 0 is full null matrix, 1≤j≤c, 1≤k≤c, nonzero circle matrix Q _j,ks relative to the ring shift right figure place of b × b rank unit matrix _j,k, wherein, 0≤s _j,k<b, Y=[B T] are by (c-u) × c b × b rank circular matrix Y _j,kform, wherein, 1≤j≤c-u, 1≤k≤c, nonzero circle matrix Y _j,ks relative to the ring shift right figure place of b × b rank unit matrix _j,k, wherein, 0≤s _j,k<b, A and C corresponding informance vector a, matrix B and the vectorial p of the corresponding part verification of D _x, matrix T and E be corresponding remaining verification vector p then _y, verify vectorial p=(p _x, p _y), be one section with b bit, information vector a is divided into e section, i.e. a=(a ₁, a ₂..., a _e), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), p _x=(p ₁, p ₂..., p _u), p _y=(p _u+1, p _u+2..., p _c), vector f is divided into c-u section, i.e. f=(f ₁, f ₂..., f _{c– u}), vectorial w is divided into u section, i.e. w=(f _{c – u+1}, f _{c – u+2}..., f _c), [f w]=(f ₁, f ₂..., f _c), vectorial q is divided into c-u section, i.e. q=(q ₁, q ₂..., q _{c – u}), vector x is divided into u section, i.e. x=(q _{c – u+1}, q _{c – u+2}..., q _c), [q x]=(q ₁, q ₂..., q _c), vectorial y is divided into c-u section, i.e. y=(y ₁, y ₂..., y _{c – u}), it is characterized in that, described coding method comprises the following steps:

1st step, uses sparse matrix and vectorial multiplier compute vector f and w;

2nd step, to iterative circuit compute vector q and x after use I type;

3rd step, uses high-density matrix to verify vectorial p with the multiplier calculating section of vector _x;

4th step, obtains part to iterative circuit compute vector y, y and vectorial q XOR after using II type and verifies vectorial p _y, thus obtain verifying vectorial p=(p _x, p _y).