CN104538435A - 一种芯片背面开槽的多层封装结构 - Google Patents

一种芯片背面开槽的多层封装结构 Download PDF

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CN104538435A
CN104538435A CN201410842152.6A CN201410842152A CN104538435A CN 104538435 A CN104538435 A CN 104538435A CN 201410842152 A CN201410842152 A CN 201410842152A CN 104538435 A CN104538435 A CN 104538435A
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carrier
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chip body
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杨欢
贾飞
张园
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Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
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Abstract

本发明公开了一种芯片背面开槽的多层封装结构，其特征在于，所述封装结构主要由键合线、子芯片、母芯片、载体、塑封体组成，所述母芯片配置于载体的上表面，键合线连接母芯片和载体，子芯片配置于母芯片的上表面，键合线连接子芯片和载体，塑封体包围键合线、子芯片、母芯片和载体的上表面，所述子芯片背面四周有开槽。所述封装结构封装过程中不需要加硅材垫块，缩短封装流程，提高封装效率及成品率。

Description

一种芯片背面开槽的多层封装结构
技术领域
本发明涉及集成电路封装领域，具体是一种芯片背面开槽的多层封装结构。
背景技术
现有技术中，母芯片小、子芯片大的多层封装技术的结构特征如图1所示：所述多层封装结构主要由键合线A1、硅材垫块A2、母芯片A3、载体A4、子芯片A5、塑封体A6组成，所述母芯片A3配置于载体A4的上表面，键合线A1连接母芯片A3和载体A4，硅材垫块A2连接母芯片A3和在母芯片A3上方的子芯片A5，键合线A1连接子芯片A5和载体A4，塑封体A6包围键合线A1、硅材垫块A2、母芯片A3、子芯片A5和载体A4的上表面。
该现有技术因为要加装硅材垫块，造成制备工艺较为复杂。
发明内容
为了解决上述现有技术存在的问题，本发明提供了一种芯片背面开槽的多层封装结构，其封装过程中不需要加硅材垫块，缩短封装流程，提高封装效率及成品率。
一种芯片背面开槽的多层封装结构，主要由键合线、子芯片、母芯片、载体、塑封体组成，所述母芯片配置于载体的上表面，键合线连接母芯片和载体，子芯片配置于母芯片的上表面，键合线连接子芯片和载体，塑封体包围键合线、子芯片、母芯片和载体的上表面，所述子芯片背面四周有开槽。
所述载体为基板或框架。
所述母芯片直径小于子芯片。
所述塑封体是环氧树脂等塑封材料，也可以是聚酰亚胺等聚合物介质材料。
所述子芯片四周开槽的背面是贴近母芯片的面，开槽区域可以有效避让键合线，开槽深度和宽度根据键合线打线需要设定，可以通过激光或蚀刻的方法进行背面四周开槽。
附图说明
图1为多层封装的现有技术图；
图2为本多层封装结构示意图。
图中，1为键合线A，2为硅材垫块A，3为母芯片A，4为载体A，5为子芯片A，6为塑封体A，7为键合线，8为子芯片，9为母芯片，10为载体，11为塑封体。
具体实施方式
以下结合附图说明对本发明作进一步的详细说明。
如图2所示，一种芯片背面开槽的多层封装结构，主要由键合线7、子芯片8、母芯片9、载体10、塑封体11组成，所述母芯片9配置于载体10的上表面，键合线7连接母芯片9和载体10，子芯片8配置于母芯片9的上表面，键合线7连接子芯片8和载体10，塑封体11包围键合线7、子芯片8、母芯片9和载体10的上表面，所述子芯片8背面四周有开槽。
所述载体10为基板或框架。
所述母芯片9直径小于子芯片8。
所述塑封体11是环氧树脂等塑封材料，也可以是聚酰亚胺等聚合物介质材料。
所述子芯片8四周开槽的背面是贴近母芯片9的面，开槽区域可以有效避让键合线7，开槽深度和宽度根据键合线7打线需要设定，可以通过激光或蚀刻的方法进行背面四周开槽。
与现有技术相比，封装过程中不需要加硅材垫块(spacer)，缩短封装流程，减少粘片及烘箱固化次数、handling次数，降低成本，提高封装效率及成品率。

Claims (5)

1.一种芯片背面开槽的多层封装结构，其特征在于，所述封装结构主要由键合线(7)、子芯片(8)、母芯片(9)、载体(10)、塑封体(11)组成，所述母芯片(9)配置于载体(10)的上表面，键合线(7)连接母芯片(9)和载体(10)，子芯片(8)配置于母芯片(9)的上表面，键合线(7)连接子芯片(8)和载体(10)，塑封体(11)包围键合线(7)、子芯片(8)、母芯片(9)和载体(10)的上表面，所述子芯片(8)背面四周有开槽。
2.根据权利要求1所述的一种芯片背面开槽的多层封装结构，其特征在于，所述载体(10)为基板或框架。
3.根据权利要求1所述的一种芯片背面开槽的多层封装结构，其特征在于，所述母芯片(9)直径小于子芯片(8)。
4.根据权利要求1所述的一种芯片背面开槽的多层封装结构，其特征在于，所述塑封体(11)是环氧树脂塑封材料或者聚酰亚胺聚合物介质材料。
5.根据权利要求1所述的一种芯片背面开槽的多层封装结构，其特征在于，子芯片(8)背面四周的开槽通过激光或蚀刻的方法进行。
CN201410842152.6A 2014-12-30 2014-12-30 一种芯片背面开槽的多层封装结构 Pending CN104538435A (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096754A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
US20110163412A1 (en) * 2007-12-24 2011-07-07 Petari Incorporation Isolator and method of manufacturing the same
CN103354226A (zh) * 2013-06-21 2013-10-16 华进半导体封装先导技术研发中心有限公司 堆叠封装器件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096754A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
US20110163412A1 (en) * 2007-12-24 2011-07-07 Petari Incorporation Isolator and method of manufacturing the same
CN103354226A (zh) * 2013-06-21 2013-10-16 华进半导体封装先导技术研发中心有限公司 堆叠封装器件

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