CN104505366A - Bottom etching method preventing etching of side wall of through-silicon-via - Google Patents
Bottom etching method preventing etching of side wall of through-silicon-via Download PDFInfo
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- CN104505366A CN104505366A CN201410562181.7A CN201410562181A CN104505366A CN 104505366 A CN104505366 A CN 104505366A CN 201410562181 A CN201410562181 A CN 201410562181A CN 104505366 A CN104505366 A CN 104505366A
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- deep hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a bottom etching method preventing etching of the side wall of a through-silicon-via. Before bottom etching of deep holes in wafer level chip scale packaging, through covering a layer of dry film on the back surface of the wafer, and through a photolithographic process, hole bottoms of small holes are exposed, and the hole bottoms are etched, thereby effectively solving problems that the side wall of the deep hole in the wafer level chip scale packaging is etched, that the hole bottom has foreign matter residue, and that the surface material is severely etched. The method simplifies process, and improves product yield, and product reliability is effectively improved.
Description
Technical field
The present invention relates to crystal wafer chip dimension encapsulation (waferlevel chip scale packaging, the WLCSP) technology field of semiconductor chip, specifically relate to a kind of bottom lithographic method preventing silicon from leading to deep hole sidewall etching.
Background technology
Crystal wafer chip dimension encapsulation (wafer level chip scalepackaging, WLCSP) is the one of IC packaged type, and it is that full wafer wafer first encapsulates by one, then cutting obtains the method for packing of single chips.Silicon through hole technology is utilized metal chip pin and PIN electrically to be guided to the back side of wafer, long-pending size constancy after chip package can be realized, and have extremely short electrical transmission range, the chip speed of service is accelerated, power reduction is the advanced technology of current encapsulation field.But the wafer oxidation layer below each chip unit PIN of wafer, be the key factor hindering the electrical back side of chip to derive.How to solve deep hole bottom to window removing wafer oxidation layer, form silicon and lead to deep hole (being generally the hole that aspect ratio is more than or equal to 2:1), expose PIN, ensure again that crystal circle structure performance etc. is unaffected simultaneously, become a difficult problems of crystal wafer chip dimension encapsulation technique.
At present, deep hole bottom is windowed and is generally adopted photoresist coating, after position exposure imaging at the bottom of hole, at the bottom of etachable material etched hole.But the method at the bottom of this etched hole can not prevent the etching of deep hole sidewall, after having etched, photoresist residual in deep hole is not easily removed totally, also can affect successive process.And in etching process, the etch rate on surface is greater than bottom etch rate, although can by thickening surface material thickness, or conditioning equipment parameter etc. improves surface etch degree, its technique relative complex, and not easily accurately controls.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of bottom lithographic method preventing silicon from leading to deep hole sidewall etching, in crystal wafer chip dimension encapsulation process, effectively can improve the vertical etch effect in deep hole, prevent deep hole sidewall from etching, avoid introducing photoresist when deep hole is windowed, solve the problem that photoresist is residual, and etching technics can be hindered the etching of crystal column surface, improve the yield of product, effectively improve the reliability of product.
Technical scheme of the present invention is achieved in that
Prevent silicon from leading to a bottom lithographic method for deep hole sidewall etching, comprise the steps:
A, prepare to comprise the wafer of several chip units, if the functional surfaces of this wafer is front, described functional surfaces has PIN and wafer oxidation layer;
B, carry out thinning to the silicon substrate of wafer rear;
C, on the silicon substrate of wafer rear, cover one deck passivation layer, and form first opening corresponding with the PIN position in functional surfaces on this passivation layer;
D, the first aperture position etching on the silicon substrate of wafer rear form aspect ratio and are more than or equal to the deep hole of 2:1, and make the wafer oxidation layer exposing wafer frontside at the bottom of the hole of deep hole;
E, in passivation layer surface and deep hole, cover a layer insulating;
The surface of the insulating barrier outside f, deep hole after step e covers one deck dry film;
G, dry film after step f form second opening corresponding with deep hole position;
The insulating barrier of the deep hole bottom after h, etch step g and wafer oxidation layer, and expose PIN;
Dry film after i, removal step h;
Covering metal line layer and the protective layer for the protection of metallic circuit layer successively in j, surface of insulating layer after step I and deep hole;
K, protective layer upper shed after step j, and metallic circuit layer after opening plants ball;
Wafer after l, cutting step k, forms single packaged chip.
As a further improvement on the present invention, in step a, the electronic component of integrated circuit that described chip unit is sensitive chip or is made up of analog circuit, digital circuit, when described chip unit is sensitive chip, the functional surfaces of described wafer is provided with cover sheet.
As a further improvement on the present invention, in step g, the diameter of described second opening is less than the diameter of described deep hole.
As a further improvement on the present invention, the generation type of described deep hole is dry etching or wet etching.
As a further improvement on the present invention, thinning mode is carried out for grinding or etching to the silicon substrate of wafer rear.
As a further improvement on the present invention, in step c, by exposure imaging technique, corresponding wafer frontside PIN position forms the first opening over the passivation layer.
As a further improvement on the present invention, in step g, by exposure imaging technique, corresponding deep hole position forms the second opening on the insulating layer.
The invention has the beneficial effects as follows: the invention provides a kind of bottom lithographic method preventing silicon from leading to deep hole sidewall etching, carry out deep hole bottom etching in crystal wafer chip dimension encapsulation before, by covering one deck dry film at the back side of wafer, pass through photoetching process again, described dry film is opened the opening of certain size, expose deep hole bottom to etch, efficiently solve crystal wafer chip dimension encapsulation medium-length hole sidewall to be etched, foreign matter is had to remain at the bottom of hole, surfacing is by the problem seriously etched, simplify technique, improve the yield of product, simultaneously, effectively improve the reliability of product.
Accompanying drawing explanation
Fig. 1 is packaging technology flow chart of the present invention;
Fig. 2 is that invention covers dry film and structural profile schematic diagram thereon after opening;
Fig. 3 is the structural profile schematic diagram after the present invention has encapsulated.
By reference to the accompanying drawings, make the following instructions:
1---silicon substrate 2---wafer oxidation layer
3---PIN 4---passivation layer
5---insulating barrier 6---dry film
7---deep hole 8---second opening
9---Cutting Road 10---metallic circuit layer
11---protective layer 12---solder bump
Embodiment
As shown in Figure 1, Figure 2 and Figure 3, a kind of bottom lithographic method preventing silicon from leading to deep hole sidewall etching, comprises the steps:
A, prepare to comprise the wafer of several chip units, if the functional surfaces of this wafer is front, described functional surfaces has PIN 3 and wafer oxidation layer 2;
B, carry out thinning to the silicon substrate 1 of wafer rear;
C, on the silicon substrate of wafer rear, cover one deck passivation layer 4, and form first opening corresponding with the PIN position in functional surfaces on this passivation layer; During concrete enforcement, cover one deck passivation layer 4 at the silicon substrate of wafer rear, as Other substrate materials, after exposure imaging technique, form the first opening in the top position of the PIN 3 of the correspondence of passivation layer 4, expose the upper shed of deep hole 7 to be etched.
D, the first aperture position etching on the silicon substrate of wafer rear form aspect ratio and are more than or equal to the deep hole 7 of 2:1, and make the wafer oxidation layer exposing wafer frontside at the bottom of the hole of deep hole 7;
E, in passivation layer surface and deep hole 7 cover a layer insulating 5; The face that passivation layer 4 and deep hole 7 can be exposed to air is referred to as first surface, covers a layer insulating 5 on first surface;
The surface of the insulating barrier outside f, deep hole 7 after step e covers one deck dry film 6; Namely one deck dry film 6 is pasted at the horizontal surface of insulating barrier 5.
G, dry film after step f form second opening 8 corresponding with deep hole 7 position;
The insulating barrier at the bottom of deep hole 7 hole after h, etch step g and wafer oxidation layer, and expose PIN 3; Namely after dry film 6 opens the second opening, the etachable material of whole effect is entered by the second opening to be had in the deep hole of insulating barrier, by controlling size and the device parameter of dry film opening, etching effect is showed in vertical direction superior, deep hole bottom is etched, be etched to and remove bottom insulation layer and wafer oxidation layer 2, expose the PIN 3 of suitable area.The etching degree of above-mentioned etching process effects on surface insulating barrier 5 is greater than the etching of insulating barrier 5 at the bottom of hole, and described dry film 6 effectively can stop the thinning of etachable material effects on surface insulating barrier 5.Namely cover top layer by mask, form opening in deep hole position, can deep hole bottom be exposed, simultaneously the etching of energy stop surface material.
Dry film after i, removal step h; Now, the face that insulating barrier 5 surface and wafer oxidation layer 2 and PIN 3 three are exposed to air forms second surface;
Covering metal line layer 10 and the protective layer 11 for the protection of metallic circuit layer successively in j, surface of insulating layer after step I and deep hole; Namely form metallic circuit layer 10 on a second surface, be coated with an insulating material as protective layer 11, prevent metallic circuit from exposing oxidized in atmosphere.
K, protective layer upper shed after step j, and metallic circuit layer after opening plants ball, form solder bump 12;
Wafer after l, cutting step k, forms single packaged chip.Namely cut along the 9 pairs of wafers of the Cutting Road between each chip unit, wafer is cut into single chips.
Preferably, in step a, the electronic component of integrated circuit that described chip unit is sensitive chip or is made up of analog circuit, digital circuit, but its type is not limited thereto.If chip unit is sensitive chip, a cover sheet can be set in the front of wafer and supports cofferdam layer etc., as well-behaved optical glass.
Preferably, in step g, the diameter of described second opening is less than the diameter of described deep hole.Namely this second opening is the circular port that diameter is little compared with deep hole diameter, and concrete opening size can require design according to bottom etching.
Preferably.The generation type of described deep hole is dry etching or wet etching.
Preferably, thinning mode is carried out for grinding or etching to the silicon substrate of wafer rear.
Preferably, in step c, by exposure imaging technique, corresponding wafer frontside PIN position forms the first opening over the passivation layer.
Preferably, in step g, by exposure imaging technique, corresponding deep hole position forms the second opening on the insulating layer.
To sum up, before the present invention carries out deep hole bottom etching in crystal wafer chip dimension encapsulation, by covering one deck dry film at the back side of wafer, then pass through photoetching process, expose deep hole bottom to etch, efficiently solve crystal wafer chip dimension encapsulation medium-length hole sidewall to be etched, have foreign matter to remain (photoresist) at the bottom of hole, surfacing is by the problem seriously etched, simplify technique, improve the yield of product, meanwhile, effectively improve the reliability of product.
Above embodiment is with reference to accompanying drawing, to a preferred embodiment of the present invention will be described in detail.Those skilled in the art by carrying out amendment on various forms or change to above-described embodiment, but when not deviating from essence of the present invention, drops within protection scope of the present invention.
Claims (7)
1. prevent silicon from leading to a bottom lithographic method for deep hole sidewall etching, it is characterized in that: comprise the steps:
A, prepare to comprise the wafer of several chip units, if the functional surfaces of this wafer is front, described functional surfaces has PIN (3) and wafer oxidation layer (2);
B, carry out thinning to the silicon substrate (1) of wafer rear;
C, on the silicon substrate of wafer rear, cover one deck passivation layer (4), and form first opening corresponding with the PIN position in functional surfaces on this passivation layer;
D, the first aperture position etching on the silicon substrate of wafer rear form aspect ratio and are more than or equal to the deep hole (7) of 2:1, and make the wafer oxidation layer exposing wafer frontside at the bottom of the hole of deep hole;
E, in passivation layer surface and deep hole, cover a layer insulating (5);
The surface of the insulating barrier outside f, deep hole after step e covers one deck dry film (6);
G, dry film after step f form second opening (8) corresponding with deep hole position;
The insulating barrier of the deep hole bottom after h, etch step g and wafer oxidation layer, and expose PIN;
Dry film after i, removal step h;
Covering metal line layer (10) and the protective layer (11) for the protection of metallic circuit layer successively in j, surface of insulating layer after step I and deep hole;
K, protective layer upper shed after step j, and metallic circuit layer after opening plants ball, form solder bump (12);
Wafer after l, cutting step k, forms single packaged chip.
2. the bottom lithographic method preventing silicon from leading to deep hole sidewall etching according to claim 1; it is characterized in that: in step a; the electronic component of integrated circuit that described chip unit is sensitive chip or is made up of analog circuit, digital circuit; when described chip unit is sensitive chip, the functional surfaces of described wafer is provided with cover sheet.
3. the bottom lithographic method preventing silicon from leading to deep hole sidewall etching according to claim 1, it is characterized in that: in step g, the diameter of described second opening is less than the diameter of described deep hole.
4. the bottom lithographic method preventing silicon from leading to deep hole sidewall etching according to claim 1, is characterized in that: the generation type of described deep hole is dry etching or wet etching.
5. the bottom lithographic method preventing silicon from leading to deep hole sidewall etching according to claim 1, is characterized in that: carry out thinning mode for grinding or etching to the silicon substrate of wafer rear.
6. the bottom lithographic method preventing silicon from leading to deep hole sidewall etching according to claim 1, it is characterized in that: in step c, by exposure imaging technique, corresponding wafer frontside PIN position forms the first opening over the passivation layer.
7. the bottom lithographic method preventing silicon from leading to deep hole sidewall etching according to claim 1, it is characterized in that: in step g, by exposure imaging technique, corresponding deep hole position forms the second opening on the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410562181.7A CN104505366A (en) | 2014-10-21 | 2014-10-21 | Bottom etching method preventing etching of side wall of through-silicon-via |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410562181.7A CN104505366A (en) | 2014-10-21 | 2014-10-21 | Bottom etching method preventing etching of side wall of through-silicon-via |
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| CN104505366A true CN104505366A (en) | 2015-04-08 |
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| CN201410562181.7A Pending CN104505366A (en) | 2014-10-21 | 2014-10-21 | Bottom etching method preventing etching of side wall of through-silicon-via |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428311A (en) * | 2015-12-16 | 2016-03-23 | 华进半导体封装先导技术研发中心有限公司 | Technology of TSV (Through Silicon Vias) back exposure |
| CN106185787A (en) * | 2015-04-30 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof, electronic installation |
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| US20090212439A1 (en) * | 2008-02-27 | 2009-08-27 | International Business Machines Corporation | Fluorine depleted adhesion layer for metal interconnect structure |
| CN103155115A (en) * | 2010-03-05 | 2013-06-12 | 东京毅力科创株式会社 | Method for producing semiconductor device |
| CN103441097A (en) * | 2013-08-28 | 2013-12-11 | 华进半导体封装先导技术研发中心有限公司 | Etching method of silicon oxide insulating layer of bottom of deep hole |
-
2014
- 2014-10-21 CN CN201410562181.7A patent/CN104505366A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090212439A1 (en) * | 2008-02-27 | 2009-08-27 | International Business Machines Corporation | Fluorine depleted adhesion layer for metal interconnect structure |
| CN103155115A (en) * | 2010-03-05 | 2013-06-12 | 东京毅力科创株式会社 | Method for producing semiconductor device |
| CN103441097A (en) * | 2013-08-28 | 2013-12-11 | 华进半导体封装先导技术研发中心有限公司 | Etching method of silicon oxide insulating layer of bottom of deep hole |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106185787A (en) * | 2015-04-30 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof, electronic installation |
| CN106185787B (en) * | 2015-04-30 | 2018-04-13 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS device and preparation method thereof, electronic device |
| CN105428311A (en) * | 2015-12-16 | 2016-03-23 | 华进半导体封装先导技术研发中心有限公司 | Technology of TSV (Through Silicon Vias) back exposure |
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Application publication date: 20150408 |