CN105514047A - Wafer level packaging method - Google Patents
Wafer level packaging method Download PDFInfo
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- CN105514047A CN105514047A CN201410539146.3A CN201410539146A CN105514047A CN 105514047 A CN105514047 A CN 105514047A CN 201410539146 A CN201410539146 A CN 201410539146A CN 105514047 A CN105514047 A CN 105514047A
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- layer
- fill material
- patterning
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
Abstract
The invention relates to a wafer level packaging method. The packaging method comprises steps of S1: providing a wafer which at least comprises a semiconductor substrate and a metal weld disc arranged on the front face of the semiconductor substrate; S2: carrying out back grinding and patterning on the back of the semiconductor substrate so as to form a silicon through-hole opening to expose the metal weld disc; S3: forming insulation layers on the back of the semiconductor substrate and on the side wall of the silicon through-hole opening; S4: forming re-routing layers on the insulation layers so as to cover the insulation layers; S5: deposing temporary filling materials so as to fill the silicon through-hole opening; and S6: patterning the re-routing layers so as to remove the re-routing layers on two sides of the silicon through-hole opening. According to the invention, after deposing the re-routing layers (RDL AL PVD), the temporary filling materials such as Dry films are selected to fill the silicon through-hole opening, so damage to the re-routing layers RDL is avoided.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to
a kind of wafer-level packaging method.
Background technology
At consumer electronics field, multifunctional equipment is more and more subject to liking of consumer, compared to the simple equipment of function, multifunctional equipment manufacturing process will be more complicated, such as need the chip of integrated multiple difference in functionality in circuit version, thus there is 3D integrated circuit (integratedcircuit, IC) technology, 3D integrated circuit (integratedcircuit, IC) a kind of system-level integrated morphology is defined as, multiple chip is stacking in vertical plane direction, thus save space.
Microelectronic packaging technology is faced with the ski-jump flow that electronic product " high performance-price ratio, high reliability, multi-functional, miniaturized and low cost " development trend is brought.Four limits pin flat packaging (QFP), plastics four limit pin flat packaging (TQFP) are subject to the favor of industry always as the main flow packing forms of surface mounting technology (SMT), but encounter when they carry out the VLSI encapsulating, mount, weld more I/O pin under the 0.3mm pin-pitch limit difficulty being difficult to overcome, especially, when producing in batches, rate of finished products will decline to a great extent.
Therefore the BGA (ball grid array) being I/O with face array, spherical salient point arises at the historic moment, and then develops into again chip size packages (ChipScalePackage is called for short CSP) technology based on it.Adopt
novelcSP technology can guarantee that VLSI realizes minimum dimension encapsulation (size close to bare chip) of chip under the prerequisite of high-performance, high reliability, and relative cost is lower, therefore meets the trend of miniaturization of electronic products.
It is the actuating force of the extensive utilization of wafer-level packaging (Wafer-LevelPackage, WLP) to the pursuit of high performance-price ratio.WLP encapsulation in recent years, because its parasitic parameter is little, performance is high and the advantage that size less (oneself close to the size of chip own), cost constantly decline, is more and more subject to the attention of industry.
Wafer-level packaging (Wafer-LevelPackage) is after wafer preceding working procedure completes, and directly utilizes semiconductor technology to carry out subsequent components encapsulation to wafer, utilize scribe line to construct periphery interconnection, then cutting and separating becomes individual devices.
In the technological process of described wafer-level packaging (Wafer-LevelPackage), mostly select rear silicon through hole (via-lastTSV) technique to encapsulate, not only technique is simple, and cost is low, current very potential method for packing, particularly in the encapsulation of CIS.But after rear silicon through hole (via-lastTSV) etching technics terminates, during layer RDL technique of rerouting, often can there is aperture at the top of cokled surface,
as Fig. 1shown in g, cause, in the wet etching process of RDL, being etched away at the RDL metal wire of the sidewall of silicon through hole TSV, cause disconnection (open) phenomenon of circuit.
Therefore need to be improved further current method for packing, to eliminate the problems referred to above.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that and will try
figurelimit key feature and the essential features of technical scheme required for protection, more do not mean that examination
figuredetermine the protection range of technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides
a kind of wafer-level packaging method, comprising:
Step S1: wafer is provided, described wafer at least comprises Semiconductor substrate and is positioned at the metal pad on described Semiconductor substrate front;
Step S2: backgrind is carried out also to the back side of described Semiconductor substrate
figurepatterning, to form silicon via openings, exposes described metal pad;
Step S3: form insulating barrier on the back side of described Semiconductor substrate and on the sidewall of described silicon via openings;
Step S4: form the layer that reroutes on described insulating barrier, to cover described insulating barrier;
Step S5: deposition temporary fill material, to fill described silicon via openings;
Step S6:
figurereroute described in patterning layer, with remove be positioned at described silicon via openings both sides part described in reroute layer.
Alternatively, in described step S5, described temporary fill material comprises negative photoresist.
Alternatively, in described step S5, the thickness of described temporary fill material is 10-50 micron.
Alternatively, described step S5 comprises:
Step S51: stick described temporary fill material on the described layer that reroutes He in described silicon via openings;
Step S52:
figuretemporary fill material described in patterning, with the described temporary fill material above the layer that reroutes described in removing;
Step S53: cure described temporary fill material, to solidify temporary fill material.
Alternatively, in described step S51, the pressure that sticks of described temporary fill material is 0.5-0.01 atmospheric pressure, and temperature is 50-150 DEG C.
Alternatively, in described step S52, described in
figurepatterning method comprises: select the reticle of silicon through hole to expose described temporary fill material.
Alternatively, after described step S6, described method also comprises further:
Step S7: form passivation layer above the described layer that reroutes, with reroute described in covering layer and described temporary fill material, described passivation layer select polyparaphenylene's benzo two uh azoles or polyimides;
Step S8:
figurepassivation layer described in patterning, to form opening, reroute described in exposed portion layer.
Alternatively, in described step S8,
figureafter passivation layer described in patterning, also comprise the step that described passivation layer is cured further.
Alternatively, after described step S8, described method also comprises further:
Step S9: form solder ball in said opening, for encapsulation;
Step S10: described wafer is cut.
Alternatively, described step S3 comprises:
Step S31: on the back side of described Semiconductor substrate, the sidewall of described silicon via openings and bottom deposit insulation material layer;
Step S32: etch described insulation material layer, to remove the described insulation material layer bottom described silicon via openings, to form described insulating barrier.
Alternatively, described step S6 comprises:
Step S61: formed on the described layer that reroutes
figurethe mask layer of patterning, with the layer that reroutes described in the part exposing described silicon via openings both sides;
Step S62: with described mask layer for mask, reroute described in wet etching layer;
Step S63: remove described mask layer.
The present invention, in order to solve problems of the prior art, provides
a kind of wafer-level packaging method, described method, by after heavy deposition wiring layer (RDLAlPVD), is selected temporary fill material (such as Dryfilm) to fill described silicon via openings, is first protected by TSV opening, then carrying out the described layer RDL that reroute
figurepatterning, to prevent from carrying out at counterweight wiring layer RDL
figurein the process of patterning, etching solution enters in described silicon via openings and causes damage to the layer that reroutes on described opening sidewalls, finally re-uses PBO or PI as passivation layer, and forms solder ball in described passivation layer, to complete described encapsulation.
Accompanying drawing explanation
Of the present invention following
accompanying drawingin this as a part of the present invention for understanding the present invention.
in accompanying drawingshow embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.?
in accompanying drawing,
fig. 1the technical process that a-1g is WLP described in prior art is illustrated
figure;
fig. 2the technical process that a-2g is WLP described in an embodiment of the present invention is illustrated
figure;
fig. 3for the technological process of WLP described in the embodiment of the invention
figure.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.?
in accompanying drawing, in order to clear, the size in Ceng He district and relative size may be exaggerated.Identical from start to finish
accompanying drawingmark represents identical element.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus be described for convenience of description
in figurea shown element or the relation of feature and other element or feature.It should be understood that except
in figurebeyond shown orientation, spatial relationship term is anticipated
figurealso comprise the different orientation of the device in using and operating.Such as, if
in accompanying drawingdevice upset, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative also anticipates
figurecomprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
The technological process of WLP described in prior art
as Fig. 1shown in a-1g, first,
as Fig. 1shown in a, Semiconductor substrate 103 is provided, the interconnection structure being formed with various active device on the semiconductor substrate and being positioned in described Semiconductor substrate, such as be positioned at the metal pad 102 in described Semiconductor substrate 103, one layer tape (tape) 101 is sticked in the front of described semiconductor device, then described semiconductor device reversion is carried out backgrind, to thin the thickness of described Semiconductor substrate.
Then, reference
fig. 1b,
figurethe described Semiconductor substrate 103 that patterning thins, to form opening in described Semiconductor substrate 103, exposes described metal pad 102.
Reference
fig. 1c, the described surface of Semiconductor substrate 103, the bottom of opening and sidewall all form insulating barrier 104, then carry out described insulating barrier 104
figurepatterning, exposes described metal pad 102 with the insulating barrier removing described open bottom.
Reference
fig. 1d, forms the layer 105 that reroutes, and carries out the described layer 105 that reroutes above described insulation 104 and described metal pad 102
figurepatterning, to remove above described metal pad and the part of described insulating barrier 104 both sides reroutes layer 105, to obtain
as Fig. 1shown in d
figurecase.
Reference
fig. 1e, deposition mask layer 106, to cover described Semiconductor substrate 103, wherein said mask layer 106 selects negative photoresist, then carries out described mask layer 106
figurepatterning, with the layer 105 that reroutes described in exposed portion.
Reference
fig. 1f, finally carry out above the layer 105 that reroutes described in exposing, form passivation layer 107 and solder sphere (ball) 108, then utilize semiconductor technology to carry out subsequent components encapsulation to wafer, utilize scribe line to construct periphery interconnection, then cutting and separating becomes individual devices.
Wherein, all there is certain problem in the device performance prepared by described method and yield, described method is easy to the disconnection (open) causing circuit, the present inventor, by a large amount of experiments and analysis, finds that the reason causing circuit to disconnect is being carried out the described layer 105 that reroutes
figurein the process of patterning, use normal photoresist exposure imaging owing to selecting in this step, but after being through baking, find that aperture is arranged at the top that photoresist is being heaved,
as Fig. 1shown in g, cause in the wet etching process of RDL, the etching liquid of RDL enters into silicon through hole TSV, is etched away at the RDL metal wire of the sidewall of silicon through hole TSV, thus causes disconnection (open) phenomenon of circuit.
Owing to there are the problems referred to above in described technique, therefore need to be further improved described method.
Embodiment 1
The present invention, in order to solve prior art Problems existing, provides a kind of new wafer-level packaging method, below in conjunction with
fig. 2a-2g is further described described method.
First, perform step 201, wafer is provided, the metal pad 202 that described wafer at least comprises Semiconductor substrate 203 and is positioned on the front of described Semiconductor substrate 203.
Particularly,
as Fig. 2shown in a, the semi-conducting material that described Semiconductor substrate 203 can select ability conventional, such as can at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Alternatively, can be formed with various active and/or passive device in described Semiconductor substrate 203, the kind of described device is not limited to a certain.
Further, described Semiconductor substrate front is also formed with metal interconnection structure, and such as multiple metal level and through hole are arranged alternately to form described metal interconnection structure, and forms metal pad 202 at the top of described metal interconnect structure.
The top of described metal pad 202 can also form other devices, does not repeat them here, and can arrange according to specific needs.
Perform step 202, backgrind is carried out also to the back side of described Semiconductor substrate 203
figurepatterning, to form silicon via openings, exposes described metal pad 202.
Particularly,
as Fig. 2shown in a, form one layer tape (TAPE) 201 in the front of described wafer, and backgrind is carried out in described Semiconductor substrate 203 reversion, by
fig. 2in a, dotted line position is ground to described solid line position.
Then
figurethe back side of Semiconductor substrate 203 described in patterning, to form silicon via openings, exposes described metal pad 202,
figurethe method of Semiconductor substrate 203 described in patterning is including, but not limited to following example:
First, described Semiconductor substrate 203 is formed
figurethe mask layer of patterning, is formed with opening in described mask layer, such as photoresist layer, then carries out exposure imaging, to form described opening; Then with described mask layer for Semiconductor substrate described in mask etch 203 and the oxide skin(coating) between described metal pad and described Semiconductor substrate, to form described silicon via openings, expose described metal pad 202; Finally remove described mask layer, obtain
as Fig. 2shown in b
figurecase.
Perform step 203, form insulating barrier 204 on the surface of described Semiconductor substrate 203.
as Fig. 2shown in c, the surface of described Semiconductor substrate 203 comprise described Semiconductor substrate the horizontal surface at the back side and the sidewall surfaces of described silicon via openings.
The method forming described insulating barrier 204 comprises: side's (on horizontal plane of Semiconductor substrate), the sidewall of described silicon via openings and bottom deposit insulation material layer on the semiconductor substrate; Etch described insulation material layer, to remove the described insulation material layer bottom described silicon via openings, to form described insulating barrier 204.
Wherein, the insulating material that described insulating barrier 204 can select this area conventional, is not limited to a certain, can selects oxide.
In addition, the deposition process of described insulating barrier 204 can select this area to commonly use, such as, can select CVD.
Perform step 204, described insulating barrier 204 forms the layer 205 that reroutes, to cover described insulating barrier 204.
as Fig. 2shown in d, the layer 205 that reroutes in this step can select conventional electric conducting material, such as, can select metal Ti or Al, but is not limited to this example.
The deposition process of the described layer 205 that reroutes can be selected sputtering method or select PVD deposition process, does not also limit to cited method.
In this step, described in the layer 205 that reroutes be positioned at the top of described insulating barrier 204, do not cover described metal pad.
Perform step 205, deposition temporary fill material 206, to fill described silicon via openings
Particularly,
as Fig. 2shown in d, described temporary fill material comprises negative photoresist.
The thickness of described temporary fill material is 10-50 micron.
The method of deposition temporary fill material 206 comprises:
Step 2051: stick described temporary fill material on the described layer 205 that reroutes He in described silicon via openings;
Step 2052:
figuretemporary fill material described in patterning, with the described temporary fill material above the layer 205 that reroutes described in removing;
Step 2053: cure described temporary fill material, to solidify temporary fill material.
In described step 2051, the pressure that sticks of described temporary fill material is 0.5-0.01 atmospheric pressure, and temperature is 50-150 DEG C.
In described step 2052, described in
figurepatterning method comprises: select the reticle of silicon through hole to carry out exposure imaging to described temporary fill material.
In described step 2052, ultraviolet light (UVbake) is selected to cure or the method for microwave baking (Ovenbake) is cured described temporary fill material.
Interim filler of filling is selected to fill described silicon via openings in this step, so that described silicon via openings is closed, the layer that reroutes on described silicon via openings sidewall is avoided to expose, prevent from causing damage to the layer that reroutes on described silicon via openings sidewall in follow-up wet etching, the performance of described semiconductor device is impacted.
Perform step 206,
figurereroute described in patterning layer 205, with remove be positioned at described silicon via openings both sides part described in reroute layer 205.
Particularly,
as Fig. 2shown in e,
figurethe method of layer 205 of rerouting described in patterning comprises:
Step 2061: formed on the described layer that reroutes
figurethe mask layer of patterning, with the layer 205 that reroutes described in the part exposing described silicon via openings both sides;
Step 2062: with described mask layer for mask, reroute described in wet etching layer 205;
Step 2063: remove described mask layer.
Wherein, in described step 2061, described mask layer selects photoresist layer.
In described step 2062, select the layer 205 that to reroute described in wet etching, to expose the described insulating barrier 204 of part being positioned at described silicon via openings both sides.
In this step owing to being filled with temporary fill material in described silicon via openings, therefore the etching solution of described wet etching can not enter in described silicon through hole, damage can not be caused to the layer that reroutes on described silicon via openings sidewall, therefore can improve performance and the yield of described semiconductor device further.
Perform step 207, above the described layer 205 that reroutes, form passivation layer 207, with reroute described in covering layer 205 and described temporary fill material, and
figurepassivation layer 207 described in patterning, to form opening, reroute described in exposed portion layer 205.
as Fig. 2shown in f, in this step, described passivation layer 207 select polyparaphenylene's benzo two uh azoles (PBO) or polyimides (PI).
Apply in this step penylene benzo two uh the passivation layer of azoles (PBO) or polyimides (PI), with reroute described in covering completely layer 205 and described temporary fill material 206.
Then formed on described passivation layer
figurethe mask layer of patterning, described mask layer is arranged in and is formed with opening, the top of the layer 205 that reroutes described in described opening is positioned at, with described mask layer for passivation layer described in mask etch, to be transferred in described passivation layer by described opening, expose the layer 205 that to reroute described in described part
as Fig. 2shown in f.
figureafter passivation layer 207 described in patterning, also comprise the step that described passivation layer 207 is cured further, such as, select ultraviolet light (UVbake) to cure or the method for microwave baking (Ovenbake) is cured described temporary fill material.
Perform step 208, form solder ball 208 in said opening, for encapsulation,
as Fig. 2shown in g; Finally described wafer is cut.
The method that this area is conventional can be selected in this step, be not limited to a certain, do not repeat them here.
So far, the introduction of the wafer level packaging process of the embodiment of the present invention is completed.After the above step, other correlation step can also be comprised, repeat no more herein.Further, in addition to the foregoing steps, the preparation method of the present embodiment can also comprise other steps among each step above-mentioned or between different steps, and these steps all can be realized by various technique of the prior art, repeat no more herein.
The present invention, in order to solve problems of the prior art, provides
a kind of wafer-level packaging method, described method, by after heavy deposition wiring layer (RDLAlPVD), is selected temporary fill material (such as Dryfilm) to fill described silicon via openings, is first protected by TSV opening, then carrying out the described layer RDL that reroute
figurepatterning, to prevent from carrying out at counterweight wiring layer RDL
figurein the process of patterning, etching solution enters in described silicon via openings and causes damage to the layer that reroutes on described opening sidewalls, finally re-uses PBO or PI as passivation layer, and forms solder ball in described passivation layer, to complete described encapsulation.
fig. 3for preparation technology's flow process of the present invention one semiconductor device described in execution mode particularly
figure, specifically comprise the following steps:
Step S1: wafer is provided, described wafer at least comprises Semiconductor substrate and is positioned at the metal pad on described Semiconductor substrate front;
Step S2: backgrind is carried out also to the back side of described Semiconductor substrate
figurepatterning, to form silicon via openings, exposes described metal pad;
Step S3: form insulating barrier on the back side of described Semiconductor substrate and on the sidewall of described silicon via openings;
Step S4: form the layer that reroutes on described insulating barrier, to cover described insulating barrier;
Step S5: deposition temporary fill material, to fill described silicon via openings;
Step S6:
figurereroute described in patterning layer, with remove be positioned at described silicon via openings both sides part described in reroute layer.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (11)
1. a wafer-level packaging method, comprising:
Step S1: wafer is provided, described wafer at least comprises Semiconductor substrate and is positioned at the metal pad on described Semiconductor substrate front;
Step S2: carry out backgrind and patterning to the back side of described Semiconductor substrate, to form silicon via openings, exposes described metal pad;
Step S3: form insulating barrier on the back side of described Semiconductor substrate and on the sidewall of described silicon via openings;
Step S4: form the layer that reroutes on described insulating barrier, to cover described insulating barrier;
Step S5: deposition temporary fill material, to fill described silicon via openings;
Step S6: reroute described in patterning layer, with remove be positioned at described silicon via openings both sides part described in reroute layer.
2. method according to claim 1, is characterized in that, in described step S5, described temporary fill material comprises negative photoresist.
3. method according to claim 1 and 2, is characterized in that, in described step S5, the thickness of described temporary fill material is 10-50 micron.
4. method according to claim 1 and 2, is characterized in that, described step S5 comprises:
Step S51: stick described temporary fill material on the described layer that reroutes He in described silicon via openings;
Step S52: temporary fill material described in patterning, with the described temporary fill material above the layer that reroutes described in removing;
Step S53: cure described temporary fill material, to solidify temporary fill material.
5. method according to claim 4, is characterized in that, in described step S51, the pressure that sticks of described temporary fill material is 0.5-0.01 atmospheric pressure, and temperature is 50-150 DEG C.
6. method according to claim 4, is characterized in that, in described step S52, described patterning method comprises: select the reticle of silicon through hole to expose described temporary fill material.
7. method according to claim 1, is characterized in that, after described step S6, described method also comprises further:
Step S7: form passivation layer above the described layer that reroutes, with reroute described in covering layer and described temporary fill material, described passivation layer select polyparaphenylene's benzo two uh azoles or polyimides;
Step S8: passivation layer described in patterning, to form opening, reroute described in exposed portion layer.
8. method according to claim 7, is characterized in that, in described step S8, after passivation layer described in patterning, also comprises the step of curing described passivation layer further.
9. method according to claim 7, is characterized in that, after described step S8, described method also comprises further:
Step S9: form solder ball in said opening, for encapsulation;
Step S10: described wafer is cut.
10. method according to claim 1, is characterized in that, described step S3 comprises:
Step S31: on the back side of described Semiconductor substrate, the sidewall of described silicon via openings and bottom deposit insulation material layer;
Step S32: etch described insulation material layer, to remove the described insulation material layer bottom described silicon via openings, to form described insulating barrier.
11. methods according to claim 1, is characterized in that, described step S6 comprises:
Step S61: the mask layer forming patterning on the described layer that reroutes, with the layer that reroutes described in the part exposing described silicon via openings both sides;
Step S62: with described mask layer for mask, reroute described in wet etching layer;
Step S63: remove described mask layer.
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| CN108010837A (en) * | 2017-12-12 | 2018-05-08 | 成都海威华芯科技有限公司 | A kind of dicing lane manufacture craft |
| CN109698136A (en) * | 2017-10-20 | 2019-04-30 | 中芯国际集成电路制造(北京)有限公司 | A kind of encapsulating method and structure of radio frequency SOI chip |
| CN111298853A (en) * | 2020-02-27 | 2020-06-19 | 西人马联合测控（泉州）科技有限公司 | Chip cutting and forming method and wafer |
| CN114899111A (en) * | 2022-04-22 | 2022-08-12 | 宜确半导体（苏州）有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| WO2024063869A1 (en) * | 2022-09-23 | 2024-03-28 | Qualcomm Incorporated | Inductive device structure and process method |
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| CN108010837A (en) * | 2017-12-12 | 2018-05-08 | 成都海威华芯科技有限公司 | A kind of dicing lane manufacture craft |
| CN111298853A (en) * | 2020-02-27 | 2020-06-19 | 西人马联合测控（泉州）科技有限公司 | Chip cutting and forming method and wafer |
| CN111298853B (en) * | 2020-02-27 | 2021-08-10 | 西人马联合测控（泉州）科技有限公司 | Chip cutting and forming method and wafer |
| CN114899111A (en) * | 2022-04-22 | 2022-08-12 | 宜确半导体（苏州）有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN114899111B (en) * | 2022-04-22 | 2023-04-25 | 宜确半导体（苏州）有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| WO2024063869A1 (en) * | 2022-09-23 | 2024-03-28 | Qualcomm Incorporated | Inductive device structure and process method |
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