CN105428311A

CN105428311A - Technology of TSV (Through Silicon Vias) back exposure

Info

Publication number: CN105428311A
Application number: CN201510943453.2A
Authority: CN
Inventors: 冯光建
Original assignee: National Center for Advanced Packaging Co Ltd
Current assignee: National Center for Advanced Packaging Co Ltd
Priority date: 2015-12-16
Filing date: 2015-12-16
Publication date: 2016-03-23

Abstract

The invention provides a technology of TSV (Through Silicon Vias) back exposure. The technology comprises the steps of performing an etching technology on the back of a wafer comprising a TSV conducting post to expose the TSV conducting post, depositing an insulating layer on the back of the whole wafer to cover the TSV conducting post and the back of the wafer with the insulating layer and to allow the thickness of the insulating layer on a side wall of the TSV conducting post to be less than that of the insulating layer on the back of the wafer, performing complete etching on the back of the wafer to expose metal on the side wall of the TSV conducting post, performing front metal deposition on the back of the wafer as a seed layer, conducting a deposited metal layer with the side wall of the TSV conducting post, and performing RDL on the deposited metal layer. The technology has the advantages that the insulating layer is removed on the side wall of the conducting post to expose the metal by the etching technology after depositing the insulating layer by utilizing the characteristics of hard deposition and thinness of the side wall of the conducting post; the technology is free from limitation of different exposed heights of the conducting post and is simple and effective; and a back exposure technology can be adequately solved.

Description

The process that TSV appears at back

Technical field

The present invention relates to technical field of semiconductors, particularly relate to the process appeared in a kind of TSV back.

Background technology

Along with the development of semiconductor technology, the characteristic size of integrated circuit constantly reduces, and device interconnection density improves constantly.Traditional two dimension encapsulation can not meet the demand of industry, and the stacked package mode therefore based on TSV perpendicular interconnection interconnects and superintegrated key technology advantage with its short distance, has led the trend that encapsulation technology develops gradually.

Leading portion TSV technology is made in TSV inside wafer, when using TSV to carry out three-dimensional integration packaging, needing to carry out the thinning TSV of the making back side to TSV substrate and appearing, and the back side conduction realizing TSV is drawn.When TSV back conductive pole exposes, because the metal of conductive pole can polluting wafer, therefore at this moment wait the insulating barrier deposited in TSV technique before being also coated with outside the conductive pole exposed.

Subsequent technique is generally first deposit a layer insulating with vapor phase method wafer back part is protected, and adds a step gold-tinted technique, protects brilliant back surface with photoresistance, then only etches above conductive pole; Or by the mode of grinding, striking off, the insulating barrier on conductive pole is removed, and the height that conductive pole exposes disunity, even high follows low difference more than 10um, like this in grinding or to strike off in process and just very likely cause damage to crystal column surface, or cause the lower conductive pole in some region successfully not removed insulating barrier, cause follow-up interconnected inefficacy.

Summary of the invention

The object of the invention is to overcome the deficiencies in the prior art, the process appeared in a kind of TSV back is provided, after depositing the insulating layer, with etching technics, insulating barrier is carried out to the sidewall of conductive pole and remove, to ensure follow-up interconnected reliability.

According to technical scheme provided by the invention, the process appeared in described TSV back, comprises the following steps:

A. carry out etching technics to the wafer back part containing TSV conductive pole, expose TSV conductive pole, now TSV conductive pole directly exposes or also has the first insulating barrier to cover;

B. carry out insulating layer deposition to whole wafer rear, TSV conductive pole and wafer rear are all covered by the second insulating barrier, and now the thickness of insulating layer of TSV conductive pole sidewall is less than the thickness of insulating layer of wafer rear;

C. whole etching is carried out to wafer rear, make the sidewall of TSV conductive pole expose metal;

D. carry out front metal deposition to wafer back part, as Seed Layer, the metal level of deposition, with the conducting of TSV conductive pole sidewall, is finally RDL on the metal level of deposition.

Concrete, expose conductive post height in step a at 1um ~ 30um.

Concrete, in step b, the second insulating barrier adopts Meteorological Act deposition, or adopts plating, spray-bonding craft deposition.Described second thickness of insulating layer is at 500nm ~ 50um.

Concrete, after step c etching, wafer rear insulating barrier residual thickness is at 100nm ~ 30um.

Concrete, the metal level of steps d can be titanium copper or aluminium lamination.

Advantage of the present invention is: the present invention utilizes the more difficult deposition of conductive pole sidewall, the feature that sidewall is thinner, after depositing the insulating layer, carry out insulating barrier with etching technics to the sidewall of conductive pole to remove, expose metal, this method, not by the restriction that conductive pole ride out differs, simply effectively, can be properly settled back and to appear technique.

Accompanying drawing explanation

Fig. 1 has carried out back to appear the wafer schematic diagram of technique.

Fig. 2 carries out insulating layer deposition schematic diagram to whole wafer rear.

Fig. 3 etches insulating barrier, exposes TSV conductive pole sidewall schematic diagram.

Fig. 4 carries out front metal deposition schematic diagram to wafer back part.

Embodiment

Below in conjunction with drawings and Examples, the invention will be further described.

The process appeared in a kind of TSV back that the present invention introduces comprises the following steps:

One, to appear the wafer of technique to carrying out back, carrying out insulating layer deposition.

As shown in Figure 1, etching technics is carried out to wafer (wafer frontside makes the pad 2 with the TSV conductive pole 1 UNICOM) back containing TSV conductive pole 1, expose TSV conductive pole 1, now TSV conductive pole 1 can also have the first insulating barrier 3 to cover above, also can be the insulating barrier above TSV conductive pole 1 has been removed, expose metal column; Now expose TSV conductive pole 1 height at 1um ~ 30um;

As shown in Figure 2, insulating layer deposition is carried out to whole wafer rear, TSV conductive pole 1 and wafer rear are all covered by the second insulating barrier 4; The second insulating barrier 4 herein can be the inorganic oxide such as silica, silicon nitride of Meteorological Act deposition, and also can be organic substance such as plating photoresistance, spray-bonding craft photoresistance etc., their Main Function be isolation wafer back part, plays the effect of insulation; Second insulating barrier 4 thickness is at 500nm ~ 50um.

The second insulating barrier 4 herein, due to the more difficult deposition of TSV conductive pole 1 sidewall, therefore there will be sidewall insulating layers less, the trend that surface thickness is larger.High Resistivity Si without depositing insulating layer, directly can carry out subsequent metal interconnection technology.

Two, insulating barrier is etched, expose the sidewall of TSV conductive pole 1.

As shown in Figure 3, whole etching is carried out to wafer rear, makes the sidewall of TSV conductive pole 1 expose metal.Etching can be wet etching herein, also can be dry etching; After wafer rear insulating barrier etching, residual thickness is at 100nm ~ 30um.

Three, carry out front metal deposition, make metal follow the conducting of TSV conductive pole 1 sidewall, on depositing metal layers 5, be finally RDL(reroute layer).

As shown in Figure 4, carry out front metal deposition to wafer back part, as Seed Layer, the metal level 5 of deposition can be titanium copper, also can be aluminium lamination; The metal interconnection that this metal level 5 and TSV conductive pole 1 expose; Follow-uply carry out follow-up RDL with this Seed Layer for substrate and make, complete metal interconnection.

Due to the present invention in process to TSV conductive pole appear part side etch, the sidewall of TSV conductive pole is made to expose metal, complete follow-up interconnected again, therefore not by the restriction that conductive pole ride out differs, effective metal interconnection can be completed to each TSV conductive pole.

To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, the present invention can be realized in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.

Claims

The process that 1.TSV appears at back, is characterized in that, comprise the following steps:

A. carry out etching technics to the wafer back part containing TSV conductive pole (1), expose TSV conductive pole (1), now TSV conductive pole (1) directly exposes or also has the first insulating barrier (3) to cover;

B. carry out insulating layer deposition to whole wafer rear, TSV conductive pole (1) and wafer rear are all covered by the second insulating barrier (4), and now the thickness of insulating layer of TSV conductive pole (1) sidewall is less than the thickness of insulating layer of wafer rear;

C. whole etching is carried out to wafer rear, make the sidewall of TSV conductive pole (1) expose metal;

D. carry out front metal deposition to wafer back part, as Seed Layer, the metal level (5) of deposition, with TSV conductive pole (1) sidewall conducting, is finally RDL on the metal level (5) of deposition.
2. the TSV back as claimed in claim 1 process of appearing, is characterized in that, expose conductive post height at 1um ~ 30um in step a.
3. the TSV back as claimed in claim 1 process of appearing, it is characterized in that, in step b, the second insulating barrier (4) adopts Meteorological Act deposition, or adopts plating, spray-bonding craft deposition.
4. the TSV back as claimed in claim 1 process of appearing, it is characterized in that, described second insulating barrier (4) thickness is at 500nm ~ 50um.
5. the TSV back as claimed in claim 1 process of appearing, it is characterized in that, after step c etching, wafer rear insulating barrier residual thickness is at 100nm ~ 30um.
6. the TSV back as claimed in claim 1 process of appearing, it is characterized in that, the metal level (5) of steps d is titanium copper or aluminium lamination.