CN106486049A - Shift register cell, driving method, GOA circuit and display device - Google Patents
Shift register cell, driving method, GOA circuit and display device Download PDFInfo
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- CN106486049A CN106486049A CN201710003953.7A CN201710003953A CN106486049A CN 106486049 A CN106486049 A CN 106486049A CN 201710003953 A CN201710003953 A CN 201710003953A CN 106486049 A CN106486049 A CN 106486049A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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Abstract
The present invention provides a kind of shift register cell, driving method, GOA (driving of array base palte row) circuit and display device.The shift register cell includes：Starting module；Pull-up node current potential maintenance module；Memory module；Carry signal output module, it is connected with second clock signal output part for the control carry signal output end when the current potential of pull-up node is for high level, when the first clock signal output terminal exports high level, control carry signal output end is connected with the first low level output end；And, gate drive signal output module, it is connected with high level output end for the control gate drive signal output end when the current potential of pull-up node is for high level, when the first clock signal output terminal exports high level, control gate drive signal output end is connected with the second low level output end；First clock signal and second clock signal inversion.The present invention solve prior art GOA circuit noise is obvious, power consumption is high, and the larger problem of leakage current.
Description
Technical field
The present invention relates to show actuation techniques field, more particularly to a kind of shift register cell, driving method, GOA electricity
Road and display device.
Background technology
With current display floater resolution ratio more and more higher, the raster data model of display floater and the output of source drive are relatively
Many, the increase of drive circuit length can increase Bonding (binding).In order to solve the more and more employings of problem above panel vendor
GOA (Gate On Array, array base palte row drive) technology, so not only can save gate driver circuit Bonding, also
Display floater narrow frame design can be realized.
Existing GOA circuit design is compared with complicated (clock signal is many, and the TFT (thin film transistor (TFT)) of employing is many), noise at present
Substantially, power consumption is high.While the threshold voltage vt h of IGZO (indium gallium zinc oxide, indium gallium zinc oxide) TFT
May be negative, therefore be designed it is possible that TFT cannot be fastened using traditional GOA, the larger problem of leakage current.
Content of the invention
Present invention is primarily targeted at providing a kind of shift register cell, driving method, GOA circuit and showing dress
Put, solve prior art GOA circuit noise is obvious, power consumption is high, and the larger problem of leakage current.
In order to achieve the above object, the invention provides a kind of shift register cell, including：
Starting module, maintains section with the first clock signal output terminal, initial signal output end, pull-up node and pull-up respectively
Point connection, for when first clock signal output terminal exports high level, control the initial signal output end, described on
Node and the pull-up is drawn to maintain node to be connected with each other；
Pull-up node current potential maintenance module, maintains node to be connected with the pull-up node and the pull-up respectively, for
It is high level that the output stage controls the pull-up to maintain the current potential of node when the current potential of the pull-up node is for high level, to keep away
The current potential for exempting from the pull-up node is reduced due to electric leakage；
Memory module, is connected between the pull-up node and carry signal output end；
Carry signal output module, respectively with the pull-up node, the carry signal output end, first clock letter
The connection of number output end, second clock signal output part and the first low level output end, for the current potential when the pull-up node be
The carry signal output end is controlled to be connected with the second clock signal output part during high level, when first clock signal
The carry signal output end is controlled to be connected with the first low level output end during output end output high level；And,
Gate drive signal output module, respectively with the pull-up node, high level output end, gate drive signal output
End is connected with the second low level output end, for controlling the raster data model to believe when the current potential of the pull-up node is for high level
Number output end is connected with the high level output end, controls the grid when first clock signal output terminal exports high level
Pole drive signal output end is connected with the second low level output end；
First clock signal and second clock signal inversion.
During enforcement, the first low level of the first low level output end output is less than the second of the output of the second low level output end
Low level.
During enforcement, the starting module includes：
The first transistor, grid are connected with first clock signal output terminal, and the first pole is connected with initial signal output end
Connect, the second pole maintains node to be connected with the pull-up；And,
Transistor seconds, grid are connected with first clock signal output terminal, and the first pole maintains node with the pull-up
Connection, the second pole is connected with the pull-up node；
The memory module includes：Storage capacitance, first end are connected with the pull-up node, and the second end is defeated with carry signal
Go out end connection.
During enforcement, the pull-up node current potential maintenance module includes：
Third transistor, grid are connected with the pull-up node, and the first pole maintains node to be connected with the pull-up, the second pole
It is connected with the second clock signal output part.
During enforcement, the carry signal output module includes：
4th transistor, grid are connected with the pull-up node, and the first pole is connected with the second clock signal output part,
Second pole is connected with the carry signal output end；And,
5th transistor, grid are connected with first clock signal output terminal, and the first pole is exported with the carry signal
End connection, the second pole is connected with the first low level output end；
The breadth length ratio of the 4th transistor is more than the breadth length ratio of the 5th transistor.
During enforcement, the carry signal output module includes：
6th transistor, grid are connected with the pull-up node, and the first pole is connected with the high level output end, the second pole
It is connected with the gate drive signal output end；And,
7th transistor, grid are connected with first clock signal output terminal, the first pole and the gate drive signal
Output end connects, and the second pole is connected with the second low level output end；
The breadth length ratio of the 6th transistor is more than the breadth length ratio for making a reservation for the 7th transistor.
During enforcement, the first transistor, the transistor seconds, the third transistor, the 4th transistor, institute
It is all n-type transistor to state the 5th transistor, the 6th transistor and the 7th transistor.
Present invention also offers a kind of driving method of shift register cell, is applied to above-mentioned shift register list
Unit, including：In each display cycle,
In initial time section, the first clock signal and initial signal are all high level, and second clock signal is low level, rises
Beginning module control initial signal output end, pull-up node and pull-up maintain node to be connected with each other, to control the pull-up node
Current potential is high level, and carry signal output module control carry signal output end exports the first low level, and gate drive signal is defeated
Go out module control gate drive signal output end and export the second low level；
In output time section, the first clock signal and initial signal are all low level, and second clock signal is high level, enters
Position signal output module control carry signal output end output high level, memory module bootstrapping draw high the electricity of the pull-up node
Position, it is high level that the pull-up node current potential maintenance module control pull-up maintains the current potential of node, so as to avoid the pull-up section
The current potential of point is reduced due to electric leakage；
In resetting time section, the first clock signal is high level, and initial signal and second clock signal are all low level, rises
Beginning module control initial signal output end, pull-up node and pull-up maintain node to be connected with each other, so that the pull-up node
Current potential is low level, and carry signal output module controls carry signal output end output first under the control of the first clock signal
Low level, gate drive signal output module control gate drive signal output end export the second low level.
Present invention also offers a kind of GOA circuit, including the above-mentioned shift register cell of multiple cascades,
In addition to first order shift register cell, per one-level shift register cell initial signal output end all with
The carry signal output end connection of adjacent upper level shift register cell.
Present invention also offers a kind of display device, including above-mentioned GOA circuit.
Compared with prior art, shift register cell of the present invention, driving method, GOA circuit and display device
Control carry signal output end to export the first low level in initial period by carry signal output module, believed by raster data model
Number output module control gate drive signal output end exports the second low level, it is to avoid noise jamming；Described in the embodiment of the present invention
Shift register cell output the stage by pull-up node maintenance module control pull-up maintain node current potential be high level,
So as to avoid electric leakage；Also, the gate drive signal output mould in the shift register cell described in the embodiment of the present invention
Block is connected with high level output end, is supplied using high level direct current, reduces dynamic power consumption.
Description of the drawings
Fig. 1 is the structure chart of the shift register cell described in the embodiment of the present invention；
Fig. 2 is the structure chart of the shift register cell described in another embodiment of the present invention；
Fig. 3 is the circuit diagram of a specific embodiment of shift register cell of the present invention；
Fig. 4 is the working timing figure of the specific embodiment of present invention shift register cell as shown in Figure 3；
Fig. 5 is the structure chart of the GOA circuit described in the embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As shown in figure 1, the shift register cell described in the embodiment of the present invention includes：
Starting module 11, respectively with the first clock signal output terminal CLK1, the initial signal output of output initial signal STV
End, pull-up node PU and pull-up maintain node PUCN connection, for when the high electricity of the first clock signal output terminal CLK1 output
At ordinary times, the initial signal output end, pull-up node PU and the pull-up is controlled to maintain node PUCN to be connected with each other；
Pull-up node current potential maintenance module 12, maintains node PUCN to connect with pull-up node PU and the pull-up respectively
Connect, for controlling the pull-up to maintain the electricity of node PUCN when the current potential of pull-up node PU is for high level in the output stage
Position is high level, is reduced due to electric leakage with the current potential that avoids pull-up node PU；
Memory module 13, is connected between pull-up node PU and carry signal output end CR；
Carry signal output module 14, respectively with pull-up node PU, carry signal output end CR, described first
Clock signal output terminal CLK1, second clock signal output part CLK2 and the first low level output of the first low level VSSL of output
End connection, for controlling carry signal output end CR with described second when the current potential of pull-up node PU is for high level
Clock signal output terminal CLK3 connects, and controls the carry to believe when the first clock signal output terminal CLK1 exports high level
Number output end CR is connected with the first low level output end of the first low level VSSL of the output；And,
Gate drive signal output module 15, respectively with pull-up node PU, the high level output of output high level VDD
End, gate drive signal output end OUT are connected with the second low level output end of the second low level VSS of output, for when described
Control gate drive signal output end OUT and the output high level VDD's when the current potential of pull-up node PU is for high level
High level output end connects, and controls the gate drive signal when the first clock signal output terminal CLK1 exports high level
Output end OUT is connected with the second low level output end of the second low level VSS of the output；
First clock signal of CLK1 output and the second clock signal inversion of CLK2 output.
Shift register cell described in the embodiment of the present invention includes starting module, pull-up node maintenance module, storage mould
Block, carry signal output module and gate drive signal output module；Shift register cell knot described in the embodiment of the present invention
Structure is simple, can reduce signal noise, reduce power consumption, reduce leakage current.
In the specific implementation, the shift register cell described in the embodiment of the present invention is defeated by carry signal in initial period
Go out module control carry signal output end and the first low level is exported, letter is driven by gate drive signal output module control gate
Number output end exports the second low level, it is to avoid noise jamming；Shift register cell described in the embodiment of the present invention is in output rank
It is high level that section maintains the current potential of node by pull-up node maintenance module control pull-up, so as to avoid electric leakage (as figure 3 below
Shown, in the output stage, the grid potential of T2 is low level, now arranges the current potential of the source electrode (i.e. pull-up maintains node) of T2
Can ensure that T2 disconnects for high level, so as to avoid electric leakage)；Also, in the shift register cell described in the embodiment of the present invention
Gate drive signal output module be connected with high level output end, using VDD direct current supply, reduce dynamic power consumption.
Preferably, the first low level VSSL of the first low level output end output is less than the output of the second low level output end
Second low level VSS.
Shift register cell described in the embodiment of the present invention is using two rank low levels, i.e. the first low level VSSL less than the
Two low levels VSS, as initial signal STV of this grade is provided by carry signal output end CR of adjacent upper level, and on
Node PU is drawn to be provided by initial signal STV in the current potential of initial period, therefore the grid electricity of the T6 in initial period Fig. 2
Position is the first low level VSSL, and the source potential of T6 is the second low level VSS, and the gate source voltage of T6 is less than 0, then can ensure that
Initial period T6 disconnects, it is to avoid electric leakage.
Shift register cell described in the embodiment of the present invention adopts doubleclocking control technology and two rank low voltage designs,
Wherein CR provides initial signal for adjacent next stage shift register cell.
Specifically, as shown in Fig. 2 the starting module 11 includes：
The first transistor T1, grid are connected with the first clock signal output terminal CLK1, and the first pole is believed with output starting
The initial signal output end connection of number STV, the second pole maintains node PUCN to be connected with the pull-up；And,
Transistor seconds T2, grid are connected with the first clock signal output terminal CLK1, and the first pole is tieed up with the pull-up
The point PUCN that serves as a diplomatic envoy connects, and the second pole is connected with pull-up node PU；
The memory module includes：Storage capacitance C, first end are connected with pull-up node PU, and the second end is believed with carry
The connection of number output end CR.
In the embodiment shown in Figure 2, T1 and T2 are n-type transistor, and when the first extremely source electrode, second extremely leaks
Pole；When first extremely drains, the second extremely source electrode.
Specifically, the pull-up node current potential maintenance module can include：
Third transistor, grid are connected with the pull-up node, and the first pole maintains node to be connected with the pull-up, the second pole
It is connected with the second clock signal output part.
Specifically, the carry signal output module can include：
4th transistor, grid are connected with the pull-up node, and the first pole is connected with the second clock signal output part,
Second pole is connected with the carry signal output end；And,
5th transistor, grid are connected with first clock signal output terminal, and the first pole is exported with the carry signal
End connection, the second pole is connected with the first low level output end；
The breadth length ratio of the 4th transistor is more than the breadth length ratio of the 5th transistor, so that exporting stage carry
Signal output part can be with Full-swing output second clock signal.
Specifically, the carry signal output module can include：
6th transistor, grid are connected with the pull-up node, and the first pole is connected with the high level output end, the second pole
It is connected with the gate drive signal output end；And,
7th transistor, grid are connected with first clock signal output terminal, the first pole and the gate drive signal
Output end connects, and the second pole is connected with the second low level output end；
The breadth length ratio of the 6th transistor is so driven in output phase gate more than the breadth length ratio of the 7th transistor
Dynamic signal output part can be extremely low with Full-swing output high level VDD, power consumption, and noise is little.
In the specific implementation, the first transistor, the transistor seconds, the third transistor, the 4th crystalline substance
Body pipe, the 5th transistor, the 6th transistor and the 7th transistor are all n-type transistor.
Shift register cell of the present invention is described below by a specific embodiment.
As shown in figure 3, a specific embodiment of shift register cell of the present invention includes starting module, pull-up section
Point current potential maintenance module, memory module, carry signal output module and gate drive signal output module, wherein,
The starting module includes：
The first transistor T1, grid are connected with the first clock signal output terminal CLK1, are drained and output initial signal STV
Initial signal output end connects, and source electrode maintains node PUCN to be connected with pull-up；And,
Transistor seconds T2, grid are connected with the first clock signal output terminal CLK1, are drained and are maintained with the pull-up
Node PUCN connects, and source electrode is connected with pull-up node PU；
The memory module includes：Storage capacitance C, first end are connected with pull-up node PU, and the second end is believed with carry
The connection of number output end CR；
The pull-up node current potential maintenance module includes：
Third transistor T3, grid are connected with pull-up node PU, and the first pole maintains node PUCN to connect with the pull-up
Connect, the second pole is connected with second clock signal output part CLK2；
The carry signal output module includes：
4th transistor T4, grid are connected with pull-up node PU, the first pole and the second clock signal output part
CLK2 connects, and the second pole is connected with carry signal output end CR；And,
5th transistor T5, grid are connected with the first clock signal output terminal CLK1, and the first pole is believed with the carry
The connection of number output end CR, the first low level VSSL is accessed in the second pole；
The breadth length ratio of the 4th transistor T4 is more than predetermined breadth length ratio.
The carry signal output module includes：
6th transistor T6, grid are connected with pull-up node PU, and high level VDD, the second pole and institute are accessed in the first pole
State the connection of gate drive signal output end OUT；And,
7th transistor T7, grid are connected with the first clock signal output terminal CLK1, and the first pole is driven with the grid
Dynamic signal output part OUT connection, the second low level VSS is accessed in the second pole；
The breadth length ratio of the 6th transistor is more than predetermined breadth length ratio.
In the specific embodiment of the shift register cell shown in Fig. 3, all of transistor is all n-type transistor.
As shown in figure 4, the specific embodiment of present invention shift register cell as shown in Figure 3 is operationally,
In initial time section t1, CLK1 exports high level, and STV is high level, and CLK2 exports low level, T1, T2, T5 and T7
All open.In initial time section t1, initial signal STV being write by T1 and T2, the voltage of pull-up node PU being lifted, while passing through
T5 and T7 are opened, and the current potential of the gate drive signal of the current potential of the carry signal of CR output and OUT output is pulled down to respectively
VSSL, VSS, set low the current potential of the current potential of PUCN and the gate drive signal of OUT output, it is to avoid noise jamming again；
In output time section t2, CLK1 exports low level, and STV is low level, and CLK2 exports high level, and T3, T4 and T6 are
Open；As in initial time section t1, potential rise your pupil of PU is opened with opening T4, T4, so that the current potential of PUCN is raised,
As Capacitance Coupled is acted on, the current potential of the carry signal exported with CR is raised, and the current potential of PU is accordingly raised.Grid due to T6
It is connected with PU, so in output time section t2, T6 is opened, the current potential of the gate drive signal of OUT output is high level；Need
Illustrate, T3 has the effect of the current potential for keeping PU, reduce electric leakage；
In resetting time section t3, CLK1 exports high level, and STV is low level, and CLK2 is exported low level, beaten by T5 and T7
Open, the current potential of the carry signal that CR is exported, the current potential of the gate drive signal of OUT output are pulled down to VSSL, VSS respectively, will
The current potential of the gate drive signal of the current potential of the carry signal of CR output and OUT output is set low again.
In the embodiment shown in fig. 3, breadth length ratio of the breadth length ratio of T4 more than T5, the breadth length ratio of T6 are long more than the width of T7
Than.
In the specific implementation, VSSL can can be 25V for -5V, VDD for -10V, VSS, when STV is high level
When, STV can be 25V, and when STV is for low level, STV can be -10V, when CLK1 exports high level, the first clock signal
Can be 25V, when CLK1 exports low level, the first clock signal can be -10V；When CLK2 exports high level, when second
Clock signal can be 25V, and when CLK2 exports low level, second clock signal can be -10V.According to the result of emulation, this
Operationally, the current potential for being increased to the carry signal of 10V, CR output in the current potential of t1, PU is set to bright embodiment as shown in Figure 3
The current potential of the low gate drive signal for being for about -10V, OUT output is set low for about -2.5V；31V is increased in the current potential of t2, PU,
It is 25V that the current potential of the carry signal of CR output is about the current potential of the gate drive signal of 18V, OUT output, and now T6 is beaten completely
Open, OUT almost Full-swing output VDD, power consumption are extremely low, and in drive circuit works, noise is minimum.
The driving method of the shift register cell described in the embodiment of the present invention, is applied to above-mentioned shift register list
Unit；The driving method includes：In each display cycle,
In initial time section, the first clock signal and initial signal are all high level, and second clock signal is low level, rises
Beginning module control initial signal output end, pull-up node and pull-up maintain node to be connected with each other, to control the pull-up node
Current potential is high level, and carry signal output module control carry signal output end exports the first low level, and gate drive signal is defeated
Go out module control gate drive signal output end and export the second low level；
In output time section, the first clock signal and initial signal are all low level, and second clock signal is high level, enters
Position signal output module control carry signal output end output high level, memory module bootstrapping draw high the electricity of the pull-up node
Position, it is high level that the pull-up node current potential maintenance module control pull-up maintains the current potential of node, so as to avoid the pull-up section
The current potential of point is reduced due to electric leakage；
In resetting time section, the first clock signal is high level, and initial signal and second clock signal are all low level, rises
Beginning module control initial signal output end, pull-up node and pull-up maintain node to be connected with each other, so that the pull-up node
Current potential is low level, and carry signal output module controls carry signal output end output first under the control of the first clock signal
Low level, gate drive signal output module control gate drive signal output end export the second low level.
GOA circuit described in the embodiment of the present invention includes the above-mentioned shift register cell of multiple cascades,
In addition to first order shift register cell, per one-level shift register cell initial signal output end all with
The carry signal output end connection of adjacent upper level shift register cell.
As shown in figure 5, be numbered S1 for first order shift register cell, be numbered S2 for second level shift LD
Device unit, be numbered S3 for third level shift register cell, be numbered S4 for fourth stage shift register cell, even number
First clock signal output terminal CLK1 of level shift register cell accesses second clock signal clk2, even level shift register
The second clock signal output part CLK2 of unit accesses the first clock signal clk1, in addition to S1, per one-level shift register
The carry signal output end of unit provides initial signal for adjacent next stage shift register cell, and in Figure 5, OUT1 is first
Level gate drive signal output end, CR1 are first order carry signal output end, and OUT2 is exported for second level gate drive signal
End, CR2 are second level carry signal output end, and OUT3 is third level gate drive signal output end, and CR3 is believed for third level carry
Number output end, OUT4 are fourth stage gate drive signal output end, and CR4 is fourth stage carry signal output end.
Display device described in the embodiment of the present invention includes above-mentioned GOA circuit.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, on the premise of without departing from principle of the present invention, some improvements and modifications can also be made, these improvements and modifications
Should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of shift register cell, it is characterised in that include：
Starting module, maintains node to connect with the first clock signal output terminal, initial signal output end, pull-up node and pull-up respectively
Connect, for when first clock signal output terminal exports high level, controlling the initial signal output end, the pull-up section
Point and the pull-up maintain node to be connected with each other；
Pull-up node current potential maintenance module, maintains node to be connected with the pull-up node and the pull-up, in output respectively
It is high level that stage controls the pull-up to maintain the current potential of node when the current potential of the pull-up node is for high level, to avoid
The current potential for stating pull-up node is reduced due to electric leakage；
Memory module, is connected between the pull-up node and carry signal output end；
Carry signal output module, defeated with the pull-up node, the carry signal output end, first clock signal respectively
Go out the connection of end, second clock signal output part and the first low level output end, be high electricity for the current potential when the pull-up node
The carry signal output end is controlled to be connected with the second clock signal output part at ordinary times, when first clock signal is exported
The carry signal output end is controlled to be connected with the first low level output end during the output high level of end；And,
Gate drive signal output module, respectively with the pull-up node, high level output end, gate drive signal output end with
Second low level output end connects, for controlling the gate drive signal defeated when the current potential of the pull-up node is for high level
Go out end to be connected with the high level output end, control when first clock signal output terminal exports high level the grid to drive
Dynamic signal output part is connected with the second low level output end；
First clock signal and second clock signal inversion.
2. shift register cell as claimed in claim 1, it is characterised in that the first of the first low level output end output is low
Level is less than the second low level of the second low level output end output.
3. shift register cell as claimed in claim 1 or 2, it is characterised in that the starting module includes：
The first transistor, grid are connected with first clock signal output terminal, and the first pole is connected with initial signal output end, the
Two poles maintain node to be connected with the pull-up；And,
Transistor seconds, grid are connected with first clock signal output terminal, and the first pole maintains node to be connected with the pull-up,
Second pole is connected with the pull-up node；
The memory module includes：Storage capacitance, first end are connected with the pull-up node, the second end and carry signal output end
Connection.
4. shift register cell as claimed in claim 3, it is characterised in that the pull-up node current potential maintenance module bag
Include：
Third transistor, grid are connected with the pull-up node, and the first pole maintains node to be connected with the pull-up, the second pole and institute
State the connection of second clock signal output part.
5. shift register cell as claimed in claim 4, it is characterised in that the carry signal output module includes：
4th transistor, grid are connected with the pull-up node, and the first pole is connected with the second clock signal output part, and second
Pole is connected with the carry signal output end；And,
5th transistor, grid are connected with first clock signal output terminal, and the first pole is connected with the carry signal output end
Connect, the second pole is connected with the first low level output end；
The breadth length ratio of the 4th transistor is more than the breadth length ratio of the 5th transistor.
6. shift register cell as claimed in claim 5, it is characterised in that the carry signal output module includes：
6th transistor, grid are connected with the pull-up node, and the first pole is connected with the high level output end, the second pole and institute
State the connection of gate drive signal output end；And,
7th transistor, grid are connected with first clock signal output terminal, and the first pole is exported with the gate drive signal
End connection, the second pole is connected with the second low level output end；
The breadth length ratio of the 6th transistor is more than the breadth length ratio for making a reservation for the 7th transistor.
7. shift register cell as claimed in claim 6, it is characterised in that the first transistor, second crystal
Pipe, the third transistor, the 4th transistor, the 5th transistor, the 6th transistor and the 7th crystal
Guan Douwei n-type transistor.
8. a kind of driving method of shift register cell, the shifting being applied to as described in any claim in claim 1 to 7
Bit register unit, it is characterised in that include：In each display cycle,
In initial time section, the first clock signal and initial signal are all high level, and second clock signal is low level, initial mould
Block control initial signal output end, pull-up node and pull-up maintain node to be connected with each other, to control the current potential of the pull-up node
For high level, carry signal output module control carry signal output end the first low level of output, gate drive signal export mould
Block control gate drive signal output end exports the second low level；
In output time section, the first clock signal and initial signal are all low level, and second clock signal is high level, and carry is believed
Number output module control carry signal output end output high level, memory module bootstrapping draw high the current potential of the pull-up node, on
It is high level to draw the node potential maintenance module control pull-up to maintain the current potential of node, so as to avoid the electricity of the pull-up node
Position is reduced due to electric leakage；
In resetting time section, the first clock signal is high level, and initial signal and second clock signal are all low level, initial mould
Block control initial signal output end, pull-up node and pull-up maintain node to be connected with each other, so that the current potential of the pull-up node
For low level, carry signal output module controls carry signal output end to export the first low electricity under the control of the first clock signal
Flat, gate drive signal output module control gate drive signal output end exports the second low level.
9. a kind of GOA circuit, it is characterised in that including multiple cascades as described in any claim in claim 1 to 7
Shift register cell,
In addition to first order shift register cell, per one-level shift register cell initial signal output end all with adjacent
The carry signal output end connection of upper level shift register cell.
10. a kind of display device, it is characterised in that including GOA circuit as claimed in claim 9.
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