CN104461428B - Multichannel DVI image co-registration Corrective control main frames - Google Patents
Multichannel DVI image co-registration Corrective control main frames Download PDFInfo
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- CN104461428B CN104461428B CN201410733929.5A CN201410733929A CN104461428B CN 104461428 B CN104461428 B CN 104461428B CN 201410733929 A CN201410733929 A CN 201410733929A CN 104461428 B CN104461428 B CN 104461428B
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1415—Digital output to display device ; Cooperation and interconnection of the display device with other functional units with means for detecting differences between the image stored in the host and the images displayed on the displays
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Abstract
A kind of multichannel DVI image co-registrations Corrective control main frame of disclosure of the invention.It is administrative center by ARM CPU, FPGA is graphics processing unit, and multichannel high-resolution DVI IMAQs are strict parallel, synchronous multiway images fusion output.Main frame is provided with 1 ARM cpu motherboards, 4 channel plates.FPGA PLDs, dual link DVI input modules, dual link DVI output modules, QDR2 data access modules, the DDR2 data access modules of Digital image processing circuit are included inside channel plate.Each component distribution is on ARM core boards, mainboard and 4 channel plates run parallel.ARM core boards, channel plate are connected by mother daughter board connector with mainboard.Cascade port extended channel number can be passed through between main frame.The present invention effectively overcome traditional PC computing clusters it is expensive, output content synchronous real-time can not be completely the same shortcoming.Embedded FPGA graphics processing units effectively reduce space hold, and dual link DVI output image high resolutions can adapt to different projection screens with different transformation parameter tables.
Description
First, technical field
The invention belongs to electrical application technology field, it is related to multichannel image integration technology, specifically multichannel DVI images melt
Close Corrective control main frame.
2nd, background technology
At present, many display channel image co-registrations are that a width is big by the demand shown for large-scale Projection Display, LED screen
The application scenario of type scene image output is more and more., should mainly for high-resolution, big visual field, abnormal curved surface projection environment
For training centre, command and control center, large-scale meeting display screen, the data display environment of financial center, manufacturing industry control
Visualization, the visible environment of city management.
Large scale display system organization plan widely used at present is the power PC networking method of synchronization, this simple for structure
It is convenient.The display system is mainly made up of three parts：Display portion, operation control part, management configuration part.Display portion is
High-resolution projector or large LED display screen；Operation control part, management configuration part are high-performance GPU video cards and main frame
PC units.Such system is high to hardware performance requirements such as computer and video cards, and GPU video cards cost is high.In addition, this networking work
Mode, due to net lag reason, the synchronous real-time of multi-tiled display output content can not be completely the same.
3rd, the content of the invention
The purpose of the present invention be in view of the shortcomings of the prior art there is provided that a kind of image syncretizing effect is good, technology is realized is convenient,
The low-cost multichannel DVI image co-registrations Corrective control main frame of device therefor.
What the purpose of the present invention was achieved in that：A kind of multichannel DVI image co-registrations Corrective control main frame, its feature exists
In：
Control main frame is administrative center by ARM CPU, and high-performance FPGA is graphics processing unit, multichannel high-resolution DVI
IMAQ, realizes geometry, the colour correction of image pixel-class, and the seamless company of multiway images is realized by strict parallel synchronous mode
Connect, fusion output.For actual engineering project demand, identify project required number of active lanes n, configures identical with number of active lanes
N passage FPGA plate and its FPGA plate upper-parts, n DVI passage of parallel processing collection image；FPGA Digital Image Processing lists
Member is FPGA PLD internal circuits, completes high resolution digital image data processing work task；ARM CPU are total
Line Interface Module is used for realizing enters row data communication with ARM, and user on ARM by being programmed to the control to FPGA and biography
Transmission of data；In processing procedure, the transformation parameter table for being applicable different special-shaped screens is configured to each projected channel image processor,
To adapt to the requirement of different special-shaped projection screens.
Control main frame by include ARM cpu bus interfaces module, FPGA PLDs, DVI input modules,
DVI output modules, QDR2 data access modules, DDR2 data access modules are constituted, and are included inside FPGA PLDs
There is digital image processing unit；ARM CPU modules are arranged on ARM core boards, FPGA PLDs, DVI input moulds
Block, DVI output modules, QDR2 data access modules, DDR2 data access modules are arranged on passage FPGA plates, DVI input moulds
Block is arranged on passage FPGA plate DVI delivery outlets, and DVI output modules are arranged on passage FPGA plate DVI input ports.ARM cores
Plate is connected by plate connector with mainboard, and FPGA plates are connected by mother daughter board connector and its copper stud support with mainboard.Mainboard
Upper to configure network interface, cascade port, serial ports and the SD card being connected with ARM and FPGA PLDs, each interchannel leads to
Cross cascade port and realize that cascade is synchronous.
Described n DVI passages collection image of parallel processing, each main frame has can be by cascade between 4 passages, main frame
Mouthful, expand to port number n.
The DVI input modules are iTMDS A/D, complete the interface logic with DVI decoding chips, after sampling or decoding
To digital image data carry out tissue after will store into memory；DVI output modules be iTMDS D/A, including DVI export
Primary module and DVI output slave module two parts, realize that dual link is exported, the data image signal in caching is output to by completion
In DVI coding chips, so that image is exported to display or projector.
The conversion ginseng for being applicable different special-shaped screens to the configuration of each projected channel image processor in processing procedure
Number tables, its transformation parameter table is that PC is stored in locally by network interface by ARM, and in the course of the work transmission configuration to respectively
Individual passage, is stored into the DDR2 data access modules of each passage.
The QDR2 data access modules complete the accessing operation to the output image after input picture and processing, use
The mode of storage input image data and output image reading and writing data, sets 2 groups of QDR2 controllers to store input picture number respectively
According to read-write and 2 groups of QDR2 storage output image reading and writing datas, 4 groups of QDR2 controllers are grouped, mutually left alone two-by-two, separate
Concurrent working, maximum clock frequency reaches 333MHz.
The DDR2 data access modules are used for completing the SECO of DDR2 memories, are responsible for storage and are transmitted from ARM
The conversion number table come over, and in image transmitting process, pixel parameter is provided to FPGA internal images processing unit, at a high speed
Processing in real time, its maximum clock frequency reaches 333MHz.
Network interface, cascade port, the serial ports being connected with ARM and FPGA PLDs are configured on the mainboard to be included
Ethernet network interface, DB9 serial port, synchronizing signal mouthful, toggle switch inputs cascade port, output cascade mouthful, and outside 220V AC
Power inlet and Switching Power Supply, SD card are arranged on SD card socket.
By inputting cascade port between main frame, output cascade mouthful cascade, extended channel number, parallel processing needs number
DVI passages gather image.
The positive effect of the present invention is：
1st, main frame can effectively overcome the expensive shortcoming of PC computing clusters in traditional large screen display system, together
When overcome PC networking bring caused by net lag reason multi-tiled display output content synchronous real-time can not be complete
Complete consistent the problem of, image syncretizing effect is good.
2nd, the FPGA digital image processing units that the machine is used are used as insertion for FPGA PLD internal circuits
Formula equipment, it can effectively reduce the occupancy in space, convenient extension；As long as in addition, being applicable to image processor configuration different different
The transformation parameter table of shaped screen, picture system just adapts to different special-shaped projection screens, strong adaptability, image co-registration correction matter
Amount is high.The machine supports multiple transformation parameter tables that prestore, and one of them configuration may be selected and uses.
3rd, each passage FPGA of main frame cascades the control for realizing refresh synchronization signal using main frame, this to be realized with hardware together
The control mode of signal is walked, make the refresh synchronization of picture material is improved well.
4th, can be according to actual engineering project demand, identify project required projected channel number, DVI needed for parallel processing
Passage gathers image.
5th, fusion calibration result is substantially improved in high-definition picture dual link DVI inputs and DVI outputs.Resolution ratio highest
Up to 2560 × 1600,1920 × 1200, the resolution ratio such as 1400 × 105060Hz are also supported.
4th, illustrate
Fig. 1 is this multichannel DVI image co-registration Corrective control main machine structure block diagrams.
Fig. 2 is each part scheme of installation of this multichannel DVI image co-registration Corrective control main frames.Cabinet two is only shown in figure
2 pieces of FPGA channel plates of side, also two pieces channel plates, use ... and represent in addition.
Fig. 3 is this multichannel DVI image co-registration Corrective control main frame outward appearance front elevations.
Fig. 4 is this multichannel DVI image co-registration Corrective control main frame outward appearance back views.
In figure, 1, mainframe box；2nd, mainboard；3rd, ARM core boards；4th, FPGA channel plates；5th, indicator light circuit plate；6th, 26 core
Flex cable；7th, indicator lamp I/O expansion mouthful；8th, certain FPGA channel plate DVI delivery outlet；9th, certain FPGA channel plate DVI input port；10、
Ethernet network interface；11st, DB9 serial port；12nd, synchronizing signal mouthful；13rd, SD card socket；14th, toggle switch；15th, cascade port is inputted；16、
Output cascade mouthful；17th, FPGA channel plates copper stud support；18th, the mother daughter board connector of ARM core boards and mainboard；19th, outside 220V
AC power supplies input port；20th, Switching Power Supply；21st, FPGA channel plates and back plane connector.
5th, embodiment
Accompanying drawing gives a specific embodiment.
The all parts of this Corrective control main frame are arranged in cabinet, and cabinet is standard 3U cabinets, possesses air-cooled, conduction etc.
Radiating mode.Length × width × height is about 4250 × 4350 × 1320 (mm), and casing possesses 4 mounting holes, ground stud.Casing
Material uses metal material shell, aluminium section.
There are mainboard, ARM core boards, FPGA channel plates and lamp plate in cabinet.All parts are laid out on each plate.ARM CPU
Module is arranged on ARM core boards, FPGA PLDs, DVI input modules, DVI output modules, QDR2 data accesses
Module, DDR2 data access modules are arranged on FPGA plates.DVI input modules are arranged on FPGA channel plate DVI delivery outlets 8,
DVI output modules are arranged on ARM core boards on FPGA channel plate DVI input ports 9 and pass through ARM core boards and the plate of mainboard with mainboard
Part connector 18 is connected, and each FPGA channel plate is connected by connector 21 and its 4 copper stud supports 17 with mainboard.
This Corrective control main frame is provided with 4 FPGA channel plates, parallel processing 4 using 4 DVI passages collection images
Individual DVI passages gather image.
The present invention can determine the DVI passages collection image channel number of different screen as needed, real using cascade system
Between existing main frame and each interchannel refresh synchronization.By inputting cascade port 15 between main frame, output cascade mouthful 16 is cascaded, and extension is logical
Road number, parallel processing needs the DVI passages of number to gather image.
This Corrective control main frame is administrative center by ARM CPU, and user on ARM by being programmed to the control to FPGA
ARM CP on system and transmission data, ARM core circuit plates are responsible for the parameter configuration management and condition monitoring of each image channel,
The firmware configuration management of the correction parameter and FPGA of each passage is stored simultaneously.ARM CPU by from PC receive for each
The transformation parameter table of passage configuration is simultaneously stored into local SD card, and each port is configured.Matched somebody with somebody during configuration by ARM transmission
Each passage is put, is stored in the DDR2 data access modules of each passage, to adapt to wanting for different special-shaped projection screens
Ask.Meanwhile, every order at ARM CPU response PC ends.
This Corrective control main frame is using high-performance FPGA as graphics processing unit, and FPGA digital image processing units are to be embedded in
The internal circuit of FPGA PLDs.The present embodiment employs 4 XILINX chips, completes the height of 4 projected channels
Resolution digital image data processing work task, 4 passages are connected by mother daughter board connector on mainboard 21 respectively, and use copper spiral shell
Column holder 17 is supported.Input cascade port 15 on mainboard, output cascade mouthfuls 16 using cascade system with being realized between main frame and each led to
Refresh synchronization between road.Cascade input interface is designated C_IN, is 16 core technical grade plug-in units.Cascaded-output interface identifier is C_
OUT, is 16 core technical grade plug-in units.
In the present embodiment, DVI input modules be iTMDS A/D, ultimate resolution be 2560 × 1600,60Hz, complete with
The digital image data obtained after the interface logic of DVI decoding chips, sampling or decoding is carried out storage to memory after tissue
In.DVI outputs set dual link to export, and have DVI to export primary module and DVI output slave module two parts, using iTMDS D/
A, ultimate resolution is 2560 × 1600,60Hz, and the data image signal in caching is output in DVI coding chips by completion,
So that image is exported to display or projector.DVI input modules are arranged on FPGA channel plate DVI input ports 9,
DVI output modules are arranged on FPGA channel plate DVI delivery outlets 8, positioned at the channel plate upper edge side.DVI input interfaces are identified
For IN1, IN2, IN3, IN4, totally 4, meet iTMDS standards.DVI output interfaces are designated OUT1, OUT 2, OUT 3, OUT 4
Totally 4, meet iTMDS standards.
QDR2 data access modules complete the accessing operation to the output image after input picture and processing.Deposited in data
Chu Shang, by the way of using storage input image data respectively and output image reading and writing data.2 groups of QDR2 controllers are set to deposit
Input image data read-write and 2 groups of QDR2 storage output image reading and writing datas are stored up, 4 groups of QDR2 controllers are grouped, do not beaten mutually two-by-two
Disturb, separate concurrent working, maximum clock frequency reaches 333MHz.
DDR2 data access modules are used for completing the SECO of DDR2 memories, are responsible for storage and are transmitted from ARM
Conversion number table, and when needing high speed to Digital Image Processing module provide pixel parameter, its maximum clock
Frequency reaches 333MHz.One group of two pieces of 64M × 16bit, 333MHz DDR2 modules are set.
Configure and be connected with ARM and FPGA PLDs including Ethernet network interface 10 on mainboard, be main frame and PC
The interface of machine interaction data, is designated NET；DB9 serial port 11, predominantly debugging are used, and are designated DEBUG；Synchronizing signal mouthful 12, be
The frame synchronization output signal of the machine picture material, is designated SNYC；SD card socket, wherein SD card can store parameter list and test chart
Piece, is designated SD；Toggle switch 14, can be set main frame machine number, is designated SET；Cascade port 15 is inputted, C_IN is designated；Output
Cascade port 16, is designated C_OUT；These interfaces are respectively positioned on mainboard upper edge side.In addition, main frame is additionally provided with outside 220V AC
Power inlet 19 and Switching Power Supply 20.Host housing front has an indicator lamp 7, including 1 power supply indicator, 4 passages,
2 working condition lamps of each passage, represent whether each passage input/output signal possesses.
Each part configuration of this Corrective control main frame is referring to table 1.
Table 1
The typical operation of this main frame is as follows：Host work is in correction mode, and FPGA module is first by DVI input modules
The data of acquisition are cached in QDR2_C0, C1 in the way of ping-pong buffer and point parity rows, then from the DDR2 of storage parameter list
The acquisition single pixel point parameter of middle order, and using coordinate data therein as address, from corresponding storage image data
Image buffer storage then takes out required pixel number evidence into QDR2_C0, C1, then carries out the multiply-add of pixel and interpolation coefficient
Computing, and the data obtained after computing are output in the way of Pingpang Memory in QDR2_C2, C3 caching, finally by meeting mark
Accurate display resolution sequential, by the view data in QDR2_C2, C3 by DVI output modules, is output to display or throwing
Shadow instrument.The view data continual real-time processing that handles, realize video image of the main frame to input.
Claims (4)
1. a kind of multichannel DVI image co-registrations Corrective control main frame, it is characterised in that：
Corrective control main frame is administrative center by ARM CPU, and high-performance FPGA is graphics processing unit, multichannel high-resolution DVI
IMAQ, realizes geometry, the colour correction of image pixel-class, and the seamless company of multiway images is realized by strict parallel synchronous mode
Connect, fusion output；For actual engineering project demand, identify project required number of active lanes n, configures identical with number of active lanes
N FPGA plate and its FPGA plate upper-parts, the image of n DVI passage of parallel processing collection；FPGA digital image processing units
For FPGA PLD internal circuits, complete high resolution digital image data processing work task and n passage is same
Walk control task；ARM cpu bus interfaces module is used for realizing enters row data communication with ARM, user by programmed on ARM come
Realize the control to FPGA and transmission data；In processing procedure, difference is applicable to the configuration of each projected channel image processor
The transformation parameter table of special-shaped screen, to adapt to the requirement of different special-shaped projection screens；
Corrective control main frame by include ARM cpu bus interfaces module, FPGA PLDs, DVI input modules,
DVI output modules, QDR2 data access modules, DDR2 data access modules are constituted, and are included inside FPGA PLDs
There is digital image processing unit；ARM CPU modules are arranged on ARM core boards, FPGA PLDs, DVI input moulds
Block, DVI output modules, QDR2 data access modules, DDR2 data access modules are arranged on passage FPGA plates, DVI input moulds
Block is arranged on passage FPGA plate DVI input ports (9), and DVI output modules are arranged on passage FPGA plate DVI delivery outlets (8)；
ARM core boards are connected by mother daughter board connector (18) with mainboard, and passage FPGA plates pass through mother daughter board connector (21) and its copper stud
Support (17) is connected with mainboard；On mainboard configure be connected with ARM and FPGA PLDs network interface, cascade port,
Serial ports and SD card, main frame and each interchannel realize that cascade is synchronous by cascade port；
The DVI input modules are iTMDS A/D, complete the interface logic with DVI decoding chips, are obtained after sampling or decoding
Digital image data will be stored after tissue into memory；DVI output modules be iTMDS D/A, including DVI output main mould
Block and DVI output slave module two parts, realize that dual link is exported, and complete the data image signal in caching being output to DVI volumes
In code chip, so that image is exported to display or projector；
It is described that the transformation parameter table for being applicable different special-shaped screens is configured to each channel image processor in processing procedure, its
Transformation parameter table is that PC is saved in each passage by network interface by ARM transmission configurations, is then store in each passage
In DDR2 data access modules；
The QDR2 data access modules complete the accessing operation to the output image after input picture and processing, set 2 groups
The storage input image data read-write of QDR2 controllers and 2 groups of QDR2 storage output image reading and writing datas, store input picture respectively
Data and output image reading and writing data, 4 groups of QDR2 controllers are grouped two-by-two, are mutually left alone, separate concurrent working, highest
Clock frequency reaches 333MHz；
The DDR2 data access modules are used for completing the SECO of DDR2 memories, are responsible for storage and are transmitted from ARM
Conversion number table, and in image transmitting process, give FPGA internal images processing unit to provide pixel parameter, at a high speed in real time
Processing, its maximum clock frequency reaches 333MHz.
2. multichannel DVI image co-registrations Corrective control main frame as claimed in claim 1, it is characterised in that：The parallel processing n
Individual DVI passages gather image, its n=4.
3. multichannel DVI image co-registrations Corrective control main frame as claimed in claim 1, it is characterised in that：Match somebody with somebody on the mainboard
Putting the network interface being connected with ARM and FPGA PLDs, cascade port, serial ports includes Ethernet network interface (10), DB9 strings
Mouth (11), synchronizing signal mouthful (12), toggle switch (14), input cascade port (15), output cascade mouthful (16), and outside 220V
AC power supplies input port (19) and Switching Power Supply (20), SD card are arranged on SD card socket (13).
4. multichannel DVI image co-registrations Corrective control main frame as claimed in claim 1, it is characterised in that：Pass through between main frame
Cascade port (15) is inputted, output cascade mouthful (16) cascade, extended channel number, parallel processing needs the DVI passage collection figures of number
Picture.
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| CN106328044B (en) * | 2015-07-06 | 2018-10-23 | 西安电子科技大学 | LED display control card and LED display control system |
| CN109840844B (en) * | 2017-11-27 | 2023-12-22 | 上海仪电（集团）有限公司中央研究院 | Financial big data acquisition processing device and system based on FPGA |
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