CN204596391U - A kind of distributor - Google Patents
A kind of distributor Download PDFInfo
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- CN204596391U CN204596391U CN201520258625.8U CN201520258625U CN204596391U CN 204596391 U CN204596391 U CN 204596391U CN 201520258625 U CN201520258625 U CN 201520258625U CN 204596391 U CN204596391 U CN 204596391U
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Abstract
A kind of distributor, the data sent from FPGA chip circuit output terminal and the sending card of the HUB scanning card of the full-color playing controller of LED display are divided into multiple data block, the IP kernel road output terminal of the SGMII interface of fpga chip changes into differential signal, consists of the subnet mouth of 2-4 SMGII interface SMGII interface Parallel opertation 4-8 SMGII interface; Then divide to send out from subnet mouth and connect LED display bus port.
Description
One: technical field
The utility model relates to the full-color synchronous broadcasting control system of asynchronous LED display screen, is especially in the distributor of the full-color synchronous broadcasting control system between sending card and receiving card, very important in whole LED display control system.
Two, background technology
Distributor is between sending card and receiving card, plays a part very important in whole LED display control system.The composition of LED display control system generally has following several part: video transmission device, video reception distributor, LED panel.The distributor that the applicant develops is connected between video transmission device and video reception distributor, and system construction drawing as shown in Figure 1.The task of distributor is that data sending card sent are divided into multiple data block, then divides from network interface and sends out.The data of the data that sending card is sent can be 4 transmission speeds be 6.25G bps, come in by optical fibre channel, so distributor receives a little data, is distributed into the data that 24 transmission speeds are 1G bps, sends from network interface.Distribution algorithms makes the connection between sending card and receiving card more flexible, can have multiple ways of distribution, meet different customer demands.
The applicant has proposed 203490926U patent: a kind of module stores the LED display module of correction data, comprise LED display, nonvolatile memory and control device, LED display is connected with nonvolatile memory, control device is connected with nonvolatile memory with LED display respectively, described nonvolatile memory is for storing LED display correction data, the LED display correction data stored in control device reading non-volatile storage, be transferred to host computer, after host computer process, display data are sent to control device, control device controls LED display display image.Fig. 1 LED display control system structural drawing.
Distributor is mainly used to carry out Data dissemination, by the Data dissemination on high-speed passage on the network interface of low velocity.The data of distributor can be come from sending card, come in be distributed to multiple network interface by unipath optical fiber, also can be come in by multi-channel optical fibre path, be distributed on more network interface, the algorithm of distribution can customize according to the demand of client, realizes the copying image of different modes.
Separately there is 202855261U, the full-color synchronous broadcasting control system of a kind of asynchronous LED display screen, comprise main control unit, LED display driver unit, program source storage unit, communication unit and display storage unit; FPGA is connected with display storage unit; The output terminal of FPGA is the output terminal of the full-color synchronous broadcasting control system of this asynchronous LED display screen.
And 202102690U, asynchronous LED screen display control card, comprise master control borad, HUB scans card, LED display bus module and LED display bus port and driving circuit, master control borad and HUB scanning card are respectively made up of one piece of FPGA chip circuit, the control chip of master control borad is that zynq7000 family device is as control processor, the fpga chip input end of master control borad connects video card output port, the FPGA chip circuit output terminal of HUB scanning card connects LED display bus port, host computer bus connects the interface circuit of the fpga chip of master control borad and HUB scanning card, LED display bus port and driving circuit connect LED display.
Asynchronous LED screen display system is primarily of Xin Kong Xi Tong ﹑ driving circuit and LED screen composition.As shown in Figure 1, what the screen design of current most of display screen adopted is modular structure to the system architecture of prior art.Its elementary cell is display unit module.
Three: utility model content
The purpose of this utility model is, proposes the distributor of the full-color broadcasting of a kind of LED display.
This technical scheme is: a kind of distributor, the data sent from FPGA chip circuit output terminal and the sending card of the HUB scanning card of the full-color playing controller of LED display are divided into multiple data block, the IP kernel road output terminal of the SGMII interface of fpga chip changes into differential signal, consists of the subnet mouth of 2-4 SMGII interface SMGII interface Parallel opertation 4-8 SMGII interface; Then divide to send out from subnet mouth and connect LED display bus port.
The task of distributor is that data sending card sent are divided into multiple data block, then divides from network interface and sends out.The data of the data that sending card is sent can be 4 transmission speeds be 6.25G bps, come in by optical fibre channel, so distributor receives a little data, is distributed into the data that 24 transmission speeds are 1G bps, sends from network interface.Distribution algorithms makes the connection between sending card and receiving card more flexible, can have multiple ways of distribution, meet different customer demands.
Distributor principle of work, distributor is mainly used to carry out Data dissemination, by the Data dissemination on high-speed passage on the network interface of low velocity.The data of distributor are come from sending card, come in be distributed to multiple network interface by unipath optical fiber, also can be come in by multi-channel optical fibre path, be distributed on more network interface, the algorithm of distribution can customize according to the demand of client, realizes the copying image of different modes.
The beneficial effects of the utility model: adopt senior FPGA to distribute design proposal, during design distributor, should select the design proposal based on programmable logic device (PLD).FPGA (field programmable gate array) programmable logic device (PLD) producer provides abundant IP kernel, and these IP kernel versatilities are good, portable good, uses IP kernel to be easy to increase New function and shorten Time To Market in the design.The IP kernel using Xilinx producer to provide in distributor is all through checking, and multiple functional, performance is measurable, device resource and utilization factor known, and document is complete, and Xilinx official supports.By in exampleization or black box mode exampleization to oneself design, can greatly shorten the construction cycle of product in the design.
The utility model distributor (HRT4A24G type) can receive the transmission speed of four road optical fiber 6.25G bps, and it is distributed away by 24 gigabit network interfaces.Distributor adopts high precision six layers of pcb board design, effectively reduces electromagnetic interference (EMI), can realize the both-way communication of grid line (surpassing five classes) or optical fiber, support Aurora agreement and gigabit ethernet interface agreement.Meanwhile, all devices adopted in distributor are lead-free product (see each product certification book), produce, because this ensure that this product meets the requirement of European Union RoHS leadless environment-friendly in process of production in strict accordance with leadless process.
Four, accompanying drawing explanation
Fig. 1 is distributor theory diagram.
Fig. 2,3 is two schemes distributor block diagram respectively.
Five, embodiment
Following Fig. 1 is distributor theory diagram.
FPGA distributes design proposal: during design distributor, should select the design proposal based on programmable logic device (PLD).FPGA (field programmable gate array) programmable logic device (PLD) producer provides abundant IP kernel, and these IP kernel versatilities are good, portable good, uses IP kernel to be easy to increase New function and shorten Time To Market in the design.The IP kernel using Xilinx producer to provide in distributor is all through checking, and multiple functional, performance is measurable, device resource and utilization factor known, and document is complete, and Xilinx official supports.By in exampleization or black box mode exampleization to oneself design, can greatly shorten the construction cycle of product in the design.
Below that the applicant develops distributor block diagram, total two schemes (Fig. 2,3).
The structure and fuction of fpga logic module: module title: data conversion module, Aurora IP kernel, DDR2IP core, SGMII IP kernel and FIFO memory.Function defines: the design is mainly used in Data dissemination.Whole logical design is divided into a few part by the function difference according to modules.Respectively:
● data conversion module: its function is stitched together at the data that DP mouth is come in.
● Aurora IP kernel: the differential conversion that optical fibre channel is come in mainly is become digital signal by its function.
DDR2IP core: its function mainly realizes the read-write capability of data, the data buffer storage come of being made a slip of the tongue by DP enters in DDR2 storer; SGMII IP kernel: the data of 8 are mainly changed into differential signal by its function, divides and sends out from network interface.FIFO memory: be mainly used to carry out data buffering.
FPGA (field programmable gate array) integrated level is high, volume is little, has the function being realized specialized application by user program.It allows circuit designers to utilize computer development platform, through design input, emulation, test and verification, until reach expected result.Adopt FPGA can shorten the construction cycle of system, reduce the power consumption of system, improve the reliability of system.
The utility model distributor (HRT4A24G type) can receive the transmission speed of four road optical fiber 6.25G bps, and it is distributed away by 24 gigabit network interfaces.Distributor adopts high precision six layers of pcb board design, effective reduction electromagnetic interference (EMI), the both-way communication of grid line (surpassing five classes) or optical fiber can be realized, support Aurora agreement and gigabit ethernet interface agreement, support that resolution 3840 × 2160 × 30 × 60HZ transmits.Meanwhile, all devices adopted in distributor are lead-free product (see each product certification book), produce, because this ensure that this product meets the requirement of European Union RoHS leadless environment-friendly in process of production in strict accordance with leadless process.
1, senior FPGA technology application
Adopt single chip VLSI design as distribution chip, apply Aurora IP kernel and the SGMII IP kernel of Xilinx FPAG: the maximum transfer speed of reception is 25G bps, the maximum network interface number that can distribute is 24.
2, different ways of distribution is supported
The distributor of the utility model design has two kinds of distribution approach.The first scheme of Fig. 2 is that vision signal is sent by sending card, by SFP Optical Fiber Transmission, have four road optical fibre channels, the transmission speed of each optical fibre channel is 6.25Gbps, run Aurora agreement, complete transmission and the process of data in FPGA inside, the maximum fiber transmission speed of support is 25G bps.Figure first scheme is by DP interface from video card image data, by the deposit data after collection in DDR2, is distributed in 24 network interfaces by FPGA.
3, other functional characteristics
Client proposes different image demands, and distributor can meet.Support that multi-channel optical fibre path is distributed to multiple network interface, four road optical fibre channels and 24 network interfaces can combination in any, simultaneous displays.Support the input of various video signal source; The transmission speed of maximum support 25G bps; Support that resolution 3840 × 2160 × 30 × 60HZ transmits.Support the transmission of single mode, multimode optical fiber.
The distributor of core that what my company developed with FPGA is, the reliability of hardware is high, the high speed characteristics of senior FPGA technology device, and the distribution speed of distributor is ensured.The use of Xilinx IP kernel technology, also makes the actual effect of system greatly improve, and has very high market using value.
2, SGMII interface is used
SGMII interface is adopted to replace traditional RGMII/GMII interface.RGMII/GMII is parallel, and the pin of needs is many, and needs with road clock, and PCB layout bothers relatively, and SGMII is serial, and not needing provides other clock, therefore adopts SGMII interface to save wiring, simplifies PCB design, reduce costs.
3, other functional characteristics
Client proposes different image demands, and distributor can meet; Support that multi-channel optical fibre path is distributed to multiple network interface, four road optical fibre channels and 24 network interfaces can combination in any, simultaneous displays; Support the input of various video signal source; The transmission speed of maximum support 25G bps; Support the subcard of different size, subcard can connect 10G electricity mouth and 1G electricity mouth; Be widely used, distributor can be used on net distribution, is equivalent to the switch carrying agreement, carries out network exchange; Support the transmission of single mode, multimode optical fiber.
Of the present utility model take FPGA as the distributor of core, and the reliability of hardware is high, the high speed characteristics of senior FPGA technology device, and the distribution speed of distributor is ensured.The use of Xilinx IP kernel technology, also makes the actual effect of system greatly improve, and has very high market using value.
Claims (1)
1. a distributor, it is characterized in that the data sent from FPGA chip circuit output terminal and the sending card of the HUB scanning card of the full-color playing controller of LED display are divided into multiple data block, the IP kernel road output terminal of the SGMII interface of fpga chip changes into differential signal, consists of the subnet mouth of 2-4 SMGII interface SMGII interface Parallel opertation 4-8 SMGII interface; Then divide to send out from subnet mouth and connect LED display bus port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520258625.8U CN204596391U (en) | 2015-04-24 | 2015-04-24 | A kind of distributor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520258625.8U CN204596391U (en) | 2015-04-24 | 2015-04-24 | A kind of distributor |
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| CN204596391U true CN204596391U (en) | 2015-08-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110990201A (en) * | 2019-11-29 | 2020-04-10 | 中国电子科技集团公司第五十四研究所 | Self-healing management controller, SoC and self-healing method |
| CN112992044A (en) * | 2019-11-29 | 2021-06-18 | 西安诺瓦星云科技股份有限公司 | Display screen controller, display screen control system and LED display system |
-
2015
- 2015-04-24 CN CN201520258625.8U patent/CN204596391U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110990201A (en) * | 2019-11-29 | 2020-04-10 | 中国电子科技集团公司第五十四研究所 | Self-healing management controller, SoC and self-healing method |
| CN112992044A (en) * | 2019-11-29 | 2021-06-18 | 西安诺瓦星云科技股份有限公司 | Display screen controller, display screen control system and LED display system |
| CN110990201B (en) * | 2019-11-29 | 2023-04-28 | 中国电子科技集团公司第五十四研究所 | Self-healing management controller, soC and self-healing method |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150826 Termination date: 20180424 |
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| CF01 | Termination of patent right due to non-payment of annual fee |