CN104425621A - 薄膜晶体管及使用该薄膜晶体管之显示阵列基板 - Google Patents
薄膜晶体管及使用该薄膜晶体管之显示阵列基板 Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
- H01L21/4757—After-treatment
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
本发明提供一种薄膜晶体管。该薄膜晶体管包括：一栅极；一覆盖该栅极之栅极绝缘层；在该栅极绝缘层上对应该栅极处的沟道层；一覆盖该沟道层之蚀刻阻挡层，该蚀刻阻挡至少包括一有机阻挡层及与该有机阻挡层层迭设置的硬遮罩层，该有机阻挡层为经固化处理之透明有机材料层，该硬遮罩层形成在该有机阻挡层背离该沟道层之表面上，用于增强该有机阻挡层之硬度；贯穿该蚀刻阻挡层之二接触孔；及经由该二接触孔与该沟道层相连之源极与漏极。本发明还提供一种使用该薄膜晶体管的显示阵列基板。
Description
技术领域
本发明涉及一种薄膜晶体管及使用该薄膜晶体管之显示阵列基板。
背景技术
利用金属氧化物半导体(Metal Oxide Semiconductor)形成沟道的薄膜晶体管(Thin Film Transistor，TFT)已被逐渐广泛应用于显示领域作为开关组件使用。在薄膜晶体管制程中由于金属氧化物半导体对后段制程，如用来形成薄膜晶体管之源、漏极之湿蚀刻(Wet-Etching)制程反应敏感，故会在金属氧化物半导体层上形成一蚀刻阻挡层借以保护该金属氧化物半导体层之特性。然而，由于蚀刻阻挡层必须满足一定的厚度需求，如大于1微米，在用黄光曝光形成接触孔时受厚度之影响使得源极与漏极之间的通道宽度通常维持在10微米左右，无法降低到一更小范围内，不仅导致薄膜晶体管本身的特性，如频率特性受到影响，而且也无法满足高分辨率(High Resolution HD)等面板的要求。
发明内容
有鉴于此，有必要提供一种具有较小通道长度的薄膜晶体管。
更进一步地，提供一种具有该薄膜晶体管之显示阵列基板。
一种薄膜晶体管，包括：
一栅极；
一覆盖该栅极之栅极绝缘层；
在该栅极绝缘层上对应该栅极处的沟道层；
一覆盖该沟道层之蚀刻阻挡层，该蚀刻阻挡层为一层迭结构，至少包括一有机阻挡层及与该有机阻挡层一硬遮罩层，该有机阻挡层与该硬遮罩层层迭设置，该有机阻挡层为经固化处理之透明有机材料层，该硬遮罩层形成在该有机阻挡层背离该沟道层之表面上，用于增强该有机阻挡层之硬度；
贯穿该蚀刻阻挡层之二接触孔；及
经由该二接触孔与该沟道层相连之源极与漏极。
一种薄膜晶体管阵列基板，包括多条相互平行的栅极线、多条相互平行且与该些栅极线绝缘相交的数据线，每一栅极线与一资料线交叉处设置一上述的薄膜晶体管。
相较于现有技术，本发明的薄膜晶体管及使用该薄膜晶体管的显示阵列基板将有机阻挡层作高温硬烤处理，于该蚀刻阻挡层上形成一硬遮罩层以增强面机阻挡层之硬度，且利用较短通道设计之光阻进行曝光显影出穿导孔，进一步利用干蚀刻技术对蚀刻阻挡层进行蚀刻以获得具有较短距离之接触孔以减小薄膜晶体管之源、漏极间之沟道宽度，达到提高TFT性能及满足面板的高分辨率之需求。
附图说明
图1是本发明第一实施方式的显示阵列基板一画素区域的局部平面结构示意图。
图2是图1所示的显示阵型基板沿II-II线的剖面结构示意图。
图3至图9描述了图2所示的薄膜晶体管各制作步骤之结构示意图。
图10是图2所示的薄膜晶体管制造流程示意图。
主要元件符号说明
| 显示阵列基板 | 20 |
| 薄膜晶体管 | 200 |
| 栅极线 | 21 |
| 数据线 | 22 |
| 栅极 | 210 |
| 源极 | 220 |
| 漏极 | 230 |
| 基板 | 201 |
| 沟道层 | 203 |
| 栅极绝缘层 | 205 |
| 蚀刻阻挡层 | 207 |
| 有机阻挡层 | 207a |
| 硬遮罩层 | 207b |
| 光阻 | 209 |
| 光罩 | 24 |
| 透光部份 | 240 |
| 不透光部份 | 241 |
| 穿导孔 | H21、H22 |
| 接触孔 | O21、O22 |
| 沟道宽度 | L2 |
| 步骤 | S401~S417 |
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
请参阅图1，图1是本发明一实施方式显示阵列基板的一画素区域之局部的平面结构示意图。该显示阵列基板20包括多条相互平行的栅极线21、多条相互平行且与该些栅极线绝缘相交的数据线22。每一栅极线11与一资料线12交叉处设置一薄膜晶体管(thin-film transistor, TFT)200，该薄膜晶体管200包括与栅极线21相连的栅极210用于外部栅极驱动器(未示出)输出的栅极信号，与数据线22相连的源极220用于接收外部数据驱动器(未示出)输出的数据信号及与该源极220间隔设置的漏极230。
当栅极线210输出的栅极信号电压高于薄膜晶体管200的阈值电压时，形成在薄膜晶体管200内部的沟道层203(如图2所示)的电特性从绝缘体变为导体，使得施加到源极220的数据信号通过沟道层203施加至漏极230上。
请参阅图2，图2为图1所示的显示阵型基板10沿II-II线的剖面结构示意图。
该薄膜晶体管200的栅极210设置在基板201上，沟道层203对应栅极210设置，栅极绝缘层210设置在栅极210与沟道层203之间。在本实施例中，该沟道层203由金属氧化物半导体结构构成，其材料包括：氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟(InO)、氧化镓(GaO)或其混合物。该薄膜晶体管200进一步包括覆盖整个沟道层203与栅极绝缘层210表面的蚀刻阻挡层207，该蚀刻阻挡层207为具有一定固化硬度之透明绝缘结构，用于保护该沟道层203避免后续制程对其造成损坏，并提供一平坦表面。在本实施例中，该蚀刻阻挡层207为一层迭结构，包括一有机阻挡层207a及与该有机阻挡层207a层迭设置之硬遮罩层207b。该有机阻挡层207a为经固化处理之透明有机材料层，该透明有机材料层可为具有光敏特性的有机材料也可为不具有光敏特性的有机材料，其中，该有机阻挡层207a之光敏特性弱于光阻(Photoresistor)材料的光敏特性。该硬遮罩层207b设置在该有机阻挡层207a背离基板201的表面上，用于增强该有机阻挡层207a之硬度。在本实施例中，该硬遮罩层207b之厚度小于该有机阻挡层207a的厚度，其材料可选自氮化硅(SiNx)、氧化硅(SiOx)、氟化硅(SiFx)、氮氧化硅(SiNxOy)等无机材料。二接触孔O21、O22沿厚度方向贯穿该蚀刻阻挡层207，从而曝露出部分沟道层203，该二接触孔O21、O22之间的间隔距离对应定义该薄膜晶体管200之沟道宽度L2。在本实施例中，该二接触孔O21、O22之间的间隔距离基本等于本发明所预期的窄沟道宽度，即小于10微米，优选为3-5微米。相应地，该薄膜晶体管200之沟道宽度L2小于10微米，优选为3-5微米。
进一步地，该薄膜晶体管200的源极220与漏极230分设于沟道层203相对的两侧并经经由二接触孔O21、O22与该沟道层203相接触。在本发明中，该蚀刻阻挡层207还同时充当了薄膜晶体管200之钝化层及平坦化层，用于间隔该源/漏极220、230与该沟道层230，并提供平坦表面。
请参阅图3-10图，其中图3-9为图2所示的薄膜晶体管200之各步骤制作过程示意图，图10为图2所示薄膜晶体管200的制造流程图。
步骤S401，请参阅图3，提供一基板201，在基板201上形成栅极210及覆盖该栅极210的栅极绝缘层205。在基板201上沉积第一金属层，图案化该第一金属层形成栅极210，然后沉积一栅极绝缘层205，使该栅极绝缘层205覆盖该栅极210。其中，该图案化的第一金属层以形成该栅极210的方法可为微影黄光蚀刻法。基板201可为玻璃基板或者石英基板，该第一金属层可为金属材料或金属合金，如钼(Mo)、铝(Al)、铬(Cr)、铜(Cu)、钕(Nd)等。该栅极绝缘层205为可以包括氮化硅(SiNx)或氧化硅(SiOx)。在本实施方式中，可利用溅射法、真空蒸镀法、脉冲激光沉积法、离子电镀法、有机金属气相生长法、等离子体CVD等沉积方法形成栅极绝缘层205。
步骤S403，请继续参阅图3，在栅极绝缘层205上对应栅极210处形成沟道层203，并于该沟道层203上涂布有机阻挡层207a以覆盖整个沟道层203。该沟道层203材料为金属氧化物半导体，如氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟(InO)、氧化镓(GaO)或其混合物。具体地，在本实施方式中，可利用溅射法、真空蒸镀法、脉冲激光沉积法、离子电镀法、有机金属气相生长法、等离子体CVD等沉积方法在该栅极绝缘层205上形成一金属氧化物半导体层，在图案化金属氧化物半导体层从而对应该栅极205处形成沟道层203。该有机阻挡层207a的材料为透明有机材料，在本实施例中，该有机阻挡层207a可为具有光敏特性的有机材料也可为不具有光敏特性的有机材料，其中，该有机阻挡层207a之光敏特性弱于光阻(Photoresistor)材料的光敏特性。该有机阻挡层207a用于保护该沟道层103避免后续制程对其造成的损害，其厚度一般大于1微米。
步骤S405，对形成有该有机阻挡层207a之基板201进行高温硬烤(Hard-baking)处理。高温硬烤使该有机阻挡层207a之表面更加平坦化并使之固化，并能有效增强该蚀刻阻挡层207与该沟道层203之间附着性。在本实施方式中，高温硬烤的温度根据有机阻挡层207a之材料特性决定，一般高温硬烤的温度于100℃~400℃范围内。经高温硬烤后的蚀刻阻挡层材料将其内部的残余的有机溶剂挥发，从而使得该有机阻挡层207a固化，并加强与沟道层203之间的附着性。
步骤S407，请参阅图4，于该有机阻挡层207a上形成硬遮罩层207b，该硬遮罩层207b与该有机阻挡层207a层迭设置共同构成一蚀刻阻挡层207。在本实施方式中，该硬遮罩层207b设置在该有机阻挡层207a背离基板201的表面上，用于增强该有机阻挡层207a之硬度。在本实施例中，该硬遮罩层207b之厚度小于该有机阻挡层207a的厚度，其材料可选自氮化硅(SiNx)、氧化硅(SiOx)、氟化硅(SiFx)、氮氧化硅(SiNxOy)等无机材料。在本实施方式中，可利用化学气相沉积(CVD)、物理气相沉积(PVD)、蒸镀、溅镀等方法沉积形成该硬遮罩层207b。该硬遮罩层207b材料为氮化硅(SiNx)、氧化硅(SiOx)、氟化硅(SiFx)等材料。
步骤S409，请参阅图5，于该蚀刻阻挡层207上涂布光阻层209。
步骤S411，请参阅图6，利用黄光制程图案化该光阻层209从而在该图案化的光阻层209上定义出穿导孔H21、H22。具体地，利用光罩(Mask)24为屏蔽对光阻层209进行黄光曝光以显影出贯穿该光阻层209的穿导孔H21、H22，该穿导孔H21、H22为贯穿该光阻层209厚度的通孔，且二者之间的距离基本等于本发明所预期的较窄沟道宽度，即小于10微米，优选为3-5微米。具体地，该光罩24包括二透光部分240与不透光部分241，二透光部分240对应的光阻层209部分经紫外光照射曝光，再经显影后形成该穿导孔H21、H22。该光罩24之不透光部分240之间的距离界定了该穿导孔H21、H22之间的距离。
步骤S413，请参阅图7，以该图案化光阻层209作屏蔽采用干蚀刻(Dry-etching)的方式该硬遮罩层207b与该有机阻挡层207，从而形成沿厚度方向贯穿该硬遮罩层207b及该有机阻挡层207的接触孔O21、O22。因此，该接触孔O21、O22之间的距离也基本等于本发明所预期的较窄沟道宽度，如：3-5微米。在本实施方式中，可利用电浆蚀刻(Plasma Etching)、反应离子蚀刻(Reactive Ion Etching，RIE)、等离子蚀刻等干蚀刻方法将蚀刻阻挡层207蚀刻至沟道层203。
步骤S415，请参阅图8，移除剩余的光阻层209。
步骤S417，请参阅图9，在该硬遮罩层207b上形成源极220与漏极230，该源极220与漏极230分别填充该接触孔O21、O22与该沟道层203相接触。具体地，于该蚀刻阻挡层207之表面沉积一第二金属层，并利用一道光罩蚀刻制程图案化该第二金属层，从而在该沟道层203相对两侧形成源极220与漏极230，并填充该二接触孔O21、O22。该第二金属层为金属材料或金属合金，如钼(Mo)、铝(Al)、铬(Cr)、铜(Cu)、钕(Nd)等。对第二金属层进行蚀刻的方法为湿蚀刻(Wet-Etching)方法。
当该薄膜晶体管200应用于液晶面板时，在后续制程中，在该薄膜晶体管200上可形成平坦化层、画素电极等习知结构，在此不再赘述。
本发明的薄膜晶体管及使用该薄膜晶体管的显示阵列基板将有机阻挡层作高温硬烤处理，于该蚀刻阻挡层上形成一硬遮罩层以增强面机阻挡层之硬度，且利用较短通道设计之光阻进行曝光显影出穿导孔，进一步利用干蚀刻技术对蚀刻阻挡层进行蚀刻以获得具有较短距离之接触孔以减小薄膜晶体管之源、漏极间之沟道宽度，达到提高TFT性能及满足面板的高分辨率之需求。
以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或等同替换，而不脱离本发明技术方案的精神和范围。
Claims (9)
1.一种薄膜晶体管，包括：
一栅极；
一覆盖该栅极之栅极绝缘层；
在该栅极绝缘层上对应该栅极处的沟道层；
一覆盖该沟道层之蚀刻阻挡层，该蚀刻阻挡层为一层迭结构，至少包括一有机阻挡层及与该有机阻挡层一硬遮罩层，该有机阻挡层与该硬遮罩层层迭设置，该有机阻挡层为经固化处理之透明有机材料层，该硬遮罩层形成在该有机阻挡层背离该沟道层之表面上，用于增强该有机阻挡层之硬度；
贯穿该蚀刻阻挡层之二接触孔；及
经由该二接触孔与该沟道层相连之源极与漏极。
2.根据权利要求1所述的薄膜晶体管，其特征在于，该有机阻挡层具有光敏特性，且该有机阻挡层之光敏特性弱于光阻材料之光敏特性。
3.根据权利要求1所述的薄膜晶体管，其特征在于，该硬遮罩层之厚度小于该有机阻挡层的厚度。
4.根据权利要求1所述的薄膜晶体管，其特征在于，该硬遮罩层材料为氮氧化硅、氮化硅、氧化硅或氟化硅。
5.根据权利要求1所述的薄膜晶体管，其特征在于，该二接触孔之间距距离小于10微米。
6.根据权利要求1所述的薄膜晶体管，其特征在于，该二接触孔之间距距离在3-5微米之间。
7.根据权利要求1所述的薄膜晶体管，其特征在于，该沟道层材料为金属氧化物半导体。
8.根据权利要求7所述的薄膜晶体管，其特征在于，该金属氧化物半导体选自氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟(InO)、氧化镓(GaO)之一或其混合物。
9.一种薄膜晶体管阵列基板，包括多条相互平行的栅极线、多条相互平行且与该些栅极线绝缘相交的数据线，每一栅极线与一资料线交叉处设置一薄膜晶体管；该薄膜晶体管为请求项1-8任意一项所述的薄膜晶体管。
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