CN104422865B - Wafer scale one-off programming OTP chip detecting methods and device - Google Patents
Wafer scale one-off programming OTP chip detecting methods and device Download PDFInfo
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Abstract
The present invention provides a kind of wafer scale one-off programming OTP chip detecting methods and device, and methods described includes：According to test program, one-off programming OTP chips itself are tested, the advance burning of test program is in the one-off programming read-only storage OTP ROM for users to use of the OTP chips；Ultraviolet erasing treatment is carried out to the OTP chips.Wafer scale OTP chip detecting methods and device that the present invention is provided, by the test program according to advance burning in OTP ROM for users to use, the OTP chips are tested, and the scheme of ultraviolet erasing treatment is carried out to the OTP chips, without embedding the OTP ROM for being exclusively used in depositing test program in OTP chips, so as to realize carrying out effective test to chip in the case where cost is limited.
Description
Technical Field
The invention relates to the field of integrated circuit testing, in particular to a wafer-level one-time programming (OTP) chip testing method and device.
Background
In the existing integrated circuit test scheme, in order to improve the test coverage as much as possible and detect a failed Chip as soon as possible, a wafer Probing (CP) test is usually performed on the Chip, that is, the Chip is tested before being packaged. The CP test of the chip comprises two parts, namely, an IP test which is preset aiming at the OTP ROM in the OTP chip, and a function test which is carried out aiming at the OTP chip.
The existing functional test scheme is that an OTP ROM specially used for storing a test program is embedded in a chip, and the test program is burned into the chip, so that the test program is controlled to operate by the OTP chip to realize functional test. The scheme can basically realize the simulation of the situation when the user uses the chip. However, the area of the OTP ROM dedicated for storing the test program in the test scheme usually occupies more than 20% of the total area of the chip, which inevitably results in an increase in the total area and cost of the chip. In practical applications, since the production cost of most chips is limited, the above chip testing scheme cannot be applied, that is, the existing chip testing scheme cannot effectively test the chips under the condition of limited cost.
Disclosure of Invention
The invention provides a wafer-level one-time programming OTP chip testing method and device, which are used for solving the problem that the existing chip testing scheme can not effectively test a chip under the condition of limited cost.
The invention provides a wafer level one-time programming (OTP) chip testing method, which comprises the following steps:
testing the one-time programming OTP chip per se according to a test program, wherein the test program is burnt in advance in a one-time programming read-only memory (OTP ROM) of the OTP chip for a user to use;
and after the test is finished, carrying out ultraviolet erasing treatment on the OTP chip so as to recover the one-time programming function of the OTPROM for the user.
Another aspect of the present invention provides a wafer level OTP chip testing apparatus, including:
the first processing module is used for testing the one-time programming OTP chip per se according to a test program which is burnt in advance in a one-time programming read-only memory (OTP ROM) of the OTP chip for a user to use;
and the erasing module is used for carrying out ultraviolet erasing treatment on the OTP chip after the test is finished so as to recover the one-time programming function of the OTP ROM used by the user.
According to the chip testing method and device provided by the invention, the OTP chip is tested according to the test program which is pre-burnt in the One Time Programmable Read Only Memory (OTP ROM for short) used by a user, and the scheme of ultraviolet ray erasing processing is carried out on the OTP chip, so that the OTPROM special for storing the test program is not required to be embedded in the chip, and the chip is effectively tested under the condition of limited cost.
Drawings
Fig. 1 is a schematic flowchart of a wafer-level OTP chip testing method according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of another wafer-level OTP chip testing method according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a wafer-level OTP chip testing apparatus according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
Fig. 1 is a schematic flow chart of a wafer level One Time Programmable (OTP) chip testing method according to an embodiment of the present invention, as shown in fig. 1, where the method includes:
101. the OTP chip is tested according to a test program, and the test program is burnt in advance in a One Time Programmable Read only memory (OTP ROM for short) of the OTP chip for a user to use.
In practical applications, the OTP chip may be an OTP Micro control Unit (MCU for short). The test program can be a program which is written in advance according to a test target to be realized as required and is burnt in the OTP ROM of the OTP chip.
Wherein the test program may include a plurality of sub-test programs; each sub-test program corresponds to at least one functional test, that is, by controlling the OTP chip to run each sub-test program, at least one functional test can be performed on the OTP chip. Specifically, 101 may include:
resetting the OTP chip to obtain a current selection identifier;
if the selection identifier is not one of the plurality of preset identifiers, performing a function test on the OTP chip by controlling the OTP chip to run a preset initial sub-test program, if the function test is passed, setting the selection identifier as any one of the plurality of identifiers, and executing the step of resetting the OTP chip again;
the initial sub-test program is any one of the plurality of sub-test programs, and the plurality of identifications are in one-to-one correspondence with other sub-test programs except the initial sub-test program in the plurality of sub-test programs;
if the selection identifier is one of the identifiers, the OTP chip is subjected to a function test by controlling the OTP chip to operate the sub-test program corresponding to the selection identifier, if the function test is passed, the selection identifier is set to be the identifier corresponding to any sub-test program which is not operated by the OTP chip currently, and the step of resetting the OTP chip is executed again until the function tests corresponding to the sub-test programs are all passed, the OTP chip is qualified, otherwise, the OTP chip is unqualified.
Specifically, if any test fails, the OTP chip fails, and generally, if any test fails, the test on the OTP chip is directly ended. In practical application, the selection identifier can be set by setting the current identifier of the identifier register, and accordingly, the first-obtained selection identifier can be a randomly or default identifier after the identifier register is opened.
In addition, a specific method for determining a sub-test program that is not currently run by the OTP chip may include multiple methods, for example, after the OTP chip is subjected to a function test by controlling the OTP chip to run the sub-test program corresponding to the selection identifier, and then the run identifier is added to the sub-test program, and accordingly, the sub-test program that does not carry the run identifier is the sub-test program that is not run by the OTP chip; for another example, after the OTP chip is controlled to run the sub-test program corresponding to the selection identifier and the function of the OTP chip is tested, the identifier corresponding to the run sub-test program is deleted, and all the sub-test programs corresponding to the currently stored identifiers are the sub-test programs that are not run by the OTP chip.
In this embodiment, the selection identifier is set to control the OTP chip to run each sub-test program, so as to perform a functional test on the OTP chip. Compared with the existing chip testing method, the method can effectively improve the efficiency of chip testing.
It should be noted that, in this embodiment, the testing the OTP chip according to the pre-programmed test program includes, but is not limited to, the foregoing embodiments, and other embodiments are not described herein again.
Optionally, in any of the above embodiments, before the performing the functional test on the OTP chip, the method may further include:
and adding a corresponding functional test identifier for the functional test.
Correspondingly, after the performing the functional test on the OTP chip, the method may further include:
and if the functional test fails, outputting a chip disqualification message comprising a functional test identifier corresponding to the functional test.
In practical applications, the method for outputting the chip fail message including the function test identifier corresponding to the function test failing to pass the test may be to display the function test identifier corresponding to the function test through a display device, or to map the function test identifier corresponding to the function test through a port outputting the chip fail message. For example, a one-to-one corresponding port is set for each functional test identifier corresponding to each functional test in advance, and the corresponding functional test identifier can be obtained according to the port outputting the chip failure message, so that the failed functional test is further determined according to the functional test identifier.
Through the embodiment, if the OTP chip is unqualified, the failed functional test can be directly determined according to the output unqualified chip message including the functional test identifier corresponding to the failed test, so that the defect of the chip can be conveniently checked and analyzed.
In addition, in practical application, besides performing the function test on the OTP chip, the performance parameter test corresponding to a certain function test can be further performed on the OTP chip according to the test result of the function test.
Then, optionally, in any of the above embodiments, the subtest program may correspond to a function test, and then further, after the setting the selection identifier as any identifier of the plurality of identifiers, or the setting the selection identifier as an identifier corresponding to any subtest program that is not currently run by the OTP chip, the method may further include:
acquiring a test excitation signal corresponding to the function test, and performing performance parameter test on the OTP chip according to the test excitation signal;
the step of resetting the OTP chip is executed again, which specifically includes:
and if the performance parameter test is passed, executing the step of resetting the OTP chip again.
Optionally, after the performance parameter test is performed on the OTP chip according to the test stimulus signal, the method further includes: and if the performance parameter test fails, outputting a chip disqualification message. In practical application, the unqualified chip message can be output through the testing machine.
102. And after the test is finished, carrying out ultraviolet erasing treatment on the OTP chip to recover the one-time programming function of the OTP ROM for the user to use.
Specifically, the specific method of the uv erasing process is not described herein.
In addition, in practical applications, before 101, the OTP chip is usually subjected to a first IP test. Specifically, the first IP test may be predetermined by an IP provider, and for example, the first IP test may include a first UV erase UV1, a first wafer probe (CP) test (i.e., CP1, which generally includes an open short test open short, OTP blank check, burning preconfigured data, and verifying the burned data), baking BAKE, a second CP test (i.e., CP2, which generally includes open short, and verifying the burned data in the first CP test again), and a second UV erase UV 2. Wherein, the temperature and time of baking can be preset.
Optionally, in practical applications, after 102, the method may further include: and carrying out second IP test on the OTP chip. Similarly, the second IP test may be predetermined, for example, the second IP test may include an open short and an OTP check.
According to the chip testing method provided by the embodiment, the OTP chip is tested according to the testing program which is pre-burned in the OTP ROM for the user to use, and the ultraviolet ray erasing processing is carried out on the OTP chip, so that the OTP ROM special for storing the testing program is not required to be embedded in the chip, and the chip is effectively tested under the condition of limited cost.
Fig. 2 is a schematic flow chart of another chip testing method according to a second embodiment of the present invention, and as shown in fig. 2, the method includes:
201. resetting the OTP chip to obtain a current selection identifier;
202. detecting whether the selected identifier is one of a plurality of preset identifiers, if not, executing 203, and if so, executing 208;
203. the OTP chip is subjected to a function test by controlling the OTP chip to run an initial sub-test program;
204. detecting whether the functional test is passed, if so, executing 205, otherwise, executing 214;
205. acquiring a test excitation signal corresponding to the function test, and performing performance parameter test on the OTP chip according to the test excitation signal;
206. detecting whether the performance parameter test passes, if so, executing 207, otherwise, executing 214;
207. setting the selection identifier as any one of the plurality of identifiers, and returning to execute 201;
208. the OTP chip is subjected to function test by controlling the OTP chip to run a sub-test program corresponding to the selection identifier;
209. detecting whether the functional test passes, if so, executing 210, otherwise, executing 214;
210. acquiring a test excitation signal corresponding to the function test, and performing performance parameter test on the OTP chip according to the test excitation signal;
211. detecting whether the performance parameter test passes, if so, executing 212, otherwise, executing 214;
212. setting the selection identifier as an identifier corresponding to any sub-test program which is not operated by the OTP chip currently, and returning to execute 201;
213. if the functional tests corresponding to the sub-test programs all pass the test, the OTP chip is qualified;
214. and finishing the test and outputting a chip fail message.
The plurality of sub-test programs are all pre-burned in an OTP ROM of the OTP chip for a user to use, the initial sub-test program is any one of the plurality of sub-test programs, and the plurality of identifications correspond to other sub-test programs except for the preset initial sub-test program in the plurality of sub-test programs in a one-to-one mode. The specific method of each step in this embodiment can be referred to as the specific method of the corresponding step in the first embodiment.
According to the wafer-level OTP chip testing method provided by the embodiment, the OTP chip is tested according to the testing program which is pre-burned in the OTPROM for the user, and the OTP chip is subjected to ultraviolet erasing processing, so that an OTP ROM special for storing the testing program is not required to be embedded in the chip, and the chip is effectively tested under the condition of limited cost.
Fig. 3 is a schematic structural diagram of a wafer-level OTP chip testing apparatus according to a third embodiment of the present invention, as shown in fig. 3, the apparatus includes: a first processing module 31 and an erasing module 32; wherein,
the first processing module 31 is configured to test the OTP chip according to a test program, where the test program is burned in the OTP ROM of the OTP chip for a user to use in advance;
and the erasing module 32 is used for performing ultraviolet erasing treatment on the OTP chip after the test is finished so as to recover the one-time programming function of the OTP ROM used by the user.
Wherein the test program may include a plurality of sub-test programs; each sub-test program corresponds to at least one functional test, that is, by controlling the OTP chip to run each sub-test program, at least one functional test can be performed on the OTP chip.
Specifically, the processing module 31 may include:
the acquisition unit is used for resetting the OTP chip and acquiring the current selection identifier;
a first processing unit, configured to perform a function test on the OTP chip by controlling the OTP chip to run a preset initial sub-test program if the selection identifier is not one of the preset identifiers, set the selection identifier as any one of the plurality of identifiers if the function test passes, and perform the step of resetting the OTP chip again;
the initial sub-test program is any one of the plurality of sub-test programs, and the plurality of identifications are in one-to-one correspondence with other sub-test programs except the initial sub-test program in the plurality of sub-test programs;
a second processing unit, configured to perform a function test on the OTP chip by controlling the OTP chip to run a sub-test program corresponding to the selection identifier if the selection identifier is one of the identifiers, set the selection identifier as an identifier corresponding to any sub-test program that is not currently run by the OTP chip if the function test passes, and perform the step of resetting the OTP chip again;
and the judging unit is used for judging that the OTP chip is qualified if the functional tests corresponding to the sub-test programs all pass the test, and otherwise, judging that the OTP chip is unqualified.
Still optionally, in the above embodiment, the apparatus may further include:
the identification module is used for adding a corresponding functional test identification for the functional test before the first processing unit or the second processing unit performs the functional test on the OTP chip;
and the output module is used for outputting a chip unqualified message including a functional test identifier corresponding to the functional test if the functional test fails after the first processing unit or the second processing unit performs the functional test on the OTP chip.
Through the embodiment, if the OTP chip is unqualified, the failed functional test can be directly determined according to the output unqualified chip message including the functional test identifier corresponding to the failed test, so that the defect of the chip can be conveniently checked and analyzed.
In addition, in practical application, besides the function test of the OTP chip, the performance parameter test corresponding to the function test can be further performed on the OTP chip according to the test result of the function test. Then, optionally, in any of the above embodiments, the sub-test program may correspond to a functional test, and the apparatus may further include:
the second processing module is configured to, after the first processing unit sets the selection identifier as any one of the plurality of identifiers, or the second processing unit sets the selection identifier as an identifier corresponding to any one of sub-test programs that are not currently run by the OTP chip, acquire a test stimulus signal corresponding to the functional test, and perform a performance parameter test on the OTP chip according to the test stimulus signal;
the second processing module is further configured to instruct the obtaining unit to perform the step of resetting the OTP chip again if the performance parameter test passes.
Further optionally, in the above embodiment, the output module is further configured to output a chip fail message if the performance parameter test fails after the second processing module performs the performance parameter test on the OTP chip according to the test excitation signal.
According to the wafer-level OTP chip testing device provided by the embodiment, the OTP chip is tested according to the testing program which is pre-burned in the OTPROM for the user, and the OTP chip is subjected to ultraviolet erasing processing, so that an OTP ROM special for storing the testing program is not required to be embedded in the chip, and the chip is effectively tested under the condition of limited cost.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working process of the apparatus described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
In addition, compared with the above scheme, the other three chip test methods currently exist are a test mode, a scan chain mode, and a mode combining the test mode and the scan chain. The test mode is specifically that a test module special for testing is embedded in a chip; receiving a test program transmitted by a test machine through a pin (in a wafer stage, the pin is a welding spot base contacted with a probe) on the test module; and running the test program on the chip to test the chip. The scan chain mode is specifically that a Design For Testability (DFT) module is embedded in a chip; and scanning the connectivity and the input-output relation of all digital logic nodes in the chip through the DFT module, and testing the chip. The mode of combining the test mode and the scan chain is specifically that the test module and the DFT module are embedded in a chip, and the scan chain mode is adopted when testing a digital circuit; when testing an analog circuit or an analog-digital hybrid circuit, a test mode is used. The above description generally illustrates the three modes of the scheme, and the corresponding specific test methods thereof are not further described here.
Compared with the above chip testing scheme, in the wafer-level OTP chip testing method provided in the embodiment of the present invention, the OTP chip may include, but is not limited to: digital circuit chip, analog circuit chip and digital-analog hybrid circuit chip. And the OTP chip is programmed in the OTP ROM for the user to use and is controlled to run the test program, so that the situation of the user using the chip is simulated to the maximum extent, and the test accuracy, reliability and test coverage rate are improved. Compared with the mode, the scheme does not need to convert the test program in the test process, so that the high-frequency limit test of the chip can be realized, and the redundancy of the performance index when a user uses the chip can be ensured.
Optionally, after 102, if it is required to perform testing again for some critical chip functions, after 102, the chip may be tested again by any one of the three chip testing methods described above. The detailed description of the retest is omitted here.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A wafer-level one-time programming (OTP) chip testing method is characterized by comprising the following steps:
testing the one-time programming OTP chip per se according to a test program, wherein the test program is burnt in advance in a one-time programming read-only memory (OTP ROM) of the OTP chip for a user to use;
after the test is finished, carrying out ultraviolet ray erasing treatment on the OTP chip so as to recover the one-time programming function of the OTP ROM for the user to use;
the test program comprises a plurality of sub-test programs; each sub-test program corresponds to at least one functional test; the testing the OTP chip according to the test program specifically includes:
resetting the OTP chip to obtain a current selection identifier;
if the selection identifier is not one of the plurality of preset identifiers, performing a function test on the OTP chip by controlling the OTP chip to run a preset initial sub-test program, if the function test is passed, setting the selection identifier as any one of the plurality of identifiers, and executing the step of resetting the OTP chip again;
the initial sub-test program is any one of the plurality of sub-test programs, and the plurality of identifications are in one-to-one correspondence with other sub-test programs except the initial sub-test program in the plurality of sub-test programs;
if the selection identifier is one of the identifiers, the OTP chip is subjected to a function test by controlling the OTP chip to operate the sub-test program corresponding to the selection identifier, if the function test is passed, the selection identifier is set to be the identifier corresponding to any sub-test program which is not operated by the OTP chip currently, and the step of resetting the OTP chip is executed again until the function tests corresponding to the sub-test programs are all passed, the OTP chip is qualified, otherwise, the OTP chip is unqualified.
2. The method of claim 1, wherein before the performing the functional test on the OTP chip, the method further comprises:
adding a corresponding functional test identifier for the functional test;
after the function test is performed on the OTP chip, the method further includes:
and if the functional test fails, outputting a chip disqualification message comprising a functional test identifier corresponding to the functional test.
3. The method of claim 1 or 2, wherein the sub-test program corresponds to a functional test; after the setting of the selection identifier as any one of the plurality of identifiers, or the setting of the selection identifier as an identifier corresponding to any sub-test program which is not currently run by the OTP chip, the method further includes:
acquiring a test excitation signal corresponding to the function test, and performing performance parameter test on the OTP chip according to the test excitation signal;
the step of resetting the OTP chip is executed again, which specifically includes:
and if the performance parameter test is passed, executing the step of resetting the OTP chip again.
4. The method of claim 3, wherein after the testing the performance parameters of the OTP chip according to the test stimulus signal, the method further comprises:
and if the performance parameter test fails, outputting a chip disqualification message.
5. A wafer level one-time programming (OTP) chip testing device is characterized by comprising:
the first processing module is used for testing the one-time programming OTP chip per se according to a test program which is burnt in advance in a one-time programming read-only memory (OTP ROM) of the OTP chip for a user to use;
the erasing module is used for carrying out ultraviolet erasing treatment on the OTP chip after the test is finished so as to recover the one-time programming function of the OTP ROM used by a user;
the test program comprises a plurality of sub-test programs; each sub-test program corresponds to at least one functional test; the first processing module comprises:
the acquisition unit is used for resetting the OTP chip and acquiring the current selection identifier;
a first processing unit, configured to perform a function test on the OTP chip by controlling the OTP chip to run a preset initial sub-test program if the selection identifier is not one of the preset identifiers, set the selection identifier as any one of the plurality of identifiers if the function test passes, and perform the step of resetting the OTP chip again;
the initial sub-test program is any one of the plurality of sub-test programs, and the plurality of identifications are in one-to-one correspondence with other sub-test programs except the initial sub-test program in the plurality of sub-test programs;
a second processing unit, configured to perform a function test on the OTP chip by controlling the OTP chip to run a sub-test program corresponding to the selection identifier if the selection identifier is one of the identifiers, set the selection identifier as an identifier corresponding to any sub-test program that is not currently run by the OTP chip if the function test passes, and perform the step of resetting the OTP chip again;
and the judging unit is used for judging that the OTP chip is qualified if the functional tests corresponding to the sub-test programs all pass the test, and otherwise, judging that the OTP chip is unqualified.
6. The apparatus of claim 5, further comprising:
the identification module is used for adding a corresponding functional test identification for the functional test before the first processing unit or the second processing unit performs the functional test on the OTP chip;
and the output module is used for outputting a chip unqualified message including a functional test identifier corresponding to the functional test if the functional test fails after the first processing unit or the second processing unit performs the functional test on the OTP chip.
7. The apparatus of claim 6, wherein the sub-test program corresponds to a functional test, the apparatus further comprising:
the second processing module is configured to, after the first processing unit sets the selection identifier as any one of the plurality of identifiers, or the second processing unit sets the selection identifier as an identifier corresponding to any one of sub-test programs that are not currently run by the OTP chip, acquire a test stimulus signal corresponding to the functional test, and perform a performance parameter test on the OTP chip according to the test stimulus signal;
the second processing module is further configured to instruct the obtaining unit to perform the step of resetting the OTP chip again if the performance parameter test passes.
8. The apparatus of claim 7,
the output module is further configured to output a chip failure message if the performance parameter test fails after the second processing module performs the performance parameter test on the OTP chip according to the test excitation signal.
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| CN108255278B (en) * | 2017-12-11 | 2019-11-15 | 维沃移动通信有限公司 | The powering method and device of OTP memory cell |
| CN109283451B (en) * | 2018-09-18 | 2020-12-29 | 电子科技大学 | Integrated circuit good product detection system and method |
| CN109541426B (en) * | 2018-11-21 | 2021-09-24 | 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 | Method for automatically reading parameters by tester in wafer test |
| CN109817270B (en) * | 2018-12-26 | 2020-12-29 | 嘉兴威伏半导体有限公司 | Test method of embedded OTP 8-bit MCU chip |
| CN109889722B (en) * | 2019-01-04 | 2021-01-26 | 信利光电股份有限公司 | High-low temperature shooting method and device of camera and camera |
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