CN104407305B - A kind of Power Integrity test device and method - Google Patents
A kind of Power Integrity test device and method Download PDFInfo
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- CN104407305B CN104407305B CN201410614538.1A CN201410614538A CN104407305B CN 104407305 B CN104407305 B CN 104407305B CN 201410614538 A CN201410614538 A CN 201410614538A CN 104407305 B CN104407305 B CN 104407305B
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- power
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- power supply
- integrity test
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Abstract
The invention discloses a kind of Power Integrity test device and method, test device is arranged between power input port CON1 and output port of power source CON2, including trigger switch circuit, monostable flipflop, Schmidt's reverser, d type flip flop circuit, NPN type triode and P-channel metal-oxide-semiconductor Q2；The input of the output end order steady state trigger of trigger switch circuit, the output end of monostable flipflop connects the input of d type flip flop circuit by Schmidt's reverser U4, the output end of d type flip flop circuit connects triode Q1 base stage by resistance R8, triode Q1 grounded emitter, triode Q1 colelctor electrode connects metal-oxide-semiconductor Q2 grid by resistance R7, metal-oxide-semiconductor Q2 source electrode meets power input port CON1, and drain electrode meets output port of power source CON2.Test device and method provided by the invention, the operating efficiency of Test Engineer can be improved, and it is simple and easy to use, and cost is cheap.
Description
Technical field
The present invention relates to testing field, more particularly, to a kind of high Power Integrity test device of testing efficiency and side
Method.
Background technology
Voltage/the signal waveform or sequential relationship of upper electric or lower electric moment was often tested in Power Integrity test, is kept away
Such difficulty can unavoidably be faced：
If the electrical waveform up and down of a signal the 1st, is simply tested, it is necessary to which a hand is used for being surveyed by oscilloprobe
Examination, hand are used for stirring power switch, are so manipulable reluctantly, but if for the equipment of no power switch,
With a hand plug attaching plug, another hand is used for testing just becoming extremely difficult；
2nd, if necessary to the sequential relationship tested in power-on and power-off moment between 2 voltage/signals, colleague must be just looked for assist
Or welding p-wire（It is clipped on the clip of probe）, it thus is not avoided that the time that can delay colleague or in p-wire is welded
Lose time.It is related to individual signal up to more than 20 especially for more complicated veneer, such as electrifying timing sequence of PC computer main boards,
Test spends the time on welding p-wire very more.
The content of the invention
The present invention provides a kind of high Power Integrity of testing efficiency and surveyed first to overcome the shortcomings of described in above-mentioned prior art
Trial assembly is put so that tester need not weld p-wire in the case where being assisted without other people also can be easily competent.
A further object of the present invention is to propose a kind of Power Integrity method of testing.
To achieve these goals, technical scheme is as follows：
A kind of Power Integrity test device, is arranged between power input port CON1 and output port of power source CON2,
Including：Trigger switch circuit, monostable flipflop, Schmidt's reverser, d type flip flop circuit, NPN type triode and P-channel MOS
Pipe Q2；
The input of the output end order steady state trigger of the trigger switch circuit, the output end of monostable flipflop are led to
The input that Schmidt's reverser U4 connects d type flip flop circuit is crossed, the output end of d type flip flop circuit connects NPN type three by resistance R8
The base stage of pole pipe, the grounded emitter of NPN type triode, the colelctor electrode of NPN type triode connect metal-oxide-semiconductor Q2 grid by resistance R7
Pole, metal-oxide-semiconductor Q2 source electrode meet power input port CON1, and metal-oxide-semiconductor Q2 drain electrode meets output port of power source CON2.
A kind of Power Integrity method of testing, including：
User sets the capacitance of capacitor array and resistance R4 resistance to obtain different time intervals according to demand；
The power input port CON1 of Power Integrity test device is accessed to the output port of power source of power supply, by electricity
The power input port of the output port of power source access Devices to test of source integrity test device, i.e., test this Power Integrity
Device is sealed between Devices to test and power supply；
Switch SW1 is clicked, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, by electricity
Electric on Devices to test after holding the time interval that array C and toggle switch SW2 is set, user can test the electricity in power up
Pressure/signal waveform；
Switch SW1 is clicked, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, by electricity
Electric under equipment to be tested after holding the time interval that array C and toggle switch SW2 is set, user can be tested in lower electric process
Voltage/signal waveform.
Compared with prior art, the beneficial effect of technical solution of the present invention is：Power Integrity test provided by the invention
Device, the operating efficiency of Test Engineer can be improved, and it is simple and easy to use, and cost is cheap.
Brief description of the drawings
Fig. 1-5 is the circuit theory diagrams of Power Integrity testing auxiliary device of the present invention.
Fig. 6 is each point in circuit of the invention（A-H）Oscillogram.
Fig. 7 is the schematic diagram of Power Integrity testing auxiliary device of the present invention.
Embodiment
Accompanying drawing being given for example only property explanation, it is impossible to be interpreted as the limitation to this patent；
In order to more preferably illustrate the present embodiment, some parts of accompanying drawing have omission, zoomed in or out, and do not represent actual product
Size；
To those skilled in the art, it is to be appreciated that some known features and its explanation, which may be omitted, in accompanying drawing
's.
Technical scheme is described further with reference to the accompanying drawings and examples.
Embodiment 1
Such as Fig. 1-5, a kind of Power Integrity test device, power input port CON1 and output port of power source are arranged on
Between CON2, including：Trigger switch circuit, monostable flipflop, Schmidt's reverser, d type flip flop circuit, linear stabilized power supply
Module, NPN type triode and P-channel metal-oxide-semiconductor Q2；
The input of the output end order steady state trigger of the trigger switch circuit, the output end of monostable flipflop are led to
The input that Schmidt's reverser U4 connects d type flip flop circuit is crossed, the output end of d type flip flop circuit connects NPN type three by resistance R8
The base stage of pole pipe, the grounded emitter of NPN type triode, the colelctor electrode of NPN type triode connect metal-oxide-semiconductor Q2 grid by resistance R7
Pole, metal-oxide-semiconductor Q2 source electrode meet power input port CON1, and metal-oxide-semiconductor Q2 drain electrode connects output port of power source CON2, linear voltage stabilization electricity
Source module exports 5V voltages and powered to each electrical part of Power Integrity test device.
In the present embodiment, trigger switch circuit includes switch SW1, Schmidt's reverser U1 and the Schmidt being sequentially connected with
Reverser U3；The effect of trigger switch circuit is to click switch SW1 to produce a low pulse.Monostable flipflop includes
555 timer U2 and peripheral circuit, the peripheral circuit include capacitor array C, toggle switch SW2 and resistance R4,555 timers
U2 TH pin connect 5V power supplys by resistance R4, and 555 timer U2 TH pin connect Dc pin, shunt-wound capacitance array C positive pole, electric capacity battle array
Row C negative pole is grounded by toggle switch SW2；D type flip flop circuit includes two-way D types rising edge flip-flops and peripheral circuit.Line
Property power module of voltage regulation includes toggle switch SW3 and linear stabilized power supply LDO, and the power input passes through toggle switch SW3
Linear stabilized power supply LDO is met, linear stabilized power supply LDO output 5V voltages, each electrical part of Power Integrity test device is powered.
During stable state in monostable flipflop 555 timer U2 output end（3 pins）Vo exports low level, is born when there is one
Pulse signal Vi is added to input（2 pins）, and its current potential is be momentarily less than (1/3) × 5V, it is high that output end vo can invert output
Level, capacitor array C（C5-C9 parallel connection）Start to charge up, when Vc is charged to (2/3) × 5V, output end vo returns from high level
Low level is returned, returns to stable state, and get ready for coming for next trigger pulse.
Output end exports duration T W=1.1*R4*C of high pulsewidth, and R4 takes 390K ohms in the present embodiment, and C is one
Capacitor array, by toggle switch SW2 select capacitor array in each electric capacity whether access circuit, the effect so done be for
Regulation exports the different in width of high pulsewidth, and C5-C9 is 10UF in example, so the adjustable-width of high pulsewidth is about 4S-
Between 20S, user can also realize the high pulsewidth of different in width using different R4 and capacitor array capacitance.
The anti-phase high pulsewidth that Schmidt's reverser U4 can export 555 timer U2 is low pulsewidth；D type flip flop circuit it is defeated
The signal PS_ON for going out end acquiescence output is low level, as long as giving a rising edge of a pulse at its CP end, the level of output will be sent out
Raw reversion.
CON1 is the power input port of Power Integrity test device, and CON2 is the power supply of Power Integrity test device
Output port.When PS_ON signals are high level, metal-oxide-semiconductor Q2 is turned on, and the power supply of power input port flows to output port of power source.
When PS_ON signals are low level, metal-oxide-semiconductor Q2 is by power input port and output port of power source are isolations.
Linear stabilized power supply LDO U6 are the logic that the voltage conversion of input power is 5V power supply source integrity test devices
Circuit uses.SW3 is a toggle switch, and effect is that higher than 5V, (conventional has 12V, 19V, 24V, 48V when input supply voltage
Deng), the dial-up in 1-4 directions is connected and the dial-up in 2-3 directions disconnects, i.e., using LDO U6 voltage conversion function；Work as input
When supply voltage is equal to 5V, the dial-up in 1-4 directions is disconnected and the dial-up in 2-3 directions is connected, at this moment apparatus logic circuit uses
The 5V power supplys that are directly accessed using equipment input of 5V power supplys.
Such as Fig. 6, each point in circuit in Power Integrity test device（A-H）Waveform：
Power Integrity test device application method and the function of finally realizing are as follows：
1st, user sets toggle switch SW3 according to access supply voltage, connects the dial-up in 1-4 directions when voltage is more than 5V
And the dial-up in 2-3 directions disconnects；When voltage is equal to, 5V disconnects the dial-up in 1-4 directions and the dial-up in 2-3 directions is connected.
2nd, user is according to self-demand（By needed after switch key SW1 interval how long on Devices to test electricity or under
Electricity）Capacitor array toggle switch SW2 is set, and it is 4S that the 4 of toggle switch SW2 switch is all off in this example, and 1 closure is
8S, 2 closures are 12S, and 3 closures are 16S, and 4 closures are 20S.Certainly this is an example, and user can also be according to itself
Demand sets different R4 resistance values and the capacitance of capacitor array to obtain different time intervals in circuit.
The 3rd, the power input port CON1 of this equipment is accessed to the output port of power source of power supply, by the power supply of this equipment
Output port accesses the power input port of Devices to test, i.e., this equipment is sealed between Devices to test and power supply.
4th, the switch key SW1 of this equipment is clicked, user has the sufficient time by oscilloprobe point in Devices to test
Circuit in, after the time interval that capacitor array toggle switch is set, electric on Devices to test, at this moment user can be very convenient
Test power up in voltage/signal waveform.
5th, the switch key SW1 of this equipment is clicked, user has the sufficient time by oscilloprobe point in Devices to test
Circuit in, after the time interval that capacitor array toggle switch is set, electric under equipment to be tested, at this moment user can be very square
Just voltage/signal waveform under test in electric process.
Same or analogous label corresponds to same or analogous part；
Position relationship is used for being given for example only property explanation described in accompanying drawing, it is impossible to is interpreted as the limitation to this patent；
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not pair
The restriction of embodiments of the present invention.For those of ordinary skill in the field, may be used also on the basis of the above description
To make other changes in different forms.There is no necessity and possibility to exhaust all the enbodiments.It is all this
All any modification, equivalent and improvement made within the spirit and principle of invention etc., should be included in the claims in the present invention
Protection domain within.
Claims (7)
1. a kind of Power Integrity test device, is arranged between power input port CON1 and output port of power source CON2, its
It is characterised by, including：Trigger switch circuit, monostable flipflop, Schmidt's reverser, d type flip flop circuit, NPN type triode
With P-channel metal-oxide-semiconductor Q2；
The input of the output end order steady state trigger of the trigger switch circuit, the output end of monostable flipflop is by applying
Close special reverser U4 connects the input of d type flip flop circuit, and the output end of d type flip flop circuit connects NPN type triode by resistance R8
Base stage, the grounded emitter of NPN type triode, the colelctor electrode of NPN type triode connects metal-oxide-semiconductor Q2 grid by resistance R7,
Metal-oxide-semiconductor Q2 source electrode meets power input port CON1, and metal-oxide-semiconductor Q2 drain electrode meets output port of power source CON2.
2. Power Integrity test device according to claim 1, it is characterised in that also including linear stabilized power supply mould
Block, the linear stabilized power supply module include toggle switch SW3 and linear stabilized power supply LDO, the power input port CON1
Linear stabilized power supply LDO is connect by toggle switch SW3, linear stabilized power supply LDO output 5V voltages, Power Integrity is tested and filled
Put each electrical part power supply.
3. Power Integrity test device according to claim 1 or 2, it is characterised in that the trigger switch circuit bag
Include the switch SW1 being sequentially connected with, Schmidt's reverser U1 and Schmidt's reverser U3.
4. Power Integrity test device according to claim 3, it is characterised in that the monostable flipflop includes
555 timer U2 and peripheral circuit, the peripheral circuit include capacitor array C, toggle switch SW2 and resistance R4,555 timers
U2 TH pin connect 5V power supplys by resistance R4, and 555 timer U2 TH pin connect Dc pin, shunt-wound capacitance array C positive pole, electric capacity battle array
Row C negative pole is grounded by toggle switch SW2.
5. Power Integrity test device according to claim 4, it is characterised in that the d type flip flop circuit includes double
Road D types rising edge flip-flops and peripheral circuit.
6. a kind of Power Integrity method of testing of any one of claim 1 to 5 Power Integrity test device, its feature
It is, including：
User sets the capacitance of capacitor array and resistance R4 resistance to obtain different time intervals according to demand；
The power input port CON1 of Power Integrity test device is accessed to the output port of power source of power supply, power supply is complete
The power input port of the output port of power source access Devices to test of whole system safety testing device, i.e., this Power Integrity test device
Seal between Devices to test and power supply；
Switch SW1 is clicked, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, by electric capacity battle array
Voltage letter electric on Devices to test after arranging the time interval that C and toggle switch SW2 is set, that user can be tested in power up
Number waveform；
Switch SW1 is clicked, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, by electric capacity battle array
It is electric under equipment to be tested after arranging the time interval that C and toggle switch SW2 is set, the voltage that user can be tested in lower electric process
Signal waveform.
7. Power Integrity method of testing according to claim 6, it is characterised in that user sets according to access supply voltage
Toggle switch SW3 is put, sets toggle switch SW3 to cause voltage to carry out electricity by linear stabilized power supply LDO when voltage is more than 5V
Pressure conversion obtains 5V voltages, and is powered to each electrical part of Power Integrity test device；When voltage is equal to 5V, dial-up is set to open
Close SW3, the 5V power supplys directly accessed using equipment input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410614538.1A CN104407305B (en) | 2014-11-03 | 2014-11-03 | A kind of Power Integrity test device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410614538.1A CN104407305B (en) | 2014-11-03 | 2014-11-03 | A kind of Power Integrity test device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104407305A CN104407305A (en) | 2015-03-11 |
| CN104407305B true CN104407305B (en) | 2017-12-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410614538.1A Expired - Fee Related CN104407305B (en) | 2014-11-03 | 2014-11-03 | A kind of Power Integrity test device and method |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106546906B (en) * | 2016-11-01 | 2020-02-07 | 郑州云海信息技术有限公司 | Method and device for testing integrity of power supply |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201217804A (en) * | 2010-10-19 | 2012-05-01 | Himax Analogic Inc | Dc-to-dc converter having test circuit |
| CN202362411U (en) * | 2011-11-30 | 2012-08-01 | 珠海市华晶微电子有限公司 | Device for testing installing accuracy of speed regulation line |
| CN102749580A (en) * | 2012-07-27 | 2012-10-24 | 苏州贝腾特电子科技有限公司 | Test device |
| CN102749578A (en) * | 2012-07-27 | 2012-10-24 | 苏州贝腾特电子科技有限公司 | Detection device |
-
2014
- 2014-11-03 CN CN201410614538.1A patent/CN104407305B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201217804A (en) * | 2010-10-19 | 2012-05-01 | Himax Analogic Inc | Dc-to-dc converter having test circuit |
| CN202362411U (en) * | 2011-11-30 | 2012-08-01 | 珠海市华晶微电子有限公司 | Device for testing installing accuracy of speed regulation line |
| CN102749580A (en) * | 2012-07-27 | 2012-10-24 | 苏州贝腾特电子科技有限公司 | Test device |
| CN102749578A (en) * | 2012-07-27 | 2012-10-24 | 苏州贝腾特电子科技有限公司 | Detection device |
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| Publication number | Publication date |
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| CN104407305A (en) | 2015-03-11 |
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Address after: Kezhu road high tech Industrial Development Zone, Guangzhou city of Guangdong Province, No. 233 510670 Patentee after: VTRON GROUP Co.,Ltd. Address before: Kezhu road high tech Industrial Development Zone, Guangzhou city of Guangdong Province, No. 233 510670 Patentee before: VTRON TECHNOLOGIES Ltd. |
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Granted publication date: 20171226 Termination date: 20211103 |
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