CN104407305A - Power source integrity test device and method - Google Patents
Power source integrity test device and method Download PDFInfo
- Publication number
- CN104407305A CN104407305A CN201410614538.1A CN201410614538A CN104407305A CN 104407305 A CN104407305 A CN 104407305A CN 201410614538 A CN201410614538 A CN 201410614538A CN 104407305 A CN104407305 A CN 104407305A
- Authority
- CN
- China
- Prior art keywords
- power
- proving installation
- power supply
- power source
- toggle switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a power source integrity test device and a method. The power source integrity test device is arranged between a power source input port CON1 and a power source output port CON2 and comprises a trigger switch circuit, a monostable trigger, a Schmidt reverser, a D trigger circuit, an NPN type triode and a P-channel MOS tube Q2, wherein an output end of the trigger switch circuit is connected with an input end of the monostable trigger, an output end of the monostable trigger is connected with an input end of the D trigger circuit through the Schmidt reverser U4, an output end of the D trigger circuit is connected with a base electrode of the triode Q1 through a resistor R8, an emitter electrode of the triode Q1 is in grounding connection, a collector electrode of the triode Q1 is connected with a grid electrode of the P-channel MOS tube Q2 through a resistor R7, a source electrode of the P-channel MOS tube Q2 is connected with the power source input port CON1, and a drain electrode is connected with the power source input port CON2. The power source integrity test device and the method improve work efficiency of test engineers, are convenient and simple to use and realize low cost.
Description
Technical field
The present invention relates to field tests, more specifically, relate to a kind of testing efficiency height Power Integrity proving installation and method.
Background technology
Power Integrity test in often can test power on or lower electricity moment voltage/signal waveform or sequential relationship, keep away and unavoidably can face such difficulty:
If the power-on and power-off waveform of a 1 just test signal, a hand is needed to be used for taking oscilloprobe to test, a hand is used for stirring power switch, manipulable reluctantly like this, if but for not having the equipment of power switch, with a hand plug attaching plug, another hand is used for testing and just becomes very difficult;
If 2 need to test sequential relationship between 2 voltage/signals instantaneously in power-on and power-off, colleague just must be looked for assist or welding p-wire (being clipped on the clip of probe), keep away the time that unavoidably can delay colleague like this or lose time welding in p-wire.Particularly for the veneer of more complicated, the electrifying timing sequence as PC computer main board relates to nearly more than 20 signal, and test spends the time on welding p-wire very many.
Summary of the invention
The present invention, for overcoming the deficiency described in above-mentioned prior art, first provides a kind of testing efficiency height Power Integrity proving installation, and making tester not need to weld p-wire when assisting without other people also can be easily competent at a job.
Another object of the present invention proposes a kind of Power Integrity method of testing.
To achieve these goals, technical scheme of the present invention is as follows:
A kind of Power Integrity proving installation, is arranged between power input port CON1 and output port of power source CON2, comprises: triggered switch circuit, monostalbe trigger, Schmidt's reverser, d type flip flop circuit, NPN type triode and P channel MOS tube Q2;
The input end of the output terminal order steady state trigger of described triggered switch circuit, the output terminal of monostalbe trigger connects the input end of d type flip flop circuit by Schmidt's reverser U4, the output terminal of d type flip flop circuit connects the base stage of triode Q1 by resistance R8, the grounded emitter of triode Q1, the collector of triode Q1 connects the grid of metal-oxide-semiconductor Q2 by resistance R7, the source electrode of metal-oxide-semiconductor Q2 meets power input port CON1, and the drain electrode of metal-oxide-semiconductor Q2 meets output port of power source CON2.
A kind of Power Integrity method of testing, comprising:
User arranges the capacitance of capacitor array toggle switch SW2 and the resistance of resistance R4 according to demand to obtain the different time intervals;
The power input port CON1 of Power Integrity proving installation is accessed the output port of power source of power supply, by the power input port of the output port of power source of Power Integrity proving installation access Devices to test, namely this Power Integrity proving installation is sealed between Devices to test and power supply;
Click switch key SW1, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, after the time interval that capacitor array C and toggle switch SW2 is arranged, Devices to test powers on, and user can test the voltage/signal waveform in power up;
Click switch key SW1, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, after the time interval that capacitor array C and toggle switch SW2 is arranged, electricity under equipment to be tested, user can test the voltage/signal waveform in lower electric process.
Compared with prior art, the beneficial effect of technical solution of the present invention is: Power Integrity proving installation provided by the invention, can improve the work efficiency of Test Engineer, and simple and easy to use, with low cost.
Accompanying drawing explanation
Fig. 1-5 is the circuit theory diagrams of Power Integrity testing auxiliary device of the present invention.
Fig. 6 is the oscillogram of each point (A-H) in circuit of the present invention.
Fig. 7 is the schematic diagram of Power Integrity testing auxiliary device of the present invention.
Embodiment
Accompanying drawing, only for exemplary illustration, can not be interpreted as the restriction to this patent;
In order to better the present embodiment is described, some parts of accompanying drawing have omission, zoom in or out, and do not represent the size of actual product;
To those skilled in the art, in accompanying drawing, some known features and explanation thereof may be omitted is understandable.
Below in conjunction with drawings and Examples, technical scheme of the present invention is described further.
Embodiment 1
As Fig. 1-5, a kind of Power Integrity proving installation, be arranged between power input port CON1 and output port of power source CON2, comprise: triggered switch circuit, monostalbe trigger, Schmidt's reverser, d type flip flop circuit, linear stabilized power supply module, NPN type triode and P channel MOS tube Q2;
The input end of the output terminal order steady state trigger of described triggered switch circuit, the output terminal of monostalbe trigger connects the input end of d type flip flop circuit by Schmidt's reverser U4, the output terminal of d type flip flop circuit connects the base stage of triode Q1 by resistance R8, the grounded emitter of triode Q1, the collector of triode Q1 connects the grid of metal-oxide-semiconductor Q2 by resistance R7, the source electrode of metal-oxide-semiconductor Q2 meets power input port CON1, the drain electrode of metal-oxide-semiconductor Q2 meets output port of power source CON2, and linear stabilized power supply module exports 5V voltage and powers to each electrical part of Power Integrity proving installation.
In the present embodiment, triggered switch circuit comprises the interrupteur SW 1, Schmidt's reverser U1 and the Schmidt's reverser U3 that connect in turn; The effect of triggered switch circuit clicks interrupteur SW 1 will produce a low pulse.Monostalbe trigger comprises 555 timer U2 and peripheral circuits, described peripheral circuit comprises capacitor array C, toggle switch SW2 and resistance R4, the TH pin of 555 timer U2 connects 5V power supply by resistance R4, the TH pin of 555 timer U2 connects Dc pin, the positive pole of shunt-wound capacitance array C, the negative pole of capacitor array C is by toggle switch SW2 ground connection; D type flip flop circuit comprises two-way D type rising edge flip-flops and peripheral circuit.Linear stabilized power supply module comprises toggle switch SW3 and linear stabilized power supply LDO, and described power input meets linear stabilized power supply LDO by toggle switch SW3, and linear stabilized power supply LDO exports 5V voltage, powers to each electrical part of Power Integrity proving installation.
Output terminal (3 pin) the Vo output low level of 555 timer U2 in monostalbe trigger during stable state, input end (2 pin) is added to when there being a undersuing Vi, and make its current potential instantaneous lower than (1/3) × 5V, output end vo can reverse output high level, the parallel connection of capacitor array C(C5-C9) start charging, when Vc is charged to (2/3) × 5V, output end vo returns low level from high level, return to stable state, and get ready for coming of next trigger pulse.
Output terminal exports the duration T W=1.1*R4*C of high pulsewidth, in the present embodiment, R4 gets 390K ohm, C is a capacitor array, each electric capacity in capacitor array whether place in circuit is selected by toggle switch SW2, the effect done like this is the different in width in order to regulation output high pulsewidth, in example, C5-C9 is 10UF, so the adjustable-width of high pulsewidth is approximately between 4S-20S, user also can use different R4 and capacitor array capacitance to realize the high pulsewidth of different in width.
The high pulsewidth that 555 timer U2 can export by Schmidt's reverser U4 is anti-phase is low pulsewidth; The signal PS_ON that the output terminal acquiescence of d type flip flop circuit exports is low level, as long as hold to a rising edge of a pulse at its CP, the level of output will reverse.
CON1 is the power input port of Power Integrity proving installation, and CON2 is the output port of power source of Power Integrity proving installation.The metal-oxide-semiconductor Q2 conducting when PS_ON signal is high level, the power supply of power input port flows to output port of power source.When PS_ON signal is low level metal-oxide-semiconductor Q2 by, power input port and output port of power source are isolations.
The logical circuit that linear stabilized power supply LDO U6 is 5V power supply source integrity test device the voltage transitions of input power uses.SW3 is a toggle switch, and effect is when input supply voltage is higher than 5V (conventional has 12V, 19V, 24V, 48V etc.), is connected by the dial-up in 1-4 direction and the disconnection of the dial-up in 2-3 direction, namely uses the voltage conversion function of LDO U6; When input supply voltage equals 5V, the dial-up in 1-4 direction is disconnected and the connection of the dial-up in 2-3 direction, the 5V power supply that the 5V power supply that at this moment apparatus logic circuit uses directly uses equipment input end to access.
As Fig. 6, the waveform of each point (A-H) in circuit in Power Integrity proving installation:
The function of Power Integrity proving installation using method and final realization is as follows:
1, user arranges toggle switch SW3 according to access supply voltage, is connected and the disconnection of the dial-up in 2-3 direction by the dial-up in 1-4 direction when voltage is greater than 5V; When voltage equals 5V, the dial-up in 1-4 direction is disconnected and the connection of the dial-up in 2-3 direction.
2, user arranges capacitor array toggle switch SW2 according to self-demand (how long powering on or lower electricity to Devices to test by needing interval after switch key SW1), 4 switches of toggle switch SW2 are all broken as 4S in this example, 1 closes as 8S, 2 close as 12S, 3 close as 16S, and 4 close as 20S.Certainly this just example, the capacitance that user also can arrange different R4 resistance values and capacitor array according to self-demand in circuit obtains the different time intervals.
3, the power input port CON1 of this equipment is accessed the output port of power source of power supply, by the power input port of the output port of power source of this equipment access Devices to test, namely this equipment is sealed between Devices to test and power supply.
4, the switch key SW1 of this equipment is clicked, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, after the time interval that capacitor array toggle switch is arranged, Devices to test powers on, and at this moment user can test the voltage/signal waveform in power up very easily.
5, the switch key SW1 of this equipment is clicked, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, after the time interval that capacitor array toggle switch is arranged, electricity under equipment to be tested, at this moment user can test the voltage/signal waveform in lower electric process very easily.
The corresponding same or analogous parts of same or analogous label;
Describe in accompanying drawing position relationship for only for exemplary illustration, the restriction to this patent can not be interpreted as;
Obviously, the above embodiment of the present invention is only for example of the present invention is clearly described, and is not the restriction to embodiments of the present invention.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all embodiments.All any amendments done within the spirit and principles in the present invention, equivalent to replace and improvement etc., within the protection domain that all should be included in the claims in the present invention.
Claims (7)
1. a Power Integrity proving installation, be arranged between power input port CON1 and output port of power source CON2, it is characterized in that, comprising: triggered switch circuit, monostalbe trigger, Schmidt's reverser, d type flip flop circuit, NPN type triode and P channel MOS tube Q2;
The input end of the output terminal order steady state trigger of described triggered switch circuit, the output terminal of monostalbe trigger connects the input end of d type flip flop circuit by Schmidt's reverser U4, the output terminal of d type flip flop circuit connects the base stage of triode Q1 by resistance R8, the grounded emitter of triode Q1, the collector of triode Q1 connects the grid of metal-oxide-semiconductor Q2 by resistance R7, the source electrode of metal-oxide-semiconductor Q2 meets power input port CON1, and the drain electrode of metal-oxide-semiconductor Q2 meets output port of power source CON2.
2. Power Integrity proving installation according to claim 1, it is characterized in that, also comprise linear stabilized power supply module, described linear stabilized power supply module comprises toggle switch SW3 and linear stabilized power supply LDO, described power input meets linear stabilized power supply LDO by toggle switch SW3, linear stabilized power supply LDO exports 5V voltage, powers to each electrical part of Power Integrity proving installation.
3. Power Integrity proving installation according to claim 1 and 2, is characterized in that, described triggered switch circuit comprises the interrupteur SW 1, Schmidt's reverser U1 and the Schmidt's reverser U3 that connect in turn.
4. Power Integrity proving installation according to claim 3, it is characterized in that, described monostalbe trigger comprises 555 timer U2 and peripheral circuits, described peripheral circuit comprises capacitor array C, toggle switch SW2 and resistance R4, the TH pin of 555 timer U2 connects 5V power supply by resistance R4, the TH pin of 555 timer U2 connects Dc pin, the positive pole of shunt-wound capacitance array C, and the negative pole of capacitor array C is by toggle switch SW2 ground connection.
5. Power Integrity proving installation according to claim 4, is characterized in that, described d type flip flop circuit comprises two-way D type rising edge flip-flops and peripheral circuit.
6. a Power Integrity method of testing, is characterized in that, comprising:
User arranges the capacitance of capacitor array toggle switch SW2 and the resistance of resistance R4 according to demand to obtain the different time intervals;
The power input port CON1 of Power Integrity proving installation is accessed the output port of power source of power supply, by the power input port of the output port of power source of Power Integrity proving installation access Devices to test, namely this Power Integrity proving installation is sealed between Devices to test and power supply;
Click switch key SW1, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, after the time interval that capacitor array C and toggle switch SW2 is arranged, Devices to test powers on, and user can test the voltage/signal waveform in power up;
Click switch key SW1, user has the sufficient time by oscilloprobe point in the circuit of Devices to test, after the time interval that capacitor array C and toggle switch SW2 is arranged, electricity under equipment to be tested, user can test the voltage/signal waveform in lower electric process.
7. Power Integrity method of testing according to claim 6, it is characterized in that, user arranges toggle switch SW3 according to access supply voltage, arranging toggle switch SW when voltage is greater than 5V makes voltage carry out voltage transitions acquisition 5V voltage by linear stabilized power supply LDO, and powers to each electrical part of Power Integrity proving installation; When voltage equals 5V, toggle switch SW is set, the 5V power supply of direct use equipment input end access.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410614538.1A CN104407305B (en) | 2014-11-03 | 2014-11-03 | A kind of Power Integrity test device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410614538.1A CN104407305B (en) | 2014-11-03 | 2014-11-03 | A kind of Power Integrity test device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104407305A true CN104407305A (en) | 2015-03-11 |
| CN104407305B CN104407305B (en) | 2017-12-26 |
Family
ID=52644950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410614538.1A Expired - Fee Related CN104407305B (en) | 2014-11-03 | 2014-11-03 | A kind of Power Integrity test device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104407305B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106546906A (en) * | 2016-11-01 | 2017-03-29 | 郑州云海信息技术有限公司 | A kind of method and device of Power Integrity test |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201217804A (en) * | 2010-10-19 | 2012-05-01 | Himax Analogic Inc | Dc-to-dc converter having test circuit |
| CN202362411U (en) * | 2011-11-30 | 2012-08-01 | 珠海市华晶微电子有限公司 | Device for testing installing accuracy of speed regulation line |
| CN102749580A (en) * | 2012-07-27 | 2012-10-24 | 苏州贝腾特电子科技有限公司 | Test device |
| CN102749578A (en) * | 2012-07-27 | 2012-10-24 | 苏州贝腾特电子科技有限公司 | Detection device |
-
2014
- 2014-11-03 CN CN201410614538.1A patent/CN104407305B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201217804A (en) * | 2010-10-19 | 2012-05-01 | Himax Analogic Inc | Dc-to-dc converter having test circuit |
| CN202362411U (en) * | 2011-11-30 | 2012-08-01 | 珠海市华晶微电子有限公司 | Device for testing installing accuracy of speed regulation line |
| CN102749580A (en) * | 2012-07-27 | 2012-10-24 | 苏州贝腾特电子科技有限公司 | Test device |
| CN102749578A (en) * | 2012-07-27 | 2012-10-24 | 苏州贝腾特电子科技有限公司 | Detection device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106546906A (en) * | 2016-11-01 | 2017-03-29 | 郑州云海信息技术有限公司 | A kind of method and device of Power Integrity test |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104407305B (en) | 2017-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203859558U (en) | Electronic equipment and external charging circuit thereof | |
| CN205450144U (en) | Test auxiliary circuit discharges | |
| CN108808643B (en) | A kind of analog switching circuit | |
| CN109217425A (en) | A kind of charger circuit and its intelligent charge control method | |
| CN208780742U (en) | A kind of circuit for reducing power-on and power-off and hardware testing being interfered | |
| CN105162196B (en) | A kind of electric vehicle charge control guidance circuit based on transistor | |
| CN104407305A (en) | Power source integrity test device and method | |
| CN205142167U (en) | Time delay outage reset circuit | |
| CN202267725U (en) | Static discharge generator | |
| CN107947123A (en) | ACDC protective circuit of switch power source and ACDC switching power units | |
| CN101902061B (en) | Method for controlling connection and disconnection of charge path of battery, circuit and battery | |
| CN207677707U (en) | A kind of precisely reliable UART communications level shifting circuit | |
| CN109375535A (en) | A kind of enabled circuit unit, sequential control system and method | |
| CN215734057U (en) | ATX power supply control circuit and ATX power supply device | |
| CN104501991A (en) | Remote controller, temperature sampling device and temperature sampling control method | |
| CN209486164U (en) | Microcontroller power supply low-voltage detection circuit without A D interface and internal reference voltage | |
| CN105759929B (en) | Power supply sequence circuit and laptop with the power supply sequence circuit | |
| CN110875607A (en) | Charging system | |
| CN110531818A (en) | Sequential control method and circuit | |
| CN207518565U (en) | A kind of metal-oxide-semiconductor switching circuit | |
| CN207664603U (en) | ACDC protective circuit of switch power source and ACDC switching power units | |
| CN103390994A (en) | Processing circuit providing dummy loads | |
| CN203056565U (en) | Induction cooker surge protection circuit | |
| CN105278405A (en) | Clamshell-type electronic equipment and turning-on/turning-off circuit thereof | |
| CN104635803A (en) | Remote controller and temperature sampling control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Kezhu road high tech Industrial Development Zone, Guangzhou city of Guangdong Province, No. 233 510670 Patentee after: VTRON GROUP Co.,Ltd. Address before: Kezhu road high tech Industrial Development Zone, Guangzhou city of Guangdong Province, No. 233 510670 Patentee before: VTRON TECHNOLOGIES Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171226 Termination date: 20211103 |