CN104393037B - Sub-micron gate length GaN HEMT device and preparation method thereof - Google Patents

Sub-micron gate length GaN HEMT device and preparation method thereof Download PDF

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CN104393037B
CN104393037B CN201410486993.8A CN201410486993A CN104393037B CN 104393037 B CN104393037 B CN 104393037B CN 201410486993 A CN201410486993 A CN 201410486993A CN 104393037 B CN104393037 B CN 104393037B
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grid
gate
metal
gan hemt
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CN104393037A (en
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裴轶
张乃千
邓光敏
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Dynax Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

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Abstract

The invention provides a sub-micron gate length GaN HEMT device and a preparation method thereof. The preparation method involves determining a gate length through optical photoetching and selective etching and then obtaining a deep sub-micron gate foot by use of multiple selective etching of fluorine-based plasma and chlorine-based plasma. The invention simultaneously discloses a device structure obtained by use of the method. The device structure comprises a semiconductor layer, and a gate, a source and a drain which are disposed on the semiconductor layer. The gate comprises a gate cap and the gate foot; and the gate foot is composed of multiple layers of metal, the direction close to the semiconductor layer is taken as a lower direction, and the thickness each layer of the multiple layers of metal is gradually decreased from the top to the bottom. The preparation method has the advantages of simple process, low cost and high efficiency. At the same time, the problems of current collapse and two-dimensional electron gas concentration reduction and the like which are caused by introduction of etching damage when aluminum gallium nitride is etched by the chlorine-based plasma can be prevented.

Description

A kind of Submicron gate length GaN HEMT devices and preparation method thereof
Technical field
The invention belongs to the making field of semiconductor device, more particularly to a kind of high electron mobility based on GaN device The preparation method of transistor (HEMT).
Background technology
HEMT (High Electron Mobility based on AlGaN/GaN materials Transistor, HEMT) in, the electronics in Two-dimensional electron gas channel has very high mobility, thus gallium nitride HEMT relative to For silicon device, switching rate is greatly improved.Simultaneously the two-dimensional electron gas (2DEG) of high concentration also cause gallium nitride HEMT to have Higher electric current density, it is adaptable to the needs of super-current power unit.In addition, gallium nitride is wide bandgap semiconductor, can be operated in Higher temperature.Silicon device generally requires extra cooling device to guarantee its normal work under high power work environment, and Gallium nitride requires cooling relatively low.Therefore gallium nitride power device is conducive to save space and cost.Therefore gallium nitride HEMT device Part has wide application prospect in microwave, power and high-temperature field.
Grid length is the important parameter for affecting device property, including resistance, mutual conductance, frequency characteristic etc..AlGaN/GaN in recent years In the application in microwave power amplifier field, the frequency characteristic in the urgent need to improving device.And can by HEMT device frequency characteristic Know, the shorter device cut-off frequency fT of grid length and maximum concussion frequency fmax are higher.This requires protected in device design and processes It is long that grid are reduced as far as possible in the case of demonstrate,proving a fixed working voltage.Submicron gate typical sizes are 0.5～0.7 μm, and device is operated in C Wave band, typical cut-off frequency fTFor 15～20GHz, list of references " 12W/mm power density AlGaN/GaN HEMTs on sapphire substrate”.It is required that device typical case's cut-off frequency is operated in more than X-band frequency more than 30GHz, i.e. device Section, now, device gate length adopts deep submicron gate.From HEMT device empirical equation (1), device when grid are a length of 0.1～0.5 μm Part cut-off frequency scope 38GHz～190GHz.
fT=νs/(2πL) (1)
The preparation method of the conventional grid of AlGaN/GaN HEMT devices is based on photoetching and metal-stripping.Peel off work Skill technology is divided into single-layer lithography glue lift-off technology and multilevel resist lift-off technology, and multilevel resist lift-off technology must be adopted The photoresist of various light sources, it is difficult to realize using common process and equipment.Single-layer lithography glue stripping technology is referred in substrate surface Last layer photoresist is applied, through front baking, exposure, development mask graph is formed, it is desired to be covered with photoetching the region of metal film is not needed Glue, layer of metal is covered with the method for plated film on its surface, and such metal film only contacts in the region for needing with substrate, finally (stripper does not react with metal level) is soaked in stripper, and with the dissolving of photoresist, metal thereon is also with one Rise and come off, so as to leave required metallic pattern.Or the mode of ultrasound is realized in acetone.Ideally, after stripping only The metal for having contact area is remained, the metal pattern configuration being formed with.In the exposed and developed reality without fully optimization In the operation of border, the material surface for depositing metal is needed often to have remaining one layer of photoresist film being difficult to observe by, this layer thin The presence of film can affect contact good between metal and quasiconductor.Additionally, in stripping process, some needs stay to be formed The metal of contact also can be stripped, and affect the yield rate of product.In the very thin device of grizzly bar, photoetching and metal lift-off material The yield rate of grid is had a significant impact.
At present the minimum feature of AlGaN/GaN HEMT determines by photoetching, conventional means of photolithography mainly have optical lithography, Beamwriter lithography and X-ray lithography technology.
Optical lithography has low cost, technology maturation, the good advantage of exposure effect.But optical lithography is used to expose 0.5 μ The grid line bar of more than m.With the continuous diminution of optical source wavelength used by optical lithography, the raising of photoresist performance, optics phase shift is covered The factors such as use of membrane technology ensure that optical lithography techniques can realize less grid line bar.Alternatively, it is also possible to using oblique The means such as steaming, isotropic etching photoresist are further reducing grid width.But to make less than 0.5 μm using optical lithography techniques The AlGaN/GaN HEMT of the long size of grid, need using phase shift mask technique and some special skills, and technology controlling and process is more multiple Miscellaneous, concordance is not very good.And phase shift optical mask, defect, and defect are often introduced in the manufacturing process of phase shifting layer The requirement of the higher defect mending of generation rate is also high than conventional mask.
Electron-beam direct writing can be used to make deep submicron gate AlGaN/GaN HEMT devices.Electron-beam direct writing method makes Deep submicron gate will typically adopt multilamellar adhesive process.Its advantage is that the live width of grid bottom can reach nanometer level, and concordance Can be made very well.But electron-beam direct writing makes deep submicron gate has efficiency very low, and high cost, is typically only applicable to Laboratory research.From 0.25 μm to 0.18 μm, e-beam direct-writing exposure mode production efficiency declines 50% to live width；Live width is from 0.18 μm to 0.13 μm, production efficiency declines 66%；To less than 0.13 μm, efficiency declines at double.And electron-beam direct writing equipment is very Costliness, cost of equipment maintenance is high.
X-ray lithography can obtain less live width, meet the process technology of 0.05～0.25 μ m in size；One electric light source X-ray lithography engine efficiency is more than 7 electron beam writers.It is X-ray source problem using the greatest problem of X-ray lithography, skill Art is not mature enough and the shortcomings of apparatus expensive.
Therefore, find a kind of process is simple, efficiency high is with low cost, high yield rate to prepare deep submicron gate long AlGaN/GaN HEMT device methods, become the industry in the urgent need to.
The content of the invention
In view of this, it is an object of the invention to overcome the above to make submicron gate photoetching and stripping in GaN HEMT devices A kind of deficiency of separating process, there is provided preparation method of Submicron gate length GaN HEMT devices.The method solves current GaN HEMT Grid photoetching process is complicated, and efficiency is low, and yield rate is low, the problem of apparatus expensive, inexpensive to meet submicron gate GaN HEMT, high Efficiency, the gate electrode processing technology of high finished product rate is required.
A kind of Submicron gate length GaN HEMT device preparation methoies that purpose of the invention is proposed, its core concept is Determine that grid are long by photoetching and etching, then deep-submicron is obtained using fluorine-based plasma and chlorine based plasma multiple etching Grid foot.Specifically, Submicron gate length GaN HEMT device preparation methoies, including semiconductor epitaxial process, gate electrode making work Skill and source, drain electrode processing technology, the semiconductor epitaxial process grows the quasiconductor of the GaN HEMT devices on substrate Layer, wherein the gate electrode processing technology includes step：
1) gate metal layer is made on the semiconductor layer；
2) sacrifice layer is made in the gate metal layer；
3) photoetching is carried out on the sacrifice layer, the photoresist mask with gate patterns is made；
4) etch for the first time, the gate patterns in photoresist mask are transferred on the sacrifice layer；
5) live width of the gate patterns being transferred on the sacrifice layer is reduced, the live width for making the gate patterns reaches sub-micro Meter level；
6) etch for second, replaced using fluorine-based plasma or chlorine based plasma etching or above two plasma Etching, by the step 5) after sacrifice layer on gate patterns be transferred in the gate metal layer, form grid pure golds category.
Preferably, the grid foot metal level is made up of multiple layer metal, wherein, as lower direction, being somebody's turn to do near the semiconductor layer Each layer of thickness successively decreases from top to bottom in multiple layer metal.
Preferably, following steps are increased after 6) step is etched for second described the：
7) deposit passivation layer, polishes passivation layer surface；
8) the grid cover metal being connected with grid pure gold category is formed on the passivation layer, obtains including the grid of grid foot and grid cover Pole.
Preferably, the grid is shaped as T-shaped, Г shapes or trapezoidal.
Preferably, the multiple layer metal is that one layer of Al, one layer of TiW are alternately formed or only one layer Al and into periodicity Layer TiW.
Preferably, the method for reducing the live width of the gate patterns being transferred on the sacrifice layer is wet etching and/or does Method is etched.
Preferably, the sacrifice layer is SiNx, SiO2, one or more in SiON, PSG, TiW, Cr, AlN, it is described sacrificial It can also be multilamellar that domestic animal layer can be one layer.
Preferably, first can make one layer of insulating medium layer on the semiconductor layer before gate metal layer is made to be formed MIS grid structures, the insulating medium layer is AlN, SiN, SiO2Or Al2O3In one or more.
Preferably, the order in the source, drain electrode processing technology and the gate fabrication process can successively each other.
Meanwhile, present invention also proposes Submicron gate length GaN HEMT devices prepared by a kind of use said method, including Semiconductor layer and the grid on semiconductor layer, source electrode and drain electrode, the grid includes grid, and enough the grid foot is golden by multilamellar Category composition, wherein so that, as lower direction, each layer of thickness successively decreases from top to bottom in the multiple layer metal near the semiconductor layer.
Preferably, the grid further includes grid cover, and the grid cover exposes over the passivation layer, and connects enough with the grid Touch.
Preferably, the multiple layer metal is that one layer of Al, one layer of TiW are alternately formed or only one layer Al and into periodicity Layer TiW.
Preferably, the grid are sufficient is additionally provided with one layer of insulating medium layer and the semiconductor layer between, the insulating medium layer with The grid foot, the semiconductor layer form together MIS grid structures, and the dielectric layer is AlN, SiN, SiO2Or Al2O3In one Kind.
Compared with prior art, it is an advantage of the current invention that：
First：The method passes through secondarily etched, and adds an isotropic etching middle, is obtained 0.1～0.5 μm Grid foot under size, compared with e-beam direct write lithography, using the equipment of optical lithography process costs is significantly reduced, and is imitated Rate is high；Compared with X-ray lithography method, have the advantages that technology maturation equipment is cheap；Compared with ordinary optical photoetching, grid size It is less, and concordance is good, it is to avoid introduce defect.
Second：Using the etching of multiple layer metal grid structure precise control grid material, it is to avoid the infringement to epitaxial material.
3rd：Increase SiN layer on AlGaN/GaN epitaxial materials to avoid etching epitaxial material.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of process flow diagram of the preparation method of GaN HEMT devices proposed by the invention.
Fig. 2A～Fig. 2 J are GaN HEMT devices preparation technology schematic flow sheet of the present invention.
Fig. 3 structural representations of grid preparation method embodiment two proposed by the invention.
Fig. 4 structural representations of grid preparation method embodiment three proposed by the invention.
Fig. 5 grid preparation method example IV structural representations proposed by the invention.
Specific embodiment
As described in background, in existing AlGaN/GaN HEMT devices preparation method, metal-stripping has finished product The low shortcoming of rate.Prepared by deep submicron gate length, in existing photoetching process, common optical lithography can only achieve 0.5 μm of level Not, although and e-beam direct write lithography technique and X-ray lithography technique can etch less line width values, the two works Or skill apparatus expensive, or inefficiency, it is difficult to meet the manufacture demand of extensive AlGaN/GaN HEMT devices.
Therefore, the present invention proposes one kind and can solve the problem that in above-mentioned gate lithography technique, complex process, inefficiency, into This height, the AlGaN/GaN HEMT device preparation methoies of the low problem of yield rate, the present invention technical thought be：In gate electrode system In making technique, first gate figure is transferred on sacrifice layer using optical lithography and subsequent etching, then is carved with wet etching or dry method Erosion sacrifice layer reduces live width, makes sacrifice layer live width be decreased to 0.1 μm by control corrosion rate time and speed.Then it is with sacrifice layer Mask, using fluorine-based plasma and chlorine based plasma the grid foot that subsequent etching obtains 0.1 μm is carried out.Using dielectric layer or Multiple layer metal, weakens grid preparation and AlGaN material is caused to etch and introducing surface damage.Or multiple layer metal is adopted with precise control Etch thicknesses.
Below, the technical scheme of this case will be elaborated by specific embodiment.
[embodiment one]
Fig. 1 and Fig. 2A -2J are refer to, the AlGaN/GaN HEMT devices preparation method of the present invention includes following several steps Suddenly：
Step S1, semiconductor layer epitaxy technique.
The step mainly grows required semi-conducting material by modes such as thin film deposition processes on substrate on substrate, For the making of subsequent device, in the present invention, the semi-conducting material is primarily referred to as AlGaN/GaN.Specifically, with reference to Fig. 2A institutes Show, first intrinsic GaN layer 3 is grown on the substrate 1 using MOCVD techniques, in intrinsic GaN layer 3, grow AlGaN layer 4.And AlGaN Two-dimensional electron gas (2DEG) are formed between layer 4 and GaN layer 3.Wherein, the material of substrate 1 can be sapphire (Sapphire), The material of SiC, Si or any other suitable growing gallium nitride well known to those skilled in the art.The deposition process of substrate 1 Including CVD, VPE, MOCVD, LPCVD, PECVD, pulsed laser deposition (PLD), atomic layer epitaxy, MBE, sputtering, evaporation etc..This Outward, one layer of nucleating layer 2 can also be grown between substrate 1 and GaN layer 3.One layer of dielectric layer 7, Jie are grown in AlGaN layer 4 The preferred SiN of matter layer, also optional SiO2, AlN or Al2O3Deng.Preferred original position single electron deposition (ALD) of its growing method, it is also possible to adopt With additive method such as CVD, LPCVD, PECVD, sputtering, evaporation etc..It is preferred that the dielectric layer of original position ALD growths advantageously reduces electric current Avalanche.The dielectric layer 7 can form metal-insulator-semiconductor layer (Metal- together with follow-up gate metal Insulator-Semiconductor；MIS structure), simultaneously because the addition of the dielectric layer so that follow-up in etching grid During metal, the semiconductor epitaxial material that can protect lower section is not damaged.
Step S2, gate electrode make.
The step is the substrate surface in the complete semi-conducting material of above-mentioned making, it is also possible in the circle for having made source electrode and drain electrode Piece surface is made, and carries out the making of grid.First carry out source-drain electrode and prepare the high temperature pair that can be avoided in source-drain electrode preparation process The preparation of grid is impacted.The preparation of gate electrode is the emphasis of the present invention, and relative to prior art, the present invention is by the grid The united application of particular technique means in the processing technology of pole, reaches the technique level of deep-submicron rank (less than 0.5 μm), and Whole technique has simple efficient, with low cost advantage.Prepared using fluorine-based plasma and chlorine based plasma etching deep Submicron gate foot, it is to avoid the low problem of deep sub-micron dimensions metal-stripping yield rate.Simultaneously using multiple layer metal or in grid structure Upper employing dielectric layer, can weaken grid preparation and AlGaN material is caused to etch and introducing surface damage.Specifically, the grid system Making technique includes following several steps：
S21, on the semiconductor layer made make gate metal layer.Specifically, steam in above-mentioned AlGaN layer 4 Layer of metal layer 8 is sent out or sputters, the metal level 8 selects chlorine based plasma energy as follow-up grid foot metal level, the embodiment Etching and metal that fluorine-based plasma can not be etched are used as grid material.It is preferred that Al, optional Cr/Al, or other chloro plasmas The metal that body can be etched.Requirement to the gate metal layer is on the one hand need to consider its matching with AlGaN/GaN materials, On the other hand, in the follow-up etching technics of the present invention, need to consider the gas between the metal level and upper and lower material to etching The reactable of body or liquid.Guarantee when etching the metal level or etching the material layer of the upper and lower both sides of the metal level, will not shape Into interference corrosion, it is ensured that the accuracy of etching.
S22, in above-mentioned gate metal layer 8 make sacrifice layer 9.Specifically, SiO can be deposited on Al2, SiNx, A kind of sacrifice layer 9 as subsequent etching in SiON, PSG, TiW.Structure is as shown in Figure 2 B.
S23, photoetching is carried out on above-mentioned sacrifice layer 9, make the photoresist mask with gate patterns.Specifically：Sacrificial Resist coating 10 on domestic animal layer 9, is exposed and develops to the photoresist 10, and as shown in FIG. 2 C, wherein mask 11 is optics light The outer mask arrived used in quarter, the figure with grid part on the mask 11, after exposure, the figure on mask 11 turns Move on to photoresist 10.
Gate patterns on photoresist mask after step S23 are transferred to the sacrifice layer 9 by S24, for the first time etching On.ICP dry etchings, wherein SiO can be adopted2, the etching gas of SiNx, SiON, PSG, TiW be containing fluoro plasma, it is optional SF6、CF4.Obtain structure as shown in Figure 2 D.
S25 and then, diminution is transferred to the live width of gate patterns on the sacrifice layer, makes the live width of the gate patterns Reach submicron order.The step can be carried out using wet method or dry etching.(1) when using wet etching, retain photoresist, adopt Buffered HF is corroded, to reduce live width.Obtain structure as shown in Figure 2 E.Then photoresist is removed, structure such as Fig. 2 F institutes are obtained Show.(2) can also remove after photoresist, strengthen dry etching using fluorine-based plasma low energy electrons, using its horizontal quarter Erosion, reduces live width, obtains structure as shown in Figure 2 F.During using dry etching, the thickness of sacrifice layer 9 is much larger than its lateral etching Width.By controlling etching speed and time to reduce live width.Live width being reduced using lateral etching, there is low cost, process is simple Advantage.
S26, second etching, etching removes excess gate metal 8 after step S25, using fluorine-based plasma or chlorine Base plasma etching or above two plasma are alternately etched, and the figure on sacrifice layer after S25 9 is transferred to into grid gold On category 8, grid pure gold category is formed.Its structural representation such as Fig. 2 G.The etching gas of gate metal Al are respectively BCl3/Cl2.Can shape It it is 0.1～0.5 μm into the long scope of grid.Due to gate metal layer it is thicker, to avoid causing the etching of AlGaN layer 4 during over etching, Increase by one layer of dielectric layer 7, the preferred SiN of dielectric layer 7 in AlGaN layer 4.Chlorine based plasma cannot etch SiN, and SiN layer is to AlGaN There is protective effect to reduce etching injury on surface.
After above-mentioned several steps, grid pure gold category is made, certainly for the device in practical application Speech, after grid foot is obtained, preferably along with following two steps realize the making of whole grid：
S27, after step S26 deposit one layer of passivation layer 12, the passivation material can be SiN, AlN or Al2O3Or industry Interior known other passivating materials.The passivation layer thickness is more than grid foot height.Then surface is chemically-mechanicapolish polished, institute's shape Into structure as illustrated in figure 2h.
S28, grid cover metal is deposited after step S27 and etched, form grid cover structure, form structure such as Fig. 2 I institutes Show.Ultimately form grid structure can be T-shaped grid can also be Г type grid, the structure such as trapezoidal grid.
Available 0.1～0.5 μm metal gate of the method, compared with e-beam direct write lithography, setting using optical lithography It is standby to significantly reduce process costs, and efficiency high；Compared with X-ray lithography method, with cheap excellent of technology maturation equipment Point；Compared with ordinary optical photoetching, grid are smaller, and concordance is good, it is to avoid introduce defect.
Step 3, source-drain electrode make
As shown in fig. 2j, source electrode 5 and drain electrode 6 and the 2DEG in AlGaN/GaN formed the modes that electrically connect can using but It is not limited in the following manner to be formed：A. high annealing；B. ion implanting；C. heavy doping.In the case where high annealing is carried out, source The electrode metal of pole 5 and drain electrode 6 is contacted through AlGAN layers with GaN, is electrically connected so as to be formed with 2DEG.Carrying out ion implanting In the case of heavily doped, source electrode 5 and drain electrode 6 are by forming the ion implanting part or heavily doped hetero moiety and its that electrically connect with 2DEG On electrode constitute.It should be understood that the source electrode 5 and the method for drain electrode 6 of being formed described herein is to be illustrated, the present invention can lead to Cross any method well known to those skilled in the art and form source electrode 5 and drain electrode 6.
[embodiment two]
Fig. 3 shows according to another embodiment of the invention.
Here omits the description of embodiment two and the same section of embodiment one, describes both differences emphatically below. Embodiment two is that the grid pure gold of embodiment two belongs to 308 for TiW, and dielectric layer 307 is AlN, Al with the difference of embodiment one2O3Or Its combination, sacrifice layer 309 is two-layer, and from top to bottom ground floor is SiO2, the second layer is Cr or AlN.In S25 steps, second Etching, etches ground floor sacrifice layer SiO initially with chlorine based plasma2On figure be transferred to second layer sacrifice layer Cr or On AlN.Then TiW is belonged to using fluorine-based plasma etching grid pure gold, now mask layer is Cr or AlN.Etching grid pure gold category is same Moment etching off removes ground floor sacrifice layer SiO2.Dielectric layer 307 is AlN, and the etching gas of AlN materials are Cl2, therefore under it Epitaxial material is protected.Defect and the surface state caused by etching injury is avoided, and then reduces current collapse.Grid pure gold category is carved Structure is formed after having lost as shown in Figure 3.Compared with embodiment one, gate metal TiW has heat stability good to embodiment two, resists The advantage of irradiation.High-temperature technology such as ohm annealing, high temperature epitaxy material can be born using the good TiW metal-gate structures of heat stability Material regrowth, injection after annealing etc..Gate metal heat stability avoids well schottky metal and quasiconductor circle under hot conditionss The degeneration of face characteristic has more preferable reliability.
[embodiment three]
Fig. 4 shows according to another embodiment of the invention.Here omits embodiment three and the same section of embodiment one Description, emphatically both differences of description below.Embodiment three is with the difference of embodiment one, the grid in embodiment three Pole metal 8 is the combination of Al and TiW.Ground floor gate metal 4081 is Al, or other metals that chlorine based plasma can be etched Material.Second layer gate metal 4082 is other metal materials that TiW or fluorine-based plasma can be etched.Dielectric layer 407 is AlN, Al2O3 or its combination.Wherein, the thickness of ground floor gate metal 4081 is significantly greater than the thickness of second layer gate metal 4082 Degree.Initially with the gate metal material of the thickness of chloro plasma etching first when should etch for second.Then using fluorine-based etc. The thin gate metal material of the plasma etching second layer.Optionally, ground floor gate metal be 550nm, second layer gate metal For 25nm.Second layer gate metal 4082 is the etching stop layer of ground floor gate metal 4081, it is to avoid chlorine based plasma energy Etching AlGaN material.Second layer metal etachable material is fluorine-based plasma, and fluorine-based plasma does not etch AlGaN material, but It is the fluorine-based change for being injected in AlGaN and causing 2DEG concentration.Now need the thickness for optimizing second layer metal material, purpose It is that thickness can stop that chlorine based plasma etches AlGaN material, and not introduce excessive fluorine-based plasma.Due to the second layer Metal thickness is 1/10th of first layer metal thickness, and the etch period of second layer metal is much smaller than first layer metal, also Mean that the action time of fluorine-based plasma is shorter, so as to farthest reduce infringement of second etching to AlGaN.Cause This embodiment three is compared with embodiment one, it is to avoid etching of the chlorine based plasma to AlGaN material.
[example IV]
Fig. 5 shows according to another embodiment of the invention.
Here omits the description of example IV and the same section of embodiment one, describes both differences emphatically below. Example IV is that the gate metal in example IV is that Al, Cr or chlorine based plasma can be etched with the difference of embodiment one Metal material and the multiple layer metal of metal material periodic arrangement composition that can etch of TiW or fluorine-based plasma, and it is more Each layer of thickness, as lower direction, successively decreases from top to bottom near the semiconductor layer in layer metal.Optionally, it is with four layers Example, first layer metal is 500nm, and second layer metal is 50nm, and third layer metal is 5nm, and the 4th layer of metal is 0.5nm etc..Fig. 5 Shown gate metal 5081 is Al, gate metal 5082 is TiW.It can also be even number that total number of metal can be odd number.Its Preparation method is that grid pure gold category needs multiple fluorine-based plasma and chlorine based plasma to enter respectively with the difference of embodiment one Row etching, such as first layer metal are etched using chlorine based plasma, and second layer metal is etched using fluorine-based plasma, third layer Metal is etched using chlorine based plasma, and the 4th layer of metal is etched using fluorine-based plasma, etc..Because metal layer thickness is passed Subtract, every layer of metal can be controlled in the quarter of fluorine-based plasma and chlorine based plasma to different materials with adjacent metal thickness difference Erosion is selected in the range of ratio.Therefore, etch negligible to the etching of lower metal during the metal of upper strata.Additionally, using multiple layer metal energy Etching depth is better controled over, concordance is more preferable.Additionally, last layer of grid pure gold belongs to, and material thickness is very thin, etch period is non- It is often short, therefore AlGaN material is not affected.Schottky gate can be prepared using the method.Schottky gate parasitic capacitance is little, Device frequency characteristic is good, therefore can be used to prepare high frequency gallium nitride microwave device.
Meanwhile, as an improvement of the present invention, with the Submicron gate length that the method for embodiment three or four is prepared AlGaN/GaN HEMT devices, it has and the different grid of existing device, and specifically, the grid only has grid foot or including grid Cap and grid foot, grid cover exposes over the passivation layer, and contacts enough with grid.Grid are made up of enough multiple layer metal, and the multiple layer metal is one layer Al, one layer of TiW are alternately formed or only one layer Al and one layer of TiW into periodicity, wherein under to be near the semiconductor layer Direction, each layer of thickness successively decreases from top to bottom in the multiple layer metal.
Further, one layer of insulating medium layer, the insulating medium layer and grid can be also set between grid foot and semiconductor layer Foot, semiconductor layer form together MIS grid structures.The insulating medium layer is AlN, SiN, SiO2Or Al2O3In one or more.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention. Various modifications to these embodiments will be apparent for those skilled in the art, as defined herein General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, the present invention Embodiment illustrated herein is not intended to be limited to, and is to fit to consistent with principles disclosed herein and features of novelty Most wide scope.

Claims (12)

1. a kind of Submicron gate length GaN HEMT device preparation methoies, including semiconductor epitaxial process, gate fabrication process and source, Drain electrode processing technology, the semiconductor epitaxial process is the semiconductor layer that the GaN HEMT devices are grown on substrate, its It is characterised by：The gate fabrication process includes step：
1) gate metal layer is made on the semiconductor layer；
2) sacrifice layer is made in the gate metal layer；
3) photoetching is carried out on the sacrifice layer, the photoresist mask with gate patterns is made；
4) etch for the first time, the gate patterns in photoresist mask are transferred on the sacrifice layer；
5) live width of the gate patterns being transferred on the sacrifice layer is reduced, the live width for making the gate patterns reaches submicron Level；
6) etch for second, alternately etched using fluorine-based plasma and chlorine based plasma etching, by the step 5) after Sacrifice layer on gate patterns be transferred in the gate metal layer, form grid pure golds category；
Wherein, the gate metal layer is the metal material that chlorine based plasma can be etched and the gold that fluorine-based plasma can be etched The multiple layer metal that category material periodicities are rearranged, and each layer of thickness is with the close semiconductor layer in its multiple layer metal Lower direction, successively decreases from top to bottom.
2. a kind of Submicron gate length GaN HEMT device preparation methoies as claimed in claim 1, it is characterised in that：Described 6) step increases following steps after etching for second：
7) deposit passivation layer, polishes passivation layer surface；
8) the grid cover metal being connected with grid pure gold category is formed on the passivation layer, obtains including the grid of grid foot and grid cover.
3. a kind of Submicron gate length GaN HEMT device preparation methoies as claimed in claim 2, it is characterised in that：The grid Be shaped as T-shaped, Г shapes or trapezoidal.
4. a kind of Submicron gate length GaN HEMT device preparation methoies as claimed in claim 1, it is characterised in that：The multilamellar Metal is that one layer of Al, one layer of TiW are alternately formed or only one layer Al and one layer of TiW into periodicity.
5. a kind of Submicron gate length GaN HEMT device preparation methoies as claimed in claim 1, it is characterised in that：Reduce transfer The method of the live width of the gate patterns on the sacrifice layer is wet etching and/or dry etching.
6. a kind of Submicron gate length GaN HEMT device preparation methoies as claimed in claim 1, it is characterised in that：The sacrifice Layer is SiNx, SiO2, one or more in SiON, PSG, TiW, Cr, AlN, the sacrifice layer can be one layer can also be Multilamellar.
7. a kind of Submicron gate length GaN HEMT device preparation methoies as claimed in claim 1, it is characterised in that：Can make First one layer of insulating medium layer is made before gate metal layer on the semiconductor layer form MIS grid structures, the insulating medium layer For AlN, SiN, SiO2Or Al2O3In one or more.
8. a kind of Submicron gate length GaN HEMT device preparation methoies as claimed in claim 1, it is characterised in that：The source, The order of drain electrode processing technology and the gate fabrication process can successively each other.
9. a kind of usage right requires Submicron gate length GaN HEMT devices prepared by the method described in 1-8 any one, including Semiconductor layer and the grid on semiconductor layer, source electrode and drain electrode, it is characterised in that：The grid includes the grid grid enough Foot is made up of multiple layer metal, wherein so that near the semiconductor layer, as lower direction, each layer of thickness is by upper in the multiple layer metal Down successively decrease.
10. Submicron gate length GaN HEMT devices as claimed in claim 9, it is characterised in that：The grid is further included Grid cover, the grid cover exposes over the passivation layer, and contacts enough with the grid.
11. Submicron gate length GaN HEMT devices as claimed in claim 9, it is characterised in that：The multiple layer metal is one layer Al, one layer of TiW are alternately formed or only one layer Al and one layer of TiW into periodicity.
12. Submicron gate length GaN HEMT devices as claimed in claim 9, it is characterised in that：The grid are partly led enough with described One layer of insulating medium layer is additionally provided between body layer, the insulating medium layer forms MIS together with grid foot, the semiconductor layer Grid structure, the dielectric layer is AlN, SiN, SiO2Or Al2O3In one kind.
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CN108172511B (en) * 2017-12-27 2020-11-24 成都海威华芯科技有限公司 Manufacturing method of T-shaped grid with air channel structure
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