CN109560118A - The face T grid N GaN/AlGaN fin high electron mobility transistor - Google Patents

The face T grid N GaN/AlGaN fin high electron mobility transistor Download PDF

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CN109560118A
CN109560118A CN201710885208.XA CN201710885208A CN109560118A CN 109560118 A CN109560118 A CN 109560118A CN 201710885208 A CN201710885208 A CN 201710885208A CN 109560118 A CN109560118 A CN 109560118A
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algan
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刘梅
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Nanjing Yu Kai Electronic Technology Co Ltd
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Nanjing Yu Kai Electronic Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention discloses a kind of face T grid N GaN/AlGaN fin high electron mobility transistor.The maximum frequency of oscillation for mainly solving existing microwave power device is small, and ohmic contact resistance is big, the serious problem of short-channel effect.It includes: substrate (1), GaN buffer layer (2), AlGaN potential barrier (3), GaN channel layer (4), gate dielectric layer (5), passivation layer (6) and source, leakage, gate electrode from bottom to top.Wherein buffer layer and channel layer use the face N GaN material；GaN channel layer and AlGaN potential barrier form GaN/AlGaN hetero-junctions；Gate electrode uses T-type grid, and is wrapped in the two sides and top of GaN/AlGaN hetero-junctions, forms 3 D stereo grid structure.Device of the present invention has grid-control ability good, and the advantage that ohmic contact resistance is small and maximum frequency of oscillation is high can be used as the microwave power device of small size.

Description

The face T grid N GaN/AlGaN fin high electron mobility transistor
Technical field
The invention belongs to technical field of microelectronic devices, the specifically a kind of high electronics of the face T grid N GaN/AlGaN fin Mobility transistor Fin-HEMT can be used for microwave power integrated circuit.
Background technique
GaN material is as third generation semiconductor material, since forbidden bandwidth is big, two-dimensional electron gas 2DEG concentration is high and electronics The advantages that saturated velocity is high, it is considered to be the excellent material of production microwave power device and high speed device.Especially AlGaN/GaN Hetero-junctions high electron mobility transistor (HEMT), is widely used in microwave power circuit.
With the diminution of transistor size, grid length is shorter and shorter, the short channel of traditional high electron mobility transistor (HEMT) Effect is more and more obvious.Common I type grid, parasitic capacitance and dead resistance are larger, influence high electron mobility transistor Ac small signal characteristic and power characteristic.It is moved with the AlGaN/GaN high electronics that fin formula field effect transistor FinFET structure makes Shifting rate transistor HEMT device wraps up grid channel from three directions, is improved grid-control using three-dimensional structure Ability improves short-channel effect.2014, S.Arulkumaran of Nanyang Technolohy University et al. made on a silicon substrate for the first time For InAlN/GaNFin-HEMT has been gone out, this structure has lower drain induced barrier to reduce, higher switching current ratio, referring to In0.17Al0.83N/AlN/GaNTripleT-shapeFin-HEMTswithgm=646mS/mm, ION=1.03A/mm, IOFF= 1.13 μ A/mm, SS=82mV/decandDIBL=28mV/VatVD=0.5V, IEEE, InternationalElectronDeviceMeeting(IEDM),2014:25.6.1-25.6.4.The device is using Ga Face GaN base structure, compared to the face N GaN base device, the face Ga GaN base device has higher ohmic contact resistance, poor two dimension electricity Sub- gas confinement, it is also weaker to the rejection ability of short-channel effect.
Summary of the invention
It is an object of the invention to be directed to the deficiency of above-mentioned high electron mobility transistor (HEMT) device, a kind of T grid N is proposed Face GaN/AlGaN fin high electron mobility transistor and production method reduce Ohmic contact electricity to inhibit short-channel effect Resistance improves maximum oscillation frequency.
To achieve the above object, the face T grid N GaN/AlGaN fin high electron mobility transistor of the invention, from bottom to top Including substrate 1, GaN buffer layer 2, AlGaN potential barrier 3, GaN channel layer 4, gate dielectric layer 5, passivation layer 6 and source, leakage, gate electrode, It is characterized by:
GaN buffer layer and channel layer are all made of the face N GaN；
Gate electrode uses T-type grid and is wrapped in the two sides and top of GaN/AlGaN hetero-junctions, forms 3 D stereo grid structure.
According to above-mentioned technical thought, the present invention makes the side of the face T grid N GaN/AlGaN fin high electron mobility transistor Method includes the following steps:
1) on the face C SiC, a surface sapphire or the face N GaN single crystal substrate, molecular beam epitaxy MBE or metallo-organic compound are utilized Chemical vapor deposition MOCVD grows 1.5~3 μm of the face N GaN buffer layer；
2) AlGaN of 20nm thickness is first grown on GaN buffer layer, Al component is gradient to 30% from 5%；Regrowth is with a thickness of 5 The AlGaN of~10nm, Al group are divided into 30%；
3) face the N GaN channel layer that growth thickness is 20~30nm in AlGaN potential barrier；
4) by etching GaN channel layer, the marginal portion of AlGaN potential barrier and GaN buffer layer, it is different to form fin GaN/AlGaN Matter knot；
5) source, drain electrode are made at the both ends of GaN channel layer upper surface；
6) using atomic layer deposition ALD or plasma enhanced CVD PECVD technique in AlGaN potential barrier and GaN Channel layer surface grows gate dielectric layer；
7) on gate dielectric layer photoetching T-type grid grid shape, and deposited by electron beam evaporation prepares gate electrode；
8) passivation layer is deposited using plasma enhanced CVD PECVD in SiN and electrode surface, etches away electrode key Extra passivation layer in chalaza, row metal of going forward side by side interconnection evaporation, completes the preparation of device.
The present invention has the advantage that
1. device of the present invention is due to using the face N GaN material, so ohmic contact resistance is smaller, there is good two-dimensional electron gas to limit Domain property, and because of barrier layer below channel layer, it is possible to grid are flexibly reduced at a distance from channel.
2. device of the present invention can be very good to inhibit short-channel effect, reinforce grid-control energy due to using fin Fin grid structure Power.
3. device of the present invention can be improved the maximum frequency of oscillation of device, improve the micro- of device due to using T-type gate electrode Wave performance.
Detailed description of the invention
Fig. 1 is device architecture schematic diagram of the present invention；
Fig. 2 is the cross-sectional view of horizontal direction a in Fig. 1；
Fig. 3 is the cross-sectional view of vertical direction b in Fig. 1；
Fig. 4 is the fabrication processing schematic diagram of device of the present invention.
Specific embodiment
Below in conjunction with attached drawing, present invention is further described in detail.
Referring to FIG. 1, FIG. 2 and FIG. 3, device of the present invention includes substrate 1, GaN buffer layer 2, AlGaN potential barrier 3, GaN channel Layer 4, gate dielectric layer 5, SiN passivation layer 6 and grid, source, drain electrode.Wherein substrate 1 uses SiC or GaN or sapphire；The face N GaN is slow It rushes layer 2 to be located on substrate 1, thickness is 1.5~3 μm；AlGaN potential barrier 3 is located on the face N GaN buffer layer 2, the potential barrier Layer 3 is made of two layers of AlGaN, and wherein the thickness of first layer AlGaN is 20nm, and Al component is gradient to 30% from 5%, the second layer The thickness of AlGaN is 5~10nm, and Al group is divided into 30%；The face N GaN channel layer 4 is located at the upper surface of AlGaN potential barrier 3, thickness It is 20~30nm；The width of AlGaN potential barrier 3 and GaN channel layer 4 is 2~5 μm；GaN channel layer 4 and AlGaN potential barrier 3 Form GaN/AlGaN hetero-junctions；Gate dielectric layer 5 is located at around channel layer 4 and the two sides of barrier layer 3, which uses SiN or Al2O3, thickness is 5~10nm；Gate electrode is located at the two sides and top of gate dielectric layer 5, which uses T junction Structure is made of grid neck and grid cover, and the height of grid neck is 40~90nm, and the length of grid neck is 200~500nm, the height of grid cover For 100~300nm, the length of grid cover is 300~600nm；Source electrode is located at the left end of 4 upper surface of channel layer, and drain electrode is located at The right end of 4 upper surface of channel layer；Passivation layer 6 be covered on source, leakage, gate electrode and gate dielectric layer 5 surface, the passivation layer 6 use SiN, with a thickness of 50~100nm.
Referring to Fig. 4, the present invention, which provides, prepares following three kinds of the face T grid N GaN/AlGaN fin high electron mobility transistor Embodiment.
Embodiment 1: production fin GaN/AlGaN hetero-junctions width is 2 μm, and the grid neck height of T-type grid is 50nm, and grid cover is high Degree is the face the T grid N GaN/AlGaN fin high electron mobility transistor of 100nm.
Step 1: grown buffer layer.
It is 680 DEG C in temperature, pressure is 5 × 10-3Under the process conditions of Pa, using molecular beam epitaxy MBE equipment in Fig. 4 (a) face the N GaN buffer layer that Grown on Sapphire Substrates a layer thickness shown in is 1.5 μm.
Step 2: growth barrier layer.
It is 680 DEG C in temperature, pressure is 5 × 10-3Under the process conditions of Pa, using molecular beam epitaxy MBE equipment in GaN layer The AlGaN that upper first growth a layer thickness is 20nm, Al component are gradient to 30% by 5% from top to bottom；Regrowth a layer thickness is 10nm, Al group are divided into 30% AlGaN layer.
Step 3: growth channel layer.
It is 680 DEG C in temperature, pressure is 5 × 10-3Under the process conditions of Pa, using molecular beam epitaxy MBE equipment in AlGaN The face the N GaN channel layer that a layer thickness is 20nm is grown on layer, GaN channel layer and AlGaN potential barrier formation GaN/AlGaN are heterogeneous It ties, forms two-dimensional electron gas at GaN/AlGaN heterojunction boundary.
The growth result of above-mentioned steps one, step 2 and step 3 such as Fig. 4 (b).
Step 4: etching fin GaN/AlGaN hetero-junctions.
The resist coating in GaN layer is exposed using electron beam lithography machine, obtains fin Fin pattern, recycles Cl2 It performs etching, the fin GaN/AlGaN hetero-junctions that formation width is 2 μm, as a result such as Fig. 4 (c).
Step 5: production source, drain electrode.
Gluing obtains photoresist mask on GaN channel layer, exposes the source of being formed, drain region using electron beam lithography machine, and Evaporation of metal is carried out, Ti/Au is selected to do source, drain electrode, wherein Ti is 5nm, Au 20nm, and laggard row metal stripping is completed in evaporation From；Recycle rapid thermal anneler in N2It is made annealing treatment in atmosphere, obtains source, drain electrode, as a result such as Fig. 4 (d).
Step 6: production gate dielectric layer.
The SiN of one layer of 55nm thickness is grown on GaN channel layer using plasma enhanced CVD PECVD, so Gluing afterwards is lithographically derived gate figure；Use SF6The SiN for etching away gate region 50nm thickness forms grid slot, the SiN conduct of remaining 5nm thickness Gate dielectric layer makes result such as Fig. 4 (e).
Step 7: production grid.
Electron beam lithography machine photoetching T-type grid shape is used in grid groove location, evaporation of metal is then carried out, Ti/Au is selected to do Gate electrode, wherein Ti is 50nm, and then Au 100nm carries out metal-stripping, ultimately forms T-type grid metal electrode, T-type grid Grid neck height is 50nm, and grid neck length degree is 200nm, and the height of grid cover is 100nm, and the length of grid cover is 300nm.
Step 8: production passivation layer.
It is blunt for the SiN of 50nm in SiN and electrode surface deposition thickness using plasma enhanced CVD PECVD Change layer；Then expose interconnection window in bonding point photoetching, use Cl2SiN passivation layer extra at interconnection window is etched away, is gone forward side by side Row metal interconnection evaporation, completes the preparation of device.
Production result such as Fig. 4 (f) of above-mentioned steps seven and step 8.
Embodiment 2: production fin GaN/AlGaN hetero-junctions width is 3 μm, and the grid neck height of T-type grid is 70nm, and grid cover is high Degree is the face the T grid N GaN/AlGaN fin high electron mobility transistor of 200nm.
Step 1: grown buffer layer.
The face the N GaN buffer layer that a layer thickness is 2 μm is grown using molecular beam epitaxy MBE on sic substrates, growth Process conditions are:
Growth temperature is 680 DEG C, and pressure is 5 × 10-3Pa。
Step 2: growth barrier layer.
The AlGaN that a layer thickness is 20nm is first grown using molecular beam epitaxy MBE in GaN layer, Al component is from top to bottom 30% is gradient to by 5%；Regrowth a layer thickness is 8nm, and Al group is divided into 30% AlGaN layer, and the process conditions of growth are:
Growth temperature is 680 DEG C, and pressure is 5 × 10-3Pa。
Step 3: growth channel layer.
The face the N GaN channel layer that a layer thickness is 25nm is grown using molecular beam epitaxy MBE in AlGaN layer, forms GaN/ The interface of AlGaN hetero-junctions, GaN channel layer and AlGaN potential barrier forms two-dimensional electron gas, and the process conditions of growth are:
Growth temperature is 680 DEG C, and pressure is 5 × 10-3Pa。
Step 4: etching fin GaN/AlGaN hetero-junctions.
The resist coating in GaN layer is exposed using electron beam lithography machine, obtains fin Fin pattern, recycles Cl2 It performs etching, the fin GaN/AlGaN hetero-junctions that formation width is 3 μm.
Step 5: production source, drain electrode.
The realization of this step is identical as the step of embodiment 1 five.
Step 6: production gate dielectric layer.
The realization of this step is identical as the step of embodiment 1 six.
Step 7: production gate electrode.
Electron beam lithography machine photoetching grid shape is used in grid groove location, then carries out evaporation of metal, Ti/Au is selected to do grid electricity Pole, wherein Ti is 70nm, then Au 200nm carries out metal-stripping, ultimately forms T-type grid metal electrode, the grid neck of T-type grid Height is 70nm, and grid neck length degree is 300nm, and the height of grid cover is 200nm, and the length of grid cover is 400nm.
Step 8: production passivation layer.
The realization of this step is identical as the step of embodiment 1 eight.
Embodiment 3: production fin GaN/AlGaN hetero-junctions width is 2.5 μm, and the grid neck height of T-type grid is 90nm, grid cover Height is the face the T grid N GaN/AlGaN fin high electron mobility transistor of 250nm.
Step A: grown buffer layer on substrate.
Using molecular beam epitaxy MBE equipment temperature be 680 DEG C, pressure be 5 × 10-3Under the process conditions of Pa, served as a contrast in SiC The face the N GaN buffer layer that a layer thickness is 2.5 μm is grown on bottom.
Step B: barrier layer is grown on the buffer layer.
Using molecular beam epitaxy MBE equipment temperature be 680 DEG C, pressure be 5 × 10-3It is slow in GaN under the process conditions of Pa The AlGaN for first growing that a layer thickness is 20nm is rushed on layer, and Al component is gradient to 30% by 5% from top to bottom, one thickness of regrowth Degree is 5nm, and Al group is divided into 30% AlGaN layer.
Step C: channel layer is grown on barrier layer.
Using molecular beam epitaxy MBE equipment temperature be 680 DEG C, pressure be 5 × 10-3Under the process conditions of Pa, in AlGaN The face the N GaN channel layer that a layer thickness is 22nm is grown on layer, forms GaN/AlGaN hetero-junctions, GaN channel layer and AlGaN potential barrier The interface of layer forms two-dimensional electron gas.
Step D: etching fin GaN/AlGaN hetero-junctions.
The resist coating in GaN layer is exposed using electron beam lithography machine, obtains fin Fin pattern, recycles Cl2 It performs etching, the fin GaN/AlGaN hetero-junctions that formation width is 2.5 μm.
Step E: production source, drain electrode.
The realization of this step is identical as the step of embodiment 1 five.
Step F: production gate dielectric layer.
The realization of this step is identical as the step of embodiment 1 six.
Step G: production gate electrode.
Electron beam lithography machine photoetching grid shape is used in grid groove location, then carries out evaporation of metal, Ti/Au is selected to do grid electricity Pole, wherein Ti is 90nm, then Au 250nm carries out metal-stripping, ultimately forms T-type grid metal electrode, the grid neck of T-type grid Height is 90nm, and grid neck length degree is 400nm, and the height of grid cover is 250nm, and the length of grid cover is 500nm.
Step H: production passivation layer.
The realization of this step is identical as the step of embodiment 1 eight.

Claims (9)

1. a kind of face T grid N GaN/AlGaN fin high electron mobility transistor includes substrate (1), GaN buffer layer from bottom to top (2), AlGaN potential barrier (3), GaN channel layer (4), gate dielectric layer (5), passivation layer (6) and grid, source, drain electrode, GaN channel layer GaN/AlGaN hetero-junctions is formed with AlGaN potential barrier, it is characterised in that:
GaN buffer layer and channel layer are all made of the face N GaN；
Gate electrode uses T-type grid, and is wrapped in the two sides and top of GaN/AlGaN hetero-junctions, forms 3 D stereo grid structure.
2. the face T grid N GaN/AlGaN fin high electron mobility transistor according to claim 1, wherein substrate (1) is adopted With sapphire or the face SiC or N GaN.
3. the face T grid N GaN/AlGaN fin high electron mobility transistor according to claim 1, wherein buffer layer (2) Using the face N GaN, with a thickness of 1.5~3 μm.
4. the face T grid N GaN/AlGaN fin high electron mobility transistor according to claim 1, wherein AlGaN potential barrier Layer (3) includes two layers of AlGaN, first layer from top to bottom be with a thickness of 20nm, Al component from 5% be gradient to 30% AlGaN, The second layer is with a thickness of 5~10nm, and Al group is divided into 30% AlGaN.
5. the face T grid N GaN/AlGaN fin high electron mobility transistor according to claim 1, wherein channel layer (4) Using the face N GaN, with a thickness of 20~30nm.
6. GaN base fin high electron mobility transistor in the face N according to claim 1, wherein gate dielectric layer (5) uses SiN, with a thickness of 5~10nm.
7. the face T grid N GaN/AlGaN fin high electron mobility transistor according to claim 1, wherein T-type grid are by grid Neck and grid cover composition, the height of grid neck are 40~90nm, and the length of grid neck is 200~500nm, the height of grid cover is 100~ 300nm, the length of grid cover are 300~600nm.
8. a kind of production method of the face T grid N GaN/AlGaN fin high electron mobility transistor, includes the following steps:
1) on the face C SiC, a surface sapphire or the face N GaN single crystal substrate, molecular beam epitaxy MBE or metallo-organic compound are utilized Chemical vapor deposition MOCVD grows 1.5~3 μm of the face N GaN buffer layer；
2) AlGaN of 20nm thickness is first grown on GaN buffer layer, Al component is gradient to 30% from 5%；Regrowth is with a thickness of 5 The AlGaN of~10nm, Al group are divided into 30%；
3) face the N GaN channel layer that growth thickness is 20~30nm in AlGaN potential barrier；
4) by etching GaN channel layer, the marginal portion of AlGaN potential barrier and GaN buffer layer, it is different to form fin GaN/AlGaN Matter knot；
5) source, drain electrode are made at the both ends of GaN channel layer upper surface；
6) using atomic layer deposition ALD or plasma enhanced CVD PECVD technique in AlGaN potential barrier and GaN Channel layer surface grows gate dielectric layer；
7) the photoetching T-type grid shape on gate dielectric layer, and deposited by electron beam evaporation prepares gate electrode；
8) passivation layer is deposited using plasma enhanced CVD PECVD in semiconductor and electrode surface, etches power down Extra passivation layer on the bonding point of pole, row metal of going forward side by side interconnection evaporation, completes the preparation of device.
9. the production method of the face T grid N GaN/AlGaN fin high electron mobility transistor according to claim 8, wherein The width of fin GaN/AlGaN hetero-junctions is 2~5 μm.
CN201710885208.XA 2017-09-26 2017-09-26 The face T grid N GaN/AlGaN fin high electron mobility transistor Pending CN109560118A (en)

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CN110571265A (en) * 2019-07-30 2019-12-13 西安电子科技大学 GaN-based fin field effect transistor device and manufacturing method thereof
CN112071902A (en) * 2020-08-14 2020-12-11 中国电子科技集团公司第五十五研究所 Spin-polarized coupled GaN high-electron-mobility transistor
WO2021109073A1 (en) * 2019-12-05 2021-06-10 苏州晶湛半导体有限公司 Semiconductor structure and manufacturing method therefor
CN114050208A (en) * 2021-11-11 2022-02-15 上海大学 Improved high electron mobility light emitting transistor
CN114883407A (en) * 2022-07-11 2022-08-09 成都功成半导体有限公司 HEMT based on Fin-FET gate structure and manufacturing method thereof
WO2023092407A1 (en) * 2021-11-25 2023-06-01 华为技术有限公司 High electron mobility transistor, radio frequency transistor, power amplifier, and method for preparing high electron mobility transistor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110571265A (en) * 2019-07-30 2019-12-13 西安电子科技大学 GaN-based fin field effect transistor device and manufacturing method thereof
WO2021109073A1 (en) * 2019-12-05 2021-06-10 苏州晶湛半导体有限公司 Semiconductor structure and manufacturing method therefor
CN112071902A (en) * 2020-08-14 2020-12-11 中国电子科技集团公司第五十五研究所 Spin-polarized coupled GaN high-electron-mobility transistor
CN112071902B (en) * 2020-08-14 2022-07-29 中国电子科技集团公司第五十五研究所 Spin-polarized coupled GaN high-electron-mobility transistor
CN114050208A (en) * 2021-11-11 2022-02-15 上海大学 Improved high electron mobility light emitting transistor
WO2023092407A1 (en) * 2021-11-25 2023-06-01 华为技术有限公司 High electron mobility transistor, radio frequency transistor, power amplifier, and method for preparing high electron mobility transistor
CN114883407A (en) * 2022-07-11 2022-08-09 成都功成半导体有限公司 HEMT based on Fin-FET gate structure and manufacturing method thereof
CN114883407B (en) * 2022-07-11 2022-11-01 成都功成半导体有限公司 HEMT based on Fin-FET gate structure and manufacturing method thereof

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