CN104392969A - 一种多芯片集成电路抗冲击封装结构 - Google Patents

一种多芯片集成电路抗冲击封装结构 Download PDF

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CN104392969A
CN104392969A CN201410535314.1A CN201410535314A CN104392969A CN 104392969 A CN104392969 A CN 104392969A CN 201410535314 A CN201410535314 A CN 201410535314A CN 104392969 A CN104392969 A CN 104392969A
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integrated circuit
sealing
packaging structure
hard
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夏俊生
邹建安
周峻霖
潘大卓
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No 214 Institute of China North Industries Group Corp
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No 214 Institute of China North Industries Group Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及一种多芯片集成电路抗冲击封装结构，其特征在于：将裸芯片（1）和引线（2）键合区集中布置在基板（3）上，采用盖帽（8）将裸芯片（1）及引线键合区置入盖帽内部，盖帽（8）内灌封软质封装材料（10），壳体（12）内集成电路其它部分整体灌封硬质封装材料（11）。本发明的优点在于：盖帽内软质材料灌封能够保护芯片和引线键合在环境应力(尤其是温度变化应力)下不受损伤，又能发挥整体硬质灌封的抗冲击防护作用。盖帽保护结构能够有效防止硬质材料对软质材料的挤压影响和温度应力影响，使芯片和引线键合得到进一步的保护，提高了产品的组装可靠性。

Description

一种多芯片集成电路抗冲击封装结构
技术领域
本发明涉及集成电路技术领域，特别涉及一种多芯片集成电路抗冲击封装结构。
背景技术
内部灌封是提高混合集成电路抗冲击水平的重要手段，为保证灌封效果，电路整体灌封通常均采用硬质材料灌封方式，其目的是吸收、分散电路内部基板、元件承受的高过载冲击应力，以提高电路整体抗冲击能力。由于整体灌封均采用硬质材料，这种灌封在环境应力(尤其是温度变化应力)作用下容易损伤引线键合和芯片表面，例如，会导致键合线断裂、键合点互连失效等，混合集成电路中裸芯片较多，很容易由此导致电路的性能参数失效。
发明内容
本发明的目的就是为了解决现有的集成电路整体硬质材料灌封结构，在环境应力作用下容易损伤引线键合和芯片表面的缺点，提供一种多芯片集成电路抗冲击封装结构。
为了实现上述目的，本发明采用如下技术方案
一种多芯片集成电路抗冲击封装结构，包括壳体以及其中连接的基板，其特征在于：
a、将裸芯片和引线键合区集中布置在基板上；
b、采用陶瓷或金属盖帽粘接在基板表面，使裸芯片及引线键合区置入盖帽内部，盖帽顶部开有小孔；
c、盖帽内灌封软质封装材料；
d、壳体内集成电路其它部分整体灌封硬质封装材料。
上述技术方案中，所述的硬质封装材料是现有技术，典型的是环氧树脂。所述的软质封装材料，典型的是硫化硅橡胶。
本发明的优点在于：
(1)采用了复合灌封方式，一方面，局部软质材料灌封能够保护芯片和引线键合在环境应力(尤其是温度变化应力)下不受损伤；另一方面，又能发挥整体硬质灌封的抗冲击防护作用。
(2)盖帽保护结构能够有效防止硬质材料对软质材料的挤压影响和温度应力影响，使芯片和引线键合得到进一步的保护，提高了产品的组装可靠性。
附图说明
图1是本发明的多芯片集成电路基板表面组装俯视图；
图2是图1中集成电路内部灌封结构示意图。
具体实施方式
　　 (1) 如图1所示，先将裸芯片1和引线2键合区集中布置在电路基板3中部，在裸芯片键合区周边预留盖帽粘接区4。完成裸芯片1与基板3之间的引线2键合组装、基板3与外壳底座12组装、基板与外壳引线5之间的电连接，以及基板上其它元件6组装。其中，基板3与外壳引线5采用常规的套装互连方式，即基板3边缘设有通孔，外壳引线5穿过通孔，且用导电材料7（导电环氧或焊料等）在通孔周边实现引线与通孔焊盘的互连。 
(2) 制作盒体结构的盖帽8，盖帽顶部开有小孔9，盖帽材料可用陶瓷或金属等刚性材料。用粘接材料13将盖帽粘接在裸芯片键合区周边的粘接区4位置上，使裸芯片及其引线键合置于盖帽内部。
  (3) 用连续滴注或注射等方式通过盖帽上面的小孔9，将软质材料10注入盖帽内（所述的软质封装材料，典型的是硫化硅橡胶），固化后即完成盖帽内灌封。然后再用硬质材料11对外壳12内电路其它部分进行整体灌封。
(4) 这种灌封结构的产品外壳端面可以加盖密封，也可不加盖密封。

Claims (1)

1.一种多芯片集成电路抗冲击封装结构，包括壳体（12）以及其中连接的基板（3），其特征在于：
a、将裸芯片（1）和引线（2）键合区集中布置在基板（3）上；
b、采用陶瓷或金属盖帽（8）粘接在基板表面，使裸芯片及引线键合区置入盖帽内部，盖帽（8）顶部开有小孔（9）；
c、盖帽（8）内灌封软质封装材料（10）；
d、壳体（12）内集成电路其它部分整体灌封硬质封装材料（11）。
CN201410535314.1A 2014-10-13 2014-10-13 一种多芯片集成电路抗冲击封装结构 Pending CN104392969A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331499A (zh) * 2017-06-30 2017-11-07 深圳市崧盛电子股份有限公司 电路结构的灌封方法及灌封电路结构
CN110600432A (zh) * 2019-05-27 2019-12-20 华为技术有限公司 一种封装结构及移动终端
CN111622747A (zh) * 2020-05-14 2020-09-04 中国科学院地质与地球物理研究所 随钻声波测井仪器接收换能器阵列全数字化装置
CN114554718A (zh) * 2022-03-21 2022-05-27 四川九洲空管科技有限责任公司 一种安装板置于外壳内只露插针的灌封工艺

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567708A (ja) * 1991-09-09 1993-03-19 Seiko Epson Corp 半導体集積回路のパツケージ方法
US5386342A (en) * 1992-01-30 1995-01-31 Lsi Logic Corporation Rigid backplane formed from a moisture resistant insulative material used to protect a semiconductor device
US5585600A (en) * 1993-09-02 1996-12-17 International Business Machines Corporation Encapsulated semiconductor chip module and method of forming the same
US5793118A (en) * 1994-05-26 1998-08-11 Nec Corporation Semiconductor device capable of accomplishing a high moisture proof
CN1342035A (zh) * 2000-09-04 2002-03-27 三洋电机株式会社 电路装置及其制造方法
CN1352804A (zh) * 1999-05-18 2002-06-05 阿梅拉西亚国际技术公司 高密度电子封装及其制造方法
CN1455960A (zh) * 2001-01-24 2003-11-12 日亚化学工业株式会社 发光二极管、光学半导体元件及适用的环氧树脂组合物及其制造方法
CN1581482A (zh) * 2003-07-31 2005-02-16 三洋电机株式会社 电路模块
CN101552264A (zh) * 2008-02-27 2009-10-07 英飞凌科技股份有限公司 功率模块
CN102405523A (zh) * 2009-04-21 2012-04-04 罗伯特·博世有限公司 用于具有吸收层的衬底的封装电路装置及其制造方法
CN103066192A (zh) * 2013-01-10 2013-04-24 李刚 半导体发光光源及制造该光源和半导体发光芯片的方法
CN103219446A (zh) * 2012-01-20 2013-07-24 日亚化学工业株式会社 发光装置用封装成形体和使用了它的发光装置
CN203351591U (zh) * 2013-07-23 2013-12-18 长兴芯亿微电子科技有限公司 一种柔性基板封装结构
CN203398110U (zh) * 2013-07-03 2014-01-15 叶逸仁 定型定规封装的led光源组合

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567708A (ja) * 1991-09-09 1993-03-19 Seiko Epson Corp 半導体集積回路のパツケージ方法
US5386342A (en) * 1992-01-30 1995-01-31 Lsi Logic Corporation Rigid backplane formed from a moisture resistant insulative material used to protect a semiconductor device
US5585600A (en) * 1993-09-02 1996-12-17 International Business Machines Corporation Encapsulated semiconductor chip module and method of forming the same
US5793118A (en) * 1994-05-26 1998-08-11 Nec Corporation Semiconductor device capable of accomplishing a high moisture proof
CN1352804A (zh) * 1999-05-18 2002-06-05 阿梅拉西亚国际技术公司 高密度电子封装及其制造方法
CN1342035A (zh) * 2000-09-04 2002-03-27 三洋电机株式会社 电路装置及其制造方法
CN1455960A (zh) * 2001-01-24 2003-11-12 日亚化学工业株式会社 发光二极管、光学半导体元件及适用的环氧树脂组合物及其制造方法
CN1581482A (zh) * 2003-07-31 2005-02-16 三洋电机株式会社 电路模块
CN101552264A (zh) * 2008-02-27 2009-10-07 英飞凌科技股份有限公司 功率模块
CN102405523A (zh) * 2009-04-21 2012-04-04 罗伯特·博世有限公司 用于具有吸收层的衬底的封装电路装置及其制造方法
CN103219446A (zh) * 2012-01-20 2013-07-24 日亚化学工业株式会社 发光装置用封装成形体和使用了它的发光装置
CN103066192A (zh) * 2013-01-10 2013-04-24 李刚 半导体发光光源及制造该光源和半导体发光芯片的方法
CN203398110U (zh) * 2013-07-03 2014-01-15 叶逸仁 定型定规封装的led光源组合
CN203351591U (zh) * 2013-07-23 2013-12-18 长兴芯亿微电子科技有限公司 一种柔性基板封装结构

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331499A (zh) * 2017-06-30 2017-11-07 深圳市崧盛电子股份有限公司 电路结构的灌封方法及灌封电路结构
CN110600432A (zh) * 2019-05-27 2019-12-20 华为技术有限公司 一种封装结构及移动终端
CN111622747A (zh) * 2020-05-14 2020-09-04 中国科学院地质与地球物理研究所 随钻声波测井仪器接收换能器阵列全数字化装置
CN114554718A (zh) * 2022-03-21 2022-05-27 四川九洲空管科技有限责任公司 一种安装板置于外壳内只露插针的灌封工艺
CN114554718B (zh) * 2022-03-21 2023-10-24 四川九洲空管科技有限责任公司 一种安装板置于外壳内只露插针的灌封工艺

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