CN104376818B - Liquid crystal display and its gate drivers - Google Patents
Liquid crystal display and its gate drivers Download PDFInfo
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- CN104376818B CN104376818B CN201310353989.XA CN201310353989A CN104376818B CN 104376818 B CN104376818 B CN 104376818B CN 201310353989 A CN201310353989 A CN 201310353989A CN 104376818 B CN104376818 B CN 104376818B
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Abstract
A kind of liquid crystal display and its gate drivers.Gate drivers include the first output unit, the second output unit, the first counter, the second counter and multiplexing unit.First counter is according to the first initial signal and polar signal counting clock signal controlling the first output unit to export odd gates drive signal.Second counter is according to the second initial signal and polar signal counting clock signal controlling the second output unit to export even gate drive signal.Multiplexing unit is optionally exported to the first counter or the second counter polar signal.
Description
Technical field
The invention relates to a kind of electronic installation, and in particular to a kind of liquid crystal display and its raster data model
Device.
Background technology
Because liquid crystal display (Liquid Crystal Display, LCD) device has, power consumption is low, caloric value is few, weight
The characteristics such as light and non-radiation type are measured, therefore is used in electronic product miscellaneous, and little by little replace traditional the moon
Extreme ray pipe (Cathode Ray Tube, CRT) display device.The liquid crystal molecule of liquid crystal display device has a kind of characteristic, is exactly
Can not always fixed drive it is constant in same polar voltages.The otherwise time one is long, even if this voltage is canceled, liquid crystal molecule
Can cannot be rotated in response to the change of electric field again because of the destruction of characteristic.Therefore at regular intervals just must be by polarity of voltage
Change, destroyed with the characteristic for avoiding liquid crystal molecule.
Liquid crystal display panel common at present can be divided into normal pixels (Normal Pixel) array and upset pixel (Flip
Pixel) array.The reversal mode of conventional pixel array is to adopt 1+2 lines reversion (Line Inversion), and overturns picture
The reversal mode of pixel array is to carry out reversion (Column Inversion).However, upset pel array aperture opening ratio compared with
It is low, and the power consumption of the reversal mode of 1+2 lines reversion is larger.Therefore, how high aperture and low power consumption to be had concurrently simultaneously
Become a considerable problem.
The content of the invention
The invention relates to a kind of liquid crystal display and its gate drivers.
According to the present invention it is proposed that a kind of liquid crystal display.Liquid crystal display include odd-numbered scan lines, even-line interlace line, often
Rule pixel (Normal Pixel) array, data wire, data driver, gate drivers and time schedule controller.Normal pixels battle array
Row include odd column pixel and even column pixels.Odd column pixel is controllable by odd-numbered scan lines, and even column pixels are controlled
In even-line interlace line.Odd column pixel is adjacent with even column pixels and positioned at same a line.Data wire connects odd column pixel and idol
Ordered series of numbers pixel.Data driver connects data wire.Gate drivers are defeated according to clock signal, the first initial signal and polar signal
Go out odd number gate drive signal to odd-numbered scan lines, and even number is exported according to clock signal, the second initial signal and polar signal
Gate drive signal is to even-line interlace line.Time schedule controller provides clock signal and polar signal.
According to the present invention it is proposed that a kind of gate drivers.Gate drivers include that the first output unit, the second output are single
Unit, the first counter, the second counter and multiplexing unit.When first counter is counted according to the first initial signal and polar signal
Clock signal exports odd gates drive signal to control the first output unit.Second counter is according to the second initial signal and polarity
Signal-count clock signal exports even gate drive signal to control the second output unit.Multiplexing unit is optionally by polarity
Signal output is to the first counter or the second counter.
More preferably understand to have to above and other of the invention aspect, preferred embodiment cited below particularly, and coordinate institute
Accompanying drawings, are described in detail below.
Brief description of the drawings
Fig. 1 is schematically shown as the schematic diagram according to a kind of liquid crystal display of first embodiment.
Fig. 2 is schematically shown as the partial schematic diagram of scan line, data wire, odd column pixel and even column pixels.
Fig. 3 is schematically shown as the schematic diagram according to a kind of gate drivers of first embodiment.
Fig. 4 is schematically shown as according to a kind of signal timing diagram of first embodiment.
Fig. 5 is schematically shown as according to a kind of signal timing diagram of second embodiment.
Fig. 6 is schematically shown as according to a kind of signal timing diagram of 3rd embodiment.
[label declaration]
1：Liquid crystal display 11：Odd-numbered scan lines
12：Even-line interlace line 13：Conventional pixel array
14：Data wire 15：Data driver
17：Time schedule controller 131：Odd column pixel
132：Even column pixels 161：First output unit
162：Second output unit 163：First counter
164：Second counter 165：Multiplexing unit
GD_1~DG_i：Gate drivers
G(1)、G(3)、G(5)、…、G(2N-1)：Odd gates drive signal
G(2)、G(4)、G(6)、…、G(2N)：Even gate drive signal
LD：Breech lock enable signal STV：Initial signal
STV1R：First initial signal STV2R：Second initial signal
STV1L：3rd initial signal STV2L：Fourth beginning signal
CKV：Clock signal POL：Polar signal
P (1)~P (n)：Clock H：First level
L：Second electrical level JUMP：Jump signal
Tf：Image time Ta, Tb：Period
Specific embodiment
First embodiment
The schematic diagram according to a kind of liquid crystal display of first embodiment is schematically shown as referring to Fig. 1 and Fig. 2, Fig. 1, is schemed
2 partial schematic diagrams for being schematically shown as scan line, data wire, odd column pixel and even column pixels.Liquid crystal display 1 is swept including odd number
Line 11, even-line interlace line 12, normal pixels (Normal Pixel) array 13, data wire 14, data driver 15, grid is retouched to drive
Dynamic device GD_1~DG_i and time schedule controller 17, i are greater than 1 positive integer.Gate drivers GD_2 is gate drivers GD_1
Next stage, gate drivers GD_3 for gate drivers GD_2 next stage.By that analogy, gate drivers GD_i is grid
The next stage of driver GD_i-1.Conventional pixel array 13 includes odd column pixel 131 and even column pixels 132.Odd column picture
Element 131 be controllable by odd-numbered scan lines 11 one of them, and even column pixels 132 be controllable by even-line interlace line 12 wherein it
One.Adjacent and positioned at same a line odd column pixel 131 is connected to identical data wire 14 with even column pixels 132.
Each gate drivers GD_1~DG_i is according to clock signal CKV, the first initial signal STVR1 and polar signal POL
Multiple odd gates drive signals G (1) of output, G (3), G (5) ..., G (2N-1) believes to odd-numbered scan lines 11 according to clock
Number CKV, the second initial signal STVR2 and polar signal POL export even gate drive signal G (2), G (4), G (6) ..., G
(2N) is to even-line interlace line 12.Wherein, N is greater than 1 positive integer.Time schedule controller 17 provides breech lock enable signal LD, starting
Signal STV, clock signal CKV and polar signal POL.Initial signal STV can be as positioned at the gate drivers GD_ of the first order
1 the first initial signal STV1R and the second initial signal STV2R.Foregoing time schedule controller 17 can adjust polar signal POL with
Control gate driver 16 change odd gates drive signal G (1), G (3), G (5) ..., G (2N-1) and even gate drive letter
Number G (2), G (4), G (6) ..., the output of G (2N) sequentially.
Refer to Fig. 1 and schematic diagram that Fig. 3, Fig. 3 are schematically shown as according to a kind of gate drivers of first embodiment.Foregoing grid
Driver GD_1~DG_i is the explanation by taking gate drivers 16 as an example in Fig. 3.Gate drivers 16 include the first output unit
161st, the second output unit 162, the first counter 163, the second counter 164 and multiplexing unit 165.First 163, counter
Such as it is counting forward, counting in reverse or hop count, and the second counter 164 is, for example, counting forward, counting in reverse or jump
Count.
First counter 163 is according to the first initial signal STV1R and polar signal POL counting clock signals CKV controlling
First output unit 161 export odd gates drive signal G (1), G (3), G (5) ..., G (2N-1).Second 164, counter
According to the second initial signal STV2R and polar signal POL counting clock signals CKV with control the second output unit 162 export even number
Gate drive signal G (2), G (4), G (6) ..., G (2N).Polar signal POL is optionally exported first by multiplexing unit 165
The counter 164 of counter 163 or second.
First counter 163 exports the 3rd initial signal STV1L according to the first initial signal STV1R and polar signal POL
To the gate drivers of next stage, the 3rd initial signal STV1L is used to close and reset first counter 163 of this grade, and calls out
First counter 163 of awake next stage.Second counter 164 is according to the second initial signal STV2R and polar signal POL outputs the
Four initial signal STV2L to next stage gate drivers, fourth beginning, signal STV2L was used to close and reset the second of this grade
Counter 164, and wake up the second counter 164 of the gate drivers of next stage.
For example, first counter 163 of gate drivers GD_1 is according to the first initial signal STV1R and polar signal
POL exports the 3rd initial signal STV1L to gate drivers GD_2, and the 3rd initial signal STV1L is used to close and reset grid
First counter 163 of driver GD_1, and wake up first counter 163 of gate drivers GD_2.Second 164, counter
Fourth beginning signal STV2L is exported to gate drivers GD_2 according to the second initial signal STV2R and polar signal POL, fourth
Beginning signal is used to close and reset second counter 164 of gate drivers GD_1, and wakes up the second of gate drivers GD_2
Counter 164.
Fig. 1, Fig. 3 and Fig. 4 are refer to, Fig. 4 is schematically shown as according to a kind of signal timing diagram of first embodiment.For example,
First counter 163 and the second counter 164 are counting forwards.When gate drivers GD_1 receives initial signal STV and polarity
After signal POL changes into the first level H by second electrical level L, the counting clock signal of the first counter 163 of gate drivers GD_1
CKV exports odd gates drive signal G (1), G (3), G (5), G (7), G (9) and G (11) to control the first output unit 161.
Wherein, clock signal CKV includes the 1st clock P (1)~n-th clock P (N), and the first level H is more than second electrical level L.Connect
, after polar signal POL changes into second electrical level L by the first level H, second counter 164 of gate drivers GD_1 is counted
Number clock signal CKV exports even gate drive signal G (2), G (4), G (6), G (8), G to control the second output unit 162
And G (12) (10).
And then, after polar signal POL changes into the first level H by second electrical level L, first meter of gate drivers GD_1
The number counting clock signal CKV of device 163 exports odd gates drive signal G (13), G (15), G to control the first output unit 161
And G (19) (17).Then, after polar signal POL changes into second electrical level L by the first level H, the of gate drivers GD_1
The counting clock signal CKV of two counter 164 exports even gate drive signal G (14), G to control the second output unit 162
(16), G (18), G (20) and G (22).
Then, after polar signal POL changes into the first level H by second electrical level L, the counting clock of the first counter 163
Signal CKV with control the first output unit 161 export odd gates drive signal G (21) ..., G (2N-3), G (2N-1) and G
(1).As n-th clock P (N) of the counting clock signal CKV of the first counter 163, the 3rd initial signal STV1L conducts are exported
The first initial signal STV1R of gate drivers GD_2.3rd initial signal STV1L is used to close and reset gate drivers
First counter 163 of GD_1, and wake up first counter 163 of gate drivers GD_2.The first of gate drivers GD_2
Counter 163 starts counting up clock signal CKV.The counting clock signal CKV of first counter 163 of gate drivers GD_2 is controlling
Make the first output unit 161 and export odd gates drive signal G (1).
And then, after polar signal POL changes into second electrical level L by the first level H, the counting clock of the second counter 164
Signal CKV with control the second output unit 162 export even gate drive signal G (24) ..., G (2N-2) and G (2N).Work as grid
During n-th clock P (N) of the counting clock signal CKV of the second counter 164 of driver GD_2, fourth beginning signal is exported
STV2L as gate drivers GD_2 the first initial signal STV2R.Fourth beginning, signal STV2L was used to close and reset grid
Second counter 164 of driver GD_1, and wake up second counter 164 of gate drivers GD_2.Gate drivers GD_
2 the second counter 164 starts counting up clock signal CKV.The counting clock signal of second counter 164 of gate drivers GD_2
CKV exports even gate drive signal G (2), G (4) and G (6) to control the second output unit 162.
Then, after polar signal POL changes into the first level H by second electrical level L, first meter of gate drivers GD_2
The number counting clock signal CKV of device 163 exports odd gates drive signal G (3), G (5), G (7) to control the first output unit 161
And G (9).Then, after polar signal POL changes into second electrical level L by the first level H, second meter of gate drivers GD_2
Number the counting clock signal CKV of device 164 with control the second output unit 162 export even gate drive signal G (8), G (10) ...,
G(2N-4).And then, after polar signal POL changes into the first level H by second electrical level L, first meter of gate drivers GD_2
Number the counting clock signal CKV of device 163 with control the first output unit 161 export odd gates drive signal G (11) ..., G (2N-
And G (2N-1) 3).
As n-th clock P (N) of the counting clock signal CKV of the first counter 163 of gate drivers GD_2, output
3rd initial signal STV1L as gate drivers GD_3 the first initial signal STV1R.3rd initial signal STV1L is used to
Close and reset first counter 163 of gate drivers GD_2, and wake up first counter 163 of gate drivers GD_3.
Then, the counting clock signal CKV of the second counter 164 of gate drivers GD_2 is controlling the second output unit 162 to export idol
Number gate drive signal G (2N-2) and G (2N).As the second counter 164 counting clock signal CKV of gate drivers GD_2
During n-th clock P (N), second initial signal STV2Rs of fourth beginning signal STV2L as gate drivers GD_3 is exported.With
This analogizes, can obtain odd gates drive signal G (1) of gate drivers GD_3~DG_i, G (3), G (5) ..., G (2N-1) with
Even gate drive signal G (2), G (4), G (6) ..., the output of G (2N) sequentially.
Second embodiment
Fig. 1, Fig. 3 and Fig. 5 are refer to, Fig. 5 is schematically shown as according to a kind of signal timing diagram of second embodiment.Second embodiment
It is counting in reverse with the first counter 163 that first embodiment main difference part is second embodiment, and the second counter
164 is counting forward.When gate drivers GD_1 receives initial signal STV and polar signal POL changes into by second electrical level L
After one level H, the counting clock signal CKV of the first counter 163 of gate drivers GD_1 is controlling the first output unit 161 defeated
Go out odd number gate drive signal G (2N-1), G (2N-3), G (2N-5), G (2N-7), G (2N-9) and G (2N-11).Then, pole is worked as
Property signal POL second electrical level L is changed into by the first level H after, the counting clock of the second counter 164 of gate drivers GD_1 letter
Number CKV exports even gate drive signal G (2), G (4), G (6), G (8), G (10) and G to control the second output unit 162
(12)。
And then, after polar signal POL changes into the first level H by second electrical level L, first meter of gate drivers GD_1
The number counting clock signal CKV of device 163 exports odd gates drive signal G (2N-13), G (2N- to control the first output unit 161
15), G (2N-17) and G (2N-19).Then, after polar signal POL changes into second electrical level L by the first level H, grid drives
The counting clock signal CKV of second counter 164 of dynamic device GD_1 drives letter to control the second output unit 162 to export even gate
Number G (14), G (16), G (18), G (20) and G (22).
Then, after polar signal POL changes into the first level H by second electrical level L, the counting clock of the first counter 163
Signal CKV with control the first output unit 161 export odd gates drive signal G (2N-21) ..., G (3) and G (1).When first
During n-th clock P (N) of the counting clock signal CKV of counter 163, the 3rd initial signal STV1L is used as gate drivers for output
The first initial signal STV1R of GD_2.3rd initial signal STV1L is used to close and reset first meter of gate drivers GD_1
Number device 163, and wake up first counter 163 of gate drivers GD_2.First counter 163 of gate drivers GD_2 starts
Counting clock signal CKV.The counting clock signal CKV of first counter 163 of gate drivers GD_2 is controlling the first output list
Unit 161 exports odd gates drive signal G (2N-1).
And then, after polar signal POL changes into second electrical level L by the first level H, the counting clock of the second counter 164
Signal CKV with control the second output unit 162 export even gate drive signal G (24) ..., G (2N-2) and G (2N).Work as grid
During n-th clock P (N) of the counting clock signal CKV of the second counter 164 of driver GD_2, fourth beginning signal is exported
STV2L as gate drivers GD_2 the first initial signal STV2R.Fourth beginning, signal STV2L was used to close and reset grid
Second counter 164 of driver GD_1, and wake up second counter 164 of gate drivers GD_2.Gate drivers GD_
2 the second counter 164 starts counting up clock signal CKV.The counting clock signal of second counter 164 of gate drivers GD_2
CKV exports even gate drive signal G (2) again to control the second output unit 162.
3rd embodiment
Fig. 1, Fig. 3 and Fig. 6 are refer to, Fig. 6 is schematically shown as according to a kind of signal timing diagram of 3rd embodiment.3rd embodiment
It is jump meter with the first counter 163 and the second counter 164 that first embodiment main difference part is 3rd embodiment
Number.Image time Tf includes period Ta and period Tb.Period Ta for image time Tf 1/2nd, and period Tb be picture when
Between Tf 1/2nd.In period Ta, jump signal JUMP is equal to second electrical level L.In period Tb, jump signal JUMP is equal to the
One level H.
In period Ta, after polar signal POL changes into the first level H by second electrical level L and jump signal JUMP is equal to
Second electrical level L, the counting clock signal CKV of the first counter 163 are driven with controlling the first output unit 161 to export the 4n-3 grid
Dynamic signal.After polar signal POL changes into second electrical level L by the first level H and jump signal is equal to second electrical level L, second
The counting clock signal CKV of counter 164 exports the 4n-2 gate drive signal to control the second output unit 162.Wherein, n
It is the positive integer more than 1.
In period Tb, after polar signal POL changes into the first level H by second electrical level L and jump signal JUMP is equal to
First level H, the counting clock signal CKV of the first counter 163 are driven with controlling the first output unit 161 to export the 4n-1 grid
Dynamic signal.After polar signal POL changes into second electrical level L by the first level H and jump signal JUMP be equal to the first level H,
The counting clock signal CKV of second counter 164 exports the 4n gate drive signal to control the second output unit 162.
For example, in period Ta, when gate drivers GD_1 receives initial signal STV and polar signal POL is by second
After level L changes into the first level H, the counting clock signal CKV of the first counter 163 of gate drivers GD_1 is controlling first
Output unit 161 exports odd gates drive signal G (1), G (5), G (9), G (13), G (17) and G (21).Then, polarity is worked as
After signal POL changes into second electrical level L by the first level H, the counting clock signal of the second counter 164 of gate drivers GD_1
CKV exports even gate drive signal G (2), G (6), G (10), G (14), G (18) and G to control the second output unit 162
(22)。
And then, after polar signal POL changes into the first level H by second electrical level L, first meter of gate drivers GD_1
The number counting clock signal CKV of device 163 exports odd gates drive signal G (25), G (29), G to control the first output unit 161
And G (37) (33).Then, after polar signal POL changes into second electrical level L by the first level H, the of gate drivers GD_1
The counting clock signal CKV of two counter 164 exports even gate drive signal G (26), G to control the second output unit 162
(30), G (34), G (38) and G (42).
Then, after polar signal POL changes into the first level H by second electrical level L, the counting clock of the first counter 163
Signal CKV with control the first output unit 161 export odd gates drive signal G (41) ..., G (4N-7) and G (4N-3).When
During n-th clock P (N) of the counting clock signal CKV of the first counter 163, the 3rd initial signal STV1L of output drives as grid
The first initial signal STV1R of dynamic device GD_2.3rd initial signal STV1L is used to close and reset the of gate drivers GD_1
One counter 163, and wake up first counter 163 of gate drivers GD_2.First counter 163 of gate drivers GD_2
Start counting up clock signal CKV.The counting clock signal CKV of first counter 163 of gate drivers GD_2 is first defeated to control
Go out unit 161 and export odd gates drive signal G (1).
And then, after polar signal POL changes into second electrical level L by the first level H, the counting clock of the second counter 164
Signal CKV with control the second output unit 162 export even gate drive signal G (46) ..., G (4N-6) and G (4N-2).When
During n-th clock P (N) of the counting clock signal CKV of the second counter 164 of gate drivers GD_2, fourth letter that begins is exported
Number STV2L as gate drivers GD_2 the first initial signal STV2R.Signal STV2L was used to close and reset fourth beginning
Second counter 164 of gate drivers GD_1, and wake up second counter 164 of gate drivers GD_2.Gate drivers
Second counter 164 of GD_2 starts counting up clock signal CKV.The counting clock of second counter 164 of gate drivers GD_2
Signal CKV exports even gate drive signal G (2) again to control the second output unit 162.
In period Tb, when gate drivers GD_1 receives initial signal STV and polar signal POL is changed by second electrical level L
After the first level H, the counting clock signal CKV of the first counter 163 of gate drivers GD_1 is controlling the first output unit
161 outputs odd gates drive signal G (3), G (7), G (11), G (15), G (19) and G (23).Then, as polar signal POL
After changing into second electrical level L by the first level H, the counting clock signal CKV of the second counter 164 of gate drivers GD_1 is controlling
Make the second output unit 162 and export even gate drive signal G (4), G (8), G (12), G (16), G (20) and G (24).
And then, after polar signal POL changes into the first level H by second electrical level L, first meter of gate drivers GD_1
The number counting clock signal CKV of device 163 exports odd gates drive signal G (27), G (31), G to control the first output unit 161
And G (39) (35).Then, after polar signal POL changes into second electrical level L by the first level H, the of gate drivers GD_1
The counting clock signal CKV of two counter 164 exports even gate drive signal G (28), G to control the second output unit 162
(32), G (36), G (40) and G (44).
Then, after polar signal POL changes into the first level H by second electrical level L, the counting clock of the first counter 163
Signal CKV with control the first output unit 161 export odd gates drive signal G (43) ..., G (4N-5) and G (4N-1).When
During n-th clock P (N) of the counting clock signal CKV of the first counter 163, the 3rd initial signal STV1L of output drives as grid
The first initial signal STV1R of dynamic device GD_2.3rd initial signal STV1L is used to close and reset the of gate drivers GD_1
One counter 163, and wake up first counter 163 of gate drivers GD_2.First counter 163 of gate drivers GD_2
Start counting up clock signal CKV.The counting clock signal CKV of first counter 163 of gate drivers GD_2 is first defeated to control
Go out unit 161 and export odd gates drive signal G (3).
And then, after polar signal POL changes into second electrical level L by the first level H, the counting clock of the second counter 164
Signal CKV with control the second output unit 162 export even gate drive signal G (48) ..., G (4N-4) and G (4N).Work as grid
During n-th clock P (N) of the counting clock signal CKV of the first counter 163 of driver GD_2, fourth beginning signal is exported
STV2L as gate drivers GD_2 the first initial signal STV2R.Fourth beginning, signal STV2L was used to close and reset grid
Second counter 164 of driver GD_1, and wake up second counter 164 of gate drivers GD_2.Gate drivers GD_
2 the second counter 164 starts counting up clock signal CKV.The counting clock signal of second counter 164 of gate drivers GD_2
CKV exports even gate drive signal G (4) again to control the second output unit 162.
The pel array that foregoing liquid crystal display and its gate drivers are applied can use conventional pixel array to improve
Aperture opening ratio.Additionally, the data driver that foregoing liquid crystal display and its gate drivers are applied can be inverted using row
(column) type of drive drives conventional pixel array to reduce power consumption.
In sum, although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, protection scope of the present invention is worked as and is defined depending on the scope of the appended claims person of defining.
Claims (19)
1. a kind of gate drivers, including：
One first output unit；
One second output unit；
One first counter, to a clock signal is counted according to one first initial signal and a polar signal with control this first
The multiple odd gates drive signals of output unit output；
One second counter, to the clock signal is counted according to one second initial signal and the polar signal with control this second
The multiple even gate drive signals of output unit output；And
One multiplexing unit, optionally to export to first counter or second counter polar signal.
2. gate drivers according to claim 1, wherein the plurality of odd gates drive signal and the plurality of even number grid
The output order of pole drive signal is controllable by the polar signal.
3. gate drivers according to claim 1, wherein when the polar signal changes into one first by a second electrical level
After level, the first rolling counters forward clock signal drives letter to control first output unit to export the plurality of odd gates
Number, after the polar signal changes into the second electrical level by first level, the second rolling counters forward clock signal is controlling
Make second output unit and export the plurality of even gate drive signal, first level is more than the second electrical level.
4. gate drivers according to claim 1, wherein first counter is according to first initial signal and the pole
The property initial signal of signal output 1 the 3rd to an another gate drivers, under another gate drivers are the gate drivers
One-level.
5. gate drivers according to claim 4, wherein second counter is according to second initial signal and the pole
Property fourth beginning signal of signal output one to an another gate drivers, under another gate drivers are the gate drivers
One-level.
6. gate drivers according to claim 1, wherein the plurality of odd gates drive signal includes a 4n-3
Gate drive signal, the plurality of even gate drive signal includes the 4n-2 gate drive signal, and n is just whole more than 1
Number, after the polar signal changes into first level by a second electrical level and a jump signal is equal to the second electrical level, this
The one rolling counters forward clock signal to control first output unit to export the 4n-3 gate drive signal, when the polarity
Signal is changed into after the second electrical level by first level and the jump signal is equal to the second electrical level, second rolling counters forward
The clock signal to control second output unit to export the 4n-2 gate drive signal, first level more than this second
Level.
7. gate drivers according to claim 1, wherein the plurality of odd gates drive signal includes a 4n-1
Gate drive signal, the plurality of even gate drive signal includes the 4n gate drive signal, and n is the positive integer more than 1,
After the polar signal changes into first level by a second electrical level and a jump signal be equal to one first level, this first meter
The rolling counters forward clock signal to control first output unit to export the 4n-1 gate drive signal, when the polar signal
Changed into after the second electrical level by first level and the jump signal be equal to first level, second rolling counters forward this when
To control second output unit to export the 4n gate drive signal, first level is more than the second electrical level to clock signal.
8. gate drivers according to claim 1, wherein first counter are counting forward, counting in reverse or jump
Count.
9. gate drivers according to claim 1, wherein second counter are counting forward, counting in reverse or jump
Count.
10. gate drivers according to claim 1, wherein first counter are counting in reverse, and this second is counted
Device is counting forward.
A kind of 11. liquid crystal displays, including：
Multiple odd-numbered scan lines；
Multiple even-line interlace lines；
One conventional pixel array, including：
One odd column pixel, is controlled by one of the plurality of odd-numbered scan lines；
One even column pixels, are controlled by one of the plurality of even-line interlace line, the odd column pixel and the even column pixels phase
It is adjacent and positioned at same a line；
One data wire, connects the odd column pixel and the even column pixels；
One data driver, connects the data wire；
One gate drivers, including：
One first output unit；
One second output unit；
One first counter, to a clock signal is counted according to one first initial signal and a polar signal with control this first
Output unit exports multiple odd gates drive signals to the plurality of odd-numbered scan lines；
One second counter, to the clock signal is counted according to one second initial signal and the polar signal with control this second
Output unit exports multiple even gate drive signals to the plurality of even-line interlace line；And
One multiplexing unit, optionally to export to first counter or second counter polar signal；
Time schedule controller, is used to provide the clock signal and the polar signal.
12. liquid crystal displays according to claim 11, the wherein time schedule controller adjust the polar signal to control this
The output of the gate drivers the plurality of odd gates drive signal of change and the plurality of even gate drive signal is sequentially.
13. liquid crystal displays according to claim 11, wherein when the polar signal changes into one by a second electrical level
After one level, the first rolling counters forward clock signal is driven with controlling first output unit to export the plurality of odd gates
Signal, after the polar signal changes into the second electrical level by first level, the second rolling counters forward clock signal with
Second output unit is controlled to export the plurality of even gate drive signal, first level is more than the second electrical level.
14. liquid crystal displays according to claim 11, also including an another gate drivers, another gate drivers
It is the next stage for being located at the gate drivers, first counter is according to first initial signal and polar signal output one the
To another gate drivers, the 3rd initial signal is used to close and reset first counter three initial signals.
15. liquid crystal displays according to claim 11, also including an another gate drivers, another gate drivers
It is the next stage for being located at the gate drivers, second counter is according to second initial signal and polar signal output one the
To another gate drivers, fourth beginning signal is used to close and reset second counter four initial signals.
16. liquid crystal displays according to claim 11, wherein the plurality of odd gates drive signal includes a 4n-3
Individual gate drive signal, the plurality of even gate drive signal includes the 4n-2 gate drive signal, and n is more than 1 just
Integer, after the polar signal changes into first level by a second electrical level and a jump signal be equal to the second electrical level, should
The first rolling counters forward clock signal to control first output unit to export the 4n-3 gate drive signal, when the pole
Property signal changed into after the second electrical level by first level and the jump signal is equal to the second electrical level, second counter counts
The number clock signals to control second output unit to export the 4n-2 gate drive signal, first level be more than this
Two level.
17. liquid crystal displays according to claim 11, wherein the plurality of odd gates drive signal includes a 4n-1
Individual gate drive signal, the plurality of even gate drive signal includes the 4n gate drive signal, and n is just whole more than 1
Number, after the polar signal changes into first level by a second electrical level and a jump signal is equal to first level, this
The one rolling counters forward clock signal to control first output unit to export the 4n-1 gate drive signal, when the polarity
Signal is changed into after the second electrical level by first level and the jump signal is equal to first level, second rolling counters forward
, to control second output unit to export the 4n gate drive signal, first level is more than second electricity for the clock signal
It is flat.
18. liquid crystal displays according to claim 11, wherein first counter are counting forward, counting in reverse or jump
Jump is counted.
19. liquid crystal displays according to claim 11, wherein second counter are counting forward, counting in reverse or jump
Jump is counted.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310353989.XA CN104376818B (en) | 2013-08-14 | 2013-08-14 | Liquid crystal display and its gate drivers |
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| CN201310353989.XA CN104376818B (en) | 2013-08-14 | 2013-08-14 | Liquid crystal display and its gate drivers |
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| CN104376818B true CN104376818B (en) | 2017-07-11 |
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| CN108806580A (en) * | 2018-06-19 | 2018-11-13 | 京东方科技集团股份有限公司 | Gate driver control circuit and its method, display device |
| CN109410867B (en) * | 2018-12-05 | 2020-10-16 | 惠科股份有限公司 | Display panel, driving method and display device |
| TWI724840B (en) * | 2020-03-26 | 2021-04-11 | 友達光電股份有限公司 | Display panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1945685A (en) * | 2006-11-02 | 2007-04-11 | 友达光电股份有限公司 | Grid electrode driving device for liquid crystal display device and its driving method |
| CN101201518A (en) * | 2006-12-11 | 2008-06-18 | 三星电子株式会社 | LCD and grid drive circuit thereof |
| CN102945657A (en) * | 2012-10-29 | 2013-02-27 | 京东方科技集团股份有限公司 | Shift register unit, grid drive circuit, array substrate and display device |
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| KR101143004B1 (en) * | 2005-06-13 | 2012-05-11 | 삼성전자주식회사 | Shift register and display device including shifter register |
| US9196205B2 (en) * | 2011-09-27 | 2015-11-24 | Sharp Kabushiki Kaisha | Scanning signal line drive circuit and display device equipped with same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1945685A (en) * | 2006-11-02 | 2007-04-11 | 友达光电股份有限公司 | Grid electrode driving device for liquid crystal display device and its driving method |
| CN101201518A (en) * | 2006-12-11 | 2008-06-18 | 三星电子株式会社 | LCD and grid drive circuit thereof |
| CN102945657A (en) * | 2012-10-29 | 2013-02-27 | 京东方科技集团股份有限公司 | Shift register unit, grid drive circuit, array substrate and display device |
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