CN104376818A - LCD and grid driver thereof - Google Patents
LCD and grid driver thereof Download PDFInfo
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- CN104376818A CN104376818A CN201310353989.XA CN201310353989A CN104376818A CN 104376818 A CN104376818 A CN 104376818A CN 201310353989 A CN201310353989 A CN 201310353989A CN 104376818 A CN104376818 A CN 104376818A
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Abstract
The invention discloses an LCD and a grid driver thereof. The grid driver comprises a first output unit, a second output unit, a first counter, a second counter and a multiplex unit. The first counter controls the first output unit to output odd number grid drive signals according to a first start signal, a polarity signal and a counting clock signal. The second counter controls the second output unit to output even number grid drive signals according to a second start signal, the polarity signal and the counting clock signal. The multiplex unit optionally outputs the polarity signal to the first counter or the second counter.
Description
Technical field
The invention relates to a kind of electronic installation, and relate to a kind of liquid crystal display and gate drivers thereof especially.
Background technology
Due to liquid crystal display (Liquid Crystal Display, LCD) device have that power consumption is low, thermal value is few, the characteristic such as lightweight and non-radiation type, therefore be used in electronic product miscellaneous, and little by little replace traditional cathode-ray tube (CRT) (Cathode Ray Tube, CRT) display device.The liquid crystal molecule of liquid crystal indicator has a kind of characteristic, is exactly can not fixed drive is constant in same polar voltages always.Otherwise the time one is of a specified duration, even if canceled by this voltage, liquid crystal molecule cannot can rotate in response to the change of electric field because of the destruction of characteristic again.Therefore just polarity of voltage must be changed at set intervals, be destroyed to avoid the characteristic of liquid crystal molecule.
Display panels common at present can be divided into normal pixels (Normal Pixel) array and upset pixel (Flip Pixel) array.The reversal mode of conventional pixel array adopts 1+2 line reversion (LineInversion), and the reversal mode overturning pel array carries out reversion (Column Inversion).But the aperture opening ratio of upset pel array is lower, and the power consumption of the reversal mode of 1+2 line reversion is larger.Therefore, how to have high aperture concurrently and namely low power consumption becomes a considerable problem simultaneously.
Summary of the invention
The invention relates to a kind of liquid crystal display and gate drivers thereof.
According to the present invention, a kind of liquid crystal display is proposed.Liquid crystal display comprises odd-numbered scan lines, even-line interlace line, normal pixels (Normal Pixel) array, data line, data driver, gate drivers and time schedule controller.Conventional pixel array comprises odd column pixel and even column pixels.Odd column pixel is controlled by odd-numbered scan lines, and even column pixels is controlled by even-line interlace line.Odd column pixel is adjacent with even column pixels and be positioned at same a line.Data line connects odd column pixel and even column pixels.Data driver connection data line.Gate drivers exports odd gates drive singal to odd-numbered scan lines according to clock signal, the first start signal and polar signal, and exports even gate drive singal to even-line interlace line according to clock signal, the second start signal and polar signal.Time schedule controller provides clock signal and polar signal.
According to the present invention, a kind of gate drivers is proposed.Gate drivers comprises the first output unit, the second output unit, the first counter, the second counter and multiplexing unit.First counter exports odd gates drive singal according to the first start signal and polar signal counting clock signal to control the first output unit.Second counter exports even gate drive singal according to the second start signal and polar signal counting clock signal to control the second output unit.Polar signal is optionally exported to the first counter or the second counter by multiplexing unit.
In order to have better understanding, preferred embodiment cited below particularly to above-mentioned and other side of the present invention, and coordinating institute's accompanying drawings, being described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates the schematic diagram into a kind of liquid crystal display according to the first embodiment.
Fig. 2 illustrates the partial schematic diagram into sweep trace, data line, odd column pixel and even column pixels.
Fig. 3 illustrates the schematic diagram into a kind of gate drivers according to the first embodiment.
Fig. 4 illustrates as a kind of signal timing diagram according to the first embodiment.
Fig. 5 illustrates as a kind of signal timing diagram according to the second embodiment.
Fig. 6 illustrates as a kind of signal timing diagram according to the 3rd embodiment.
[label declaration]
1: liquid crystal display 11: odd-numbered scan lines
12: even-line interlace line 13: conventional pixel array
14: data line 15: data driver
17: time schedule controller 131: odd column pixel
132: even column pixels 161: the first output unit
162: the second output unit 163: the first counters
164: the second counters 165: multiplexing unit
GD_1 ~ DG_i: gate drivers
G (1), G (3), G (5) ..., G (2N-1): odd gates drive singal
G (2), G (4), G (6) ..., G (2N): even gate drive singal
LD: breech lock enable signal STV: start signal
STV1R: the first start signal STV2R: the second start signal
STV1L: the three start signal STV2L: fourth beginning signal
CKV: clock signal POL: polar signal
P (1) ~ P (n): clock H: the first level
L: second electrical level JUMP: jump signal
Tf: image time Ta, Tb: period
Embodiment
First embodiment
Illustrate the schematic diagram into a kind of liquid crystal display according to the first embodiment referring to Fig. 1 and Fig. 2, Fig. 1, Fig. 2 illustrates the partial schematic diagram into sweep trace, data line, odd column pixel and even column pixels.Liquid crystal display 1 comprise odd-numbered scan lines 11, even-line interlace line 12, normal pixels (Normal Pixel) array 13, data line 14, data driver 15, gate drivers GD_1 ~ DG_i and time schedule controller 17, i be greater than 1 positive integer.Gate drivers GD_2 is the next stage of gate drivers GD_1, and gate drivers GD_3 is the next stage of gate drivers GD_2.By that analogy, gate drivers GD_i is the next stage of gate drivers GD_i-1.Conventional pixel array 13 comprises odd column pixel 131 and even column pixels 132.Odd column pixel 131 be controlled by odd-numbered scan lines 11 one of them, and even column pixels 132 be controlled by even-line interlace line 12 one of them.Adjacent and the odd column pixel 131 being positioned at same a line is connected to identical data line 14 with even column pixels 132.
Each gate drivers GD_1 ~ DG_i according to clock signal CKV, the first start signal STVR1 and polar signal POL export multiple odd gates drive singal G (1), G (3), G (5) ..., G (2N-1) to odd-numbered scan lines 11, and according to clock signal CKV, the second start signal STVR2 and polar signal POL export even gate drive singal G (2), G (4), G (6) ..., G (2N) is to even-line interlace line 12.Wherein, N be greater than 1 positive integer.Time schedule controller 17 provides breech lock enable signal LD, start signal STV, clock signal CKV and polar signal POL.Start signal STV can as the first start signal STV1R of gate drivers GD_1 and the second start signal STV2R being positioned at the first order.Aforementioned time schedule controller 17 can adjust polar signal POL with control gate driver 16 change odd gates drive singal G (1), G (3), G (5) ..., G (2N-1) and even gate drive singal G (2), G (4), G (6) ..., G (2N) output order.
Please refer to Fig. 1 and Fig. 3, Fig. 3 illustrates the schematic diagram into a kind of gate drivers according to the first embodiment.Aforementioned gate drivers GD_1 ~ DG_i in Fig. 3 be for gate drivers 16 explanation.Gate drivers 16 comprises the first output unit 161, second output unit 162, first counter 163, second counter 164 and multiplexing unit 165.First counter 163 is such as counting forward, counting in reverse or hop count, and the second counter 164 is such as counting forward, counting in reverse or hop count.
First counter 163 according to the first start signal STV1R and polar signal POL counting clock signal CKV with control the first output unit 161 export odd gates drive singal G (1), G (3), G (5) ..., G (2N-1).Second counter 164 according to the second start signal STV2R and polar signal POL counting clock signal CKV with control the second output unit 162 export even gate drive singal G (2), G (4), G (6) ..., G (2N).Polar signal POL is optionally exported the first counter 163 or the second counter 164 by multiplexing unit 165.
First counter 163 exports the gate drivers of the 3rd start signal STV1L to next stage according to the first start signal STV1R and polar signal POL, 3rd start signal STV1L in order to close and to reset the first counter 163 at the corresponding levels, and wakes the first counter 163 of next stage up.Second counter 164 exports the gate drivers of fourth beginning signal STV2L to next stage according to the second start signal STV2R and polar signal POL, fourth beginning signal STV2L in order to close and to reset the second counter 164 at the corresponding levels, and wakes the second counter 164 of the gate drivers of next stage up.
For example, first counter 163 of gate drivers GD_1 exports the 3rd start signal STV1L to gate drivers GD_2 according to the first start signal STV1R and polar signal POL, 3rd start signal STV1L in order to close and to reset first counter 163 of gate drivers GD_1, and wakes first counter 163 of gate drivers GD_2 up.Second counter 164 exports fourth beginning signal STV2L to gate drivers GD_2 according to the second start signal STV2R and polar signal POL, fourth beginning signal in order to close and to reset second counter 164 of gate drivers GD_1, and wakes second counter 164 of gate drivers GD_2 up.
Please refer to Fig. 1, Fig. 3 and Fig. 4, Fig. 4 illustrates as a kind of signal timing diagram according to the first embodiment.For example, the first counter 163 and the second counter 164 are counting forwards.After gate drivers GD_1 receives start signal STV and polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_1 exports odd gates drive singal G (1), G (3), G (5), G (7), G (9) and G (11) to control the first output unit 161.Wherein, clock signal CKV comprises the 1st clock P (1) ~ N number of clock P (N), and the first level H is greater than second electrical level L.Then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV of gate drivers GD_1 exports even gate drive singal G (2), G (4), G (6), G (8), G (10) and G (12) to control the second output unit 162.
And then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_1 exports odd gates drive singal G (13), G (15), G (17) and G (19) to control the first output unit 161.Then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV of gate drivers GD_1 exports even gate drive singal G (14), G (16), G (18), G (20) and G (22) to control the second output unit 162.
Then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV with control the first output unit 161 export odd gates drive singal G (21) ..., G (2N-3), G (2N-1) and G (1).As N number of clock P (N) of the first counter 163 counting clock signal CKV, export the first start signal STV1R of the 3rd start signal STV1L as gate drivers GD_2.3rd start signal STV1L in order to close and to reset first counter 163 of gate drivers GD_1, and wakes first counter 163 of gate drivers GD_2 up.First counter 163 of gate drivers GD_2 starts counting clock signal CKV.The first counter 163 counting clock signal CKV of gate drivers GD_2 exports odd gates drive singal G (1) to control the first output unit 161.
And then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV with control the second output unit 162 export even gate drive singal G (24) ..., G (2N-2) and G (2N).As N number of clock P (N) of the second counter 164 counting clock signal CKV of gate drivers GD_2, export the first start signal STV2R of fourth beginning signal STV2L as gate drivers GD_2.Fourth beginning signal STV2L in order to close and to reset second counter 164 of gate drivers GD_1, and wakes second counter 164 of gate drivers GD_2 up.Second counter 164 of gate drivers GD_2 starts counting clock signal CKV.The second counter 164 counting clock signal CKV of gate drivers GD_2 exports even gate drive singal G (2), G (4) and G (6) to control the second output unit 162.
Then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_2 exports odd gates drive singal G (3), G (5), G (7) and G (9) to control the first output unit 161.Then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV of gate drivers GD_2 with control the second output unit 162 export even gate drive singal G (8), G (10) ..., G (2N-4).And then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_2 with control the first output unit 161 export odd gates drive singal G (11) ..., G (2N-3) and G (2N-1).
As N number of clock P (N) of the first counter 163 counting clock signal CKV of gate drivers GD_2, export the first start signal STV1R of the 3rd start signal STV1L as gate drivers GD_3.3rd start signal STV1L in order to close and to reset first counter 163 of gate drivers GD_2, and wakes first counter 163 of gate drivers GD_3 up.Then, the second counter 164 counting clock signal CKV of gate drivers GD_2 exports even gate drive singal G (2N-2) and G (2N) to control the second output unit 162.As N number of clock P (N) of the second counter 164 counting clock signal CKV of gate drivers GD_2, export the second start signal STV2R of fourth beginning signal STV2L as gate drivers GD_3.By that analogy, can obtain the odd gates drive singal G (1) of gate drivers GD_3 ~ DG_i, G (3), G (5) ..., G (2N-1) and even gate drive singal G (2), G (4), G (6) ..., G (2N) output order.
Second embodiment
Please refer to Fig. 1, Fig. 3 and Fig. 5, Fig. 5 illustrates as a kind of signal timing diagram according to the second embodiment.Second embodiment and the first embodiment main difference part are that the first counter 163 of the second embodiment is counting in reverse, and the second counter 164 is counting forwards.After gate drivers GD_1 receives start signal STV and polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_1 exports odd gates drive singal G (2N-1), G (2N-3), G (2N-5), G (2N-7), G (2N-9) and G (2N-11) to control the first output unit 161.Then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV of gate drivers GD_1 exports even gate drive singal G (2), G (4), G (6), G (8), G (10) and G (12) to control the second output unit 162.
And then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_1 exports odd gates drive singal G (2N-13), G (2N-15), G (2N-17) and G (2N-19) to control the first output unit 161.Then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV of gate drivers GD_1 exports even gate drive singal G (14), G (16), G (18), G (20) and G (22) to control the second output unit 162.
Then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV with control the first output unit 161 export odd gates drive singal G (2N-21) ..., G (3) and G (1).As N number of clock P (N) of the first counter 163 counting clock signal CKV, export the first start signal STV1R of the 3rd start signal STV1L as gate drivers GD_2.3rd start signal STV1L in order to close and to reset first counter 163 of gate drivers GD_1, and wakes first counter 163 of gate drivers GD_2 up.First counter 163 of gate drivers GD_2 starts counting clock signal CKV.The first counter 163 counting clock signal CKV of gate drivers GD_2 exports odd gates drive singal G (2N-1) to control the first output unit 161.
And then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV with control the second output unit 162 export even gate drive singal G (24) ..., G (2N-2) and G (2N).As N number of clock P (N) of the second counter 164 counting clock signal CKV of gate drivers GD_2, export the first start signal STV2R of fourth beginning signal STV2L as gate drivers GD_2.Fourth beginning signal STV2L in order to close and to reset second counter 164 of gate drivers GD_1, and wakes second counter 164 of gate drivers GD_2 up.Second counter 164 of gate drivers GD_2 starts counting clock signal CKV.The second counter 164 counting clock signal CKV of gate drivers GD_2 exports even gate drive singal G (2) again to control the second output unit 162.
3rd embodiment
Please refer to Fig. 1, Fig. 3 and Fig. 6, Fig. 6 illustrates as a kind of signal timing diagram according to the 3rd embodiment.3rd embodiment and the first embodiment main difference part are that the first counter 163 of the 3rd embodiment and the second counter 164 are hop count.Image time Tf comprises period Ta and period Tb.Period Ta is 1/2nd of image time Tf, and period Tb is 1/2nd of image time Tf.In period Ta, jump signal JUMP equals second electrical level L.In period Tb, jump signal JUMP equals the first level H.
In period Ta, after polar signal POL is changed into the first level H by second electrical level L and jump signal JUMP equals second electrical level L, the first counter 163 counting clock signal CKV exports 4n-3 gate drive signal to control the first output unit 161.After polar signal POL changes into second electrical level L by the first level H and jump signal equals second electrical level L, the second counter 164 counting clock signal CKV exports 4n-2 gate drive signal to control the second output unit 162.Wherein, n be greater than 1 positive integer.
In period Tb, after polar signal POL changes into the first level H by second electrical level L and jump signal JUMP equals the first level H, the first counter 163 counting clock signal CKV exports 4n-1 gate drive signal to control the first output unit 161.After polar signal POL changes into second electrical level L by the first level H and jump signal JUMP equals the first level H, the second counter 164 counting clock signal CKV exports 4n gate drive signal to control the second output unit 162.
For example, in period Ta, after gate drivers GD_1 receives start signal STV and polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_1 exports odd gates drive singal G (1), G (5), G (9), G (13), G (17) and G (21) to control the first output unit 161.Then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV of gate drivers GD_1 exports even gate drive singal G (2), G (6), G (10), G (14), G (18) and G (22) to control the second output unit 162.
And then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_1 exports odd gates drive singal G (25), G (29), G (33) and G (37) to control the first output unit 161.Then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV of gate drivers GD_1 exports even gate drive singal G (26), G (30), G (34), G (38) and G (42) to control the second output unit 162.
Then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV with control the first output unit 161 export odd gates drive singal G (41) ..., G (4N-7) and G (4N-3).As N number of clock P (N) of the first counter 163 counting clock signal CKV, export the first start signal STV1R of the 3rd start signal STV1L as gate drivers GD_2.3rd start signal STV1L in order to close and to reset first counter 163 of gate drivers GD_1, and wakes first counter 163 of gate drivers GD_2 up.First counter 163 of gate drivers GD_2 starts counting clock signal CKV.The first counter 163 counting clock signal CKV of gate drivers GD_2 exports odd gates drive singal G (1) to control the first output unit 161.
And then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV with control the second output unit 162 export even gate drive singal G (46) ..., G (4N-6) and G (4N-2).As N number of clock P (N) of the second counter 164 counting clock signal CKV of gate drivers GD_2, export the first start signal STV2R of fourth beginning signal STV2L as gate drivers GD_2.Fourth beginning signal STV2L in order to close and to reset second counter 164 of gate drivers GD_1, and wakes second counter 164 of gate drivers GD_2 up.Second counter 164 of gate drivers GD_2 starts counting clock signal CKV.The second counter 164 counting clock signal CKV of gate drivers GD_2 exports even gate drive singal G (2) again to control the second output unit 162.
In period Tb, after gate drivers GD_1 receives start signal STV and polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_1 exports odd gates drive singal G (3), G (7), G (11), G (15), G (19) and G (23) to control the first output unit 161.Then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV of gate drivers GD_1 exports even gate drive singal G (4), G (8), G (12), G (16), G (20) and G (24) to control the second output unit 162.
And then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV of gate drivers GD_1 exports odd gates drive singal G (27), G (31), G (35) and G (39) to control the first output unit 161.Then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV of gate drivers GD_1 exports even gate drive singal G (28), G (32), G (36), G (40) and G (44) to control the second output unit 162.
Then, after polar signal POL changes into the first level H by second electrical level L, the first counter 163 counting clock signal CKV with control the first output unit 161 export odd gates drive singal G (43) ..., G (4N-5) and G (4N-1).As N number of clock P (N) of the first counter 163 counting clock signal CKV, export the first start signal STV1R of the 3rd start signal STV1L as gate drivers GD_2.3rd start signal STV1L in order to close and to reset first counter 163 of gate drivers GD_1, and wakes first counter 163 of gate drivers GD_2 up.First counter 163 of gate drivers GD_2 starts counting clock signal CKV.The first counter 163 counting clock signal CKV of gate drivers GD_2 exports odd gates drive singal G (3) to control the first output unit 161.
And then, after polar signal POL changes into second electrical level L by the first level H, the second counter 164 counting clock signal CKV with control the second output unit 162 export even gate drive singal G (48) ..., G (4N-4) and G (4N).As N number of clock P (N) of the first counter 163 counting clock signal CKV of gate drivers GD_2, export the first start signal STV2R of fourth beginning signal STV2L as gate drivers GD_2.Fourth beginning signal STV2L in order to close and to reset second counter 164 of gate drivers GD_1, and wakes second counter 164 of gate drivers GD_2 up.Second counter 164 of gate drivers GD_2 starts counting clock signal CKV.The second counter 164 counting clock signal CKV of gate drivers GD_2 exports even gate drive singal G (4) again to control the second output unit 162.
The pel array that foregoing liquid crystal display and gate drivers thereof are applied can adopt conventional pixel array to improve aperture opening ratio.In addition, the data driver that foregoing liquid crystal display and gate drivers thereof are applied can adopt the type of drive of row reversion (column) to drive conventional pixel array to reduce power consumption.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on the appended right person of defining.
Claims (20)
1. a gate drivers, comprising:
One first output unit;
One second output unit;
One first counter, exports multiple odd gates drive singal in order to count a clock signal according to one first start signal and a polar signal to control this first output unit;
One second counter, exports multiple even gate drive singal in order to count this clock signal according to one second start signal and this polar signal to control this second output unit; And
One multiplexing unit, in order to optionally to export this first counter or this second counter to by this polar signal.
2. gate drivers according to claim 1, wherein the output order of the plurality of odd gates drive singal and the plurality of even gate drive singal is controlled by this polar signal.
3. gate drivers according to claim 1, wherein after this polar signal changes into one first level by a second electrical level, this this clock signal of the first rolling counters forward exports the plurality of odd gates drive singal to control this first output unit, after this polar signal changes into this second electrical level by this first level, this this clock signal of the second rolling counters forward exports the plurality of even gate drive singal to control this second output unit, and this first level is greater than this second electrical level.
4. gate drivers according to claim 1, wherein this first counter exports one the 3rd another gate drivers of start signal to according to this first start signal and this polar signal, and this another gate drivers is the next stage of this gate drivers.
5. gate drivers according to claim 4, wherein this second counter exports fourth another gate drivers of beginning signal to according to this second start signal and this polar signal, and this another gate drivers is the next stage of this gate drivers.
6. gate drivers according to claim 1, wherein the plurality of odd gates drive singal comprises a 4n-3 gate drive signal, the plurality of even gate drive singal comprises a 4n-2 gate drive signal, n be greater than 1 positive integer, after this polar signal is changed into one first level by a second electrical level and a jump signal equals this second electrical level, this this clock signal of the first rolling counters forward exports this 4n-3 gate drive signal to control this first output unit, after this polar signal changes into this second electrical level by this first level and this jump signal equals this second electrical level, this this clock signal of the second rolling counters forward exports this 4n-2 gate drive signal to control this second output unit, this first level is greater than this second electrical level.
7. gate drivers according to claim 1, wherein the plurality of odd gates drive singal comprises a 4n-1 gate drive signal, the plurality of even gate drive singal comprises a 4n gate drive signal, n be greater than 1 positive integer, after this polar signal changes into one first level by a second electrical level and a jump signal equals one first level, this this clock signal of the first rolling counters forward exports this 4n-1 gate drive signal to control this first output unit, after this polar signal changes into this second electrical level by this first level and this jump signal equals this first level, this this clock signal of the second rolling counters forward exports this 4n gate drive signal to control this second output unit, this first level is greater than this second electrical level.
8. gate drivers according to claim 1, wherein this first counter is counting forward, counting in reverse or hop count.
9. gate drivers according to claim 1, wherein this second counter is counting forward, counting in reverse or hop count.
10. gate drivers according to claim 1, wherein this first counter is counting in reverse, and this second counter is counting forward.
11. 1 kinds of liquid crystal display, comprising:
Multiple odd-numbered scan lines;
Multiple even-line interlace line;
One conventional pixel array, comprising:
One odd column pixel, be controlled by the plurality of odd-numbered scan lines one of them;
One even column pixels, be controlled by the plurality of even-line interlace line one of them, this odd column pixel is adjacent with this even column pixels and be positioned at same a line;
One data line, connects this odd column pixel and this even column pixels;
One data driver, connects this data line;
One gate drivers, in order to export multiple odd gates drive singal according to a clock signal, one first start signal and a polar signal to the plurality of odd-numbered scan lines, and export multiple even gate drive singal to the plurality of even-line interlace line according to this clock signal, one second start signal and this polar signal;
Time schedule controller, in order to provide this clock signal and this polar signal.
12. liquid crystal display according to claim 11, wherein this time schedule controller adjusts this polar signal to control the output order that this gate drivers changes the plurality of odd gates drive singal and the plurality of even gate drive singal.
13. liquid crystal display according to claim 11, wherein this gate drivers comprises:
One first output unit;
One second output unit;
One first counter, exports the plurality of odd gates drive singal in order to count this clock signal according to this first start signal and this polar signal to control this first output unit;
One second counter, exports the plurality of even gate drive singal in order to count this clock signal according to this second start signal and this polar signal to control this second output unit; And
One multiplexing unit, in order to optionally to export this first counter or this second counter to by this polar signal.
14. liquid crystal display according to claim 13, wherein after this polar signal changes into one first level by a second electrical level, this this clock signal of the first rolling counters forward exports the plurality of odd gates drive singal to control this first output unit, after this polar signal changes into this second electrical level by this first level, this this clock signal of the second rolling counters forward exports the plurality of even gate drive singal to control this second output unit, and this first level is greater than this second electrical level.
15. liquid crystal display according to claim 13, also comprise another gate drivers, this another gate drivers is the next stage being positioned at this gate drivers, this first counter exports one the 3rd start signal to this another gate drivers according to this first start signal and this polar signal, and the 3rd start signal is in order to close and to reset this first counter.
16. liquid crystal display according to claim 13, also comprise another gate drivers, this another gate drivers is the next stage being positioned at this gate drivers, this second counter exports fourth beginning signal to this another gate drivers according to this second start signal and this polar signal, and this fourth beginning signal is in order to close and to reset this second counter.
17. liquid crystal display according to claim 13, wherein the plurality of odd gates drive singal comprises a 4n-3 gate drive signal, the plurality of even gate drive singal comprises a 4n-2 gate drive signal, n be greater than 1 positive integer, after this polar signal is changed into one first level by a second electrical level and a jump signal equals this second electrical level, this this clock signal of the first rolling counters forward exports this 4n-3 gate drive signal to control this first output unit, after this polar signal changes into this second electrical level by this first level and this jump signal equals this second electrical level, this this clock signal of the second rolling counters forward exports this 4n-2 gate drive signal to control this second output unit, this first level is greater than this second electrical level.
18. liquid crystal display according to claim 13, wherein the plurality of odd gates drive singal comprises a 4n-1 gate drive signal, the plurality of even gate drive singal comprises a 4n gate drive signal, n be greater than 1 positive integer, after this polar signal changes into one first level by a second electrical level and a jump signal equals this first level, this this clock signal of the first rolling counters forward exports this 4n-1 gate drive signal to control this first output unit, after this polar signal changes into this second electrical level by this first level and this jump signal equals this first level, this this clock signal of the second rolling counters forward exports this 4n gate drive signal to control this second output unit, this first level is greater than this second electrical level.
19. liquid crystal display according to claim 11, wherein this first counter is counting forward, counting in reverse or hop count.
20. liquid crystal display according to claim 11, wherein this second counter is counting forward, counting in reverse or hop count.
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| CN109410867A (en) * | 2018-12-05 | 2019-03-01 | 惠科股份有限公司 | Display panel, driving method and display device |
| CN112164367A (en) * | 2020-03-26 | 2021-01-01 | 友达光电股份有限公司 | Display panel |
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| CN104376818B (en) | 2017-07-11 |
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