CN102376274B - Liquid crystal display - Google Patents
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- CN102376274B CN102376274B CN 201010247160 CN201010247160A CN102376274B CN 102376274 B CN102376274 B CN 102376274B CN 201010247160 CN201010247160 CN 201010247160 CN 201010247160 A CN201010247160 A CN 201010247160A CN 102376274 B CN102376274 B CN 102376274B
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 36
- 230000000630 rising effect Effects 0.000 claims description 23
- 230000008771 sex reversal Effects 0.000 claims description 17
- 238000009413 insulation Methods 0.000 claims description 4
- 239000010409 thin film Substances 0.000 description 25
- 238000000034 method Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
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Abstract
The invention discloses a liquid crystal display which comprises a liquid crystal panel, a display control circuit and a data driven circuit, wherein the display control circuit is used for receiving an image signal and generating a time sequence signal and a data signal according to the image signal; the data driven circuit is used for receiving the time sequence signal and the data signal so as to form a plurality of data voltages; and before the data voltage for driving a non-polar inversed pixel is pre-output, the data driven circuit is used for adjusting the voltages of a plurality of data wires to be preset voltage, so that the electric charge quantity stored by a polar inversed pixel is the same as that stored by the non-polar inversed pixel for the same-gram scale frame. The liquid crystal display can be used for improving the phenomenon that the frame flashes when the image of the liquid crystal display is displayed and has a better display effect.
Description
Technical field
The present invention relates to a kind of LCD.
Background technology
The liquid crystal molecule of LCD has such specific character: remain unchanged for a long time if be loaded into the direction of an electric field at liquid crystal layer two ends, the characteristic of liquid crystal molecule just can be destroyed so, namely can't rotate to form different GTGs in response to the variation of electric field again.Therefore, LCD just must change direction of an electric field so that liquid crystal molecule reverses at regular intervals, thereby avoids the characteristic of liquid crystal molecule to be destroyed.Common inversion driving mode has at present: frame counter-rotating driving (Frame Inversion), row reverse and drive (Column Inversion), row reverses to drive (Line/Row Inversion) and put counter-rotating and drives (Dot Inversion).Wherein, point counter-rotating drives and comprises that again single line point counter-rotating drives (1-line dot inversion) and two-wire point counter-rotating driving type of drive such as (2-line dot inversion), can make that as the LCD of type of drive the power consumption of LCD is less and its film flicker phenomenon is less with the driving of reversing of two-wire point.
So-called two-wire point counter-rotating drives, the polarity that is the capable pixel institute on-load voltage with each same column during 4i+2 is capable of the 4i+1 of LCD is consistent, the polarity of the capable pixel institute on-load voltage with each same column during 4i+4 is capable of 4i+3 is consistent, and the polarity of the capable pixel institute on-load voltage with each same column during 4i+3 is capable of 4i+2 is opposite, and the polarity of pixel institute of the same delegation on-load voltages of adjacent two row is opposite arbitrarily.Wherein, i is the integer more than or equal to zero.The polarity of each pixel institute on-load voltage is reversed frame by frame.
Yet for 4i+1 and the capable pixel of 4i+3, its on-load voltage is the data voltage that little by little changes to required polarity, and therefore the duration of charging that needs is longer.And for the pixel that 4i+2 is capable and 4i+4 is capable, the polarity of its on-load voltage is identical with the polarity of previous row respective pixel, but then reaches required data voltage within a short period of time.Therefore, when the same row pixel that 4i+1 is capable and 4i+2 is capable adds identical data voltage in advance, this 4i+1 is capable, and in fact the stored charge amount is different with the capable pixel of this 4i+2, and then causes the brightness that this 4i+1 is capable and the capable pixel of this 4i+2 is shown different.So when this LCD showed same grey menu, bright line and concealed wire can appear in its shown image, the user will see more serious film flicker phenomenon.
Equally, adopt the row counter-rotating to drive and other multi-thread some counter-rotating drives and also has mentioned problem in the above-mentioned two-wire point counter-rotating driving.
Summary of the invention
In order to solve the film flicker phenomenon that occurs when LCD shows image in the prior art, be necessary to provide a kind of LCD that can improve film flicker phenomenon when showing image.
A kind of LCD, it comprises liquid crystal panel, display control circuit and data drive circuit.This liquid crystal panel comprises the multi-strip scanning line, many data lines that intersect with the insulation of this multi-strip scanning line and a plurality of pixels that defined by this multi-strip scanning line and these many data lines.This display control circuit receives picture signal and generates clock signal and data-signal according to this picture signal.This data drive circuit receives this clock signal and this data-signal to form a plurality of data voltages.This data drive circuit is before the data voltage of the pixel of the nonpolarity counter-rotating row of pre-output driving, voltage on these many data lines is all adjusted to predetermined voltage, so that for same grey menu, the pixel stored charge amount of this reversal of poles row is considered as identical with the pixel stored charge amount of this nonpolarity counter-rotating row.
Compared to prior art, because the data drive circuit of LCD of the present invention is before the data voltage of the pixel of the nonpolarity counter-rotating row of pre-output, voltage on these many data lines is all adjusted to predetermined voltage, therefore, the data voltage of the pixel of the corresponding nonpolarity counter-rotating row that these many data lines transmit need little by little change to the data voltage of required polarity from this predetermined voltage, and then make for same grey menu, the pixel stored charge amount difference of the pixel of reversal of poles row and nonpolarity counter-rotating row reduces, thus phenomenon of picture flicker when improving this LCD and showing image.
Description of drawings
Fig. 1 is the structural representation of LCD first embodiment of the present invention.
Fig. 2 is LCD shown in Figure 1 when showing a frame picture, the synoptic diagram of its pixel institute on-load voltage polarity.
Fig. 3 is the driving sequential chart of LCD shown in Figure 1.
Fig. 4 is the structural representation of LCD second embodiment of the present invention.
Fig. 5 is the synoptic diagram of the look-up table of LCD shown in Figure 4.
Fig. 6 is the process flow diagram that LCD shown in Figure 4 is improved the driving method of film flicker phenomenon when showing image.
Fig. 7 is the driving sequential chart of the refreshing frequency of LCD shown in Figure 4 when being 60HZ.
Fig. 8 is the driving sequential chart of the refreshing frequency of LCD shown in Figure 4 when being 75HZ.
Fig. 9 is the driving sequential chart of LCD the 3rd embodiment of the present invention.
Figure 10 is the oscillogram of the load control signal of another embodiment of LCD shown in Figure 1.
Figure 11 is the oscillogram of the load control signal of another embodiment of LCD shown in Figure 4.
Figure 12 is the driving sequential chart of another embodiment of LCD shown in Figure 4.
Figure 13 is the driving sequential chart of the another embodiment of LCD shown in Figure 4.
The main element symbol description
LCD 100,200
Public voltage generating circuit 18,28
Sweep trace G
1～G
L, G '
1～G '
L
Data line D
1～D
M, D '
1～D '
M
Pixel 127,227
Thin film transistor (TFT) 121,221
Pixel electrode 123,223
Public electrode 125,225
Grid g, g '
Source electrode s, s '
Drain electrode d, d '
Storer 220
Sequential control circuit 130,230
Look-up table 222
Embodiment
Main thought of the present invention is the load control signal that outputs to data drive circuit by the display control circuit of adjusting LCD, this load control signal not only can be controlled the data voltage that data drive circuit output drives each row pixel, the more important thing is that this load control circuit can also be controlled data drive circuit and adjust voltage on these many data lines.Particularly, this load control signal has a plurality of first and triggers sign and a plurality of second triggering sign, these a plurality of first triggerings indicate and comprise a plurality of first output property triggerings signs of exporting the data voltage of the pixel that drives nonpolarity counter-rotating row (explanation to the reversal of poles row sees also described in bright LCD first embodiment of this law) for the trigger data driving circuit, indicate with the second output property triggering of the data voltage of a plurality of pixels for trigger data driving circuit output driving stage sex reversal capable (explanation to nonpolarity counter-rotating row sees also described in bright LCD first embodiment of this law), this second triggering indicates and comprises that a plurality of first property adjusted triggerings indicate, these a plurality of first property adjusted triggerings indicate and were used for before this data drive circuit is exported the data voltage of the pixel that drives nonpolarity counter-rotating row in advance, trigger the voltage of this data drive circuit on will these many data lines and all adjust to this predetermined voltage.Wherein, this first property adjusted triggering indicate trigger the voltage of this data drive circuit on will this many data lines and all adjust to this predetermined voltage after, this first output property triggering indicates and just triggers the data voltage that this data drive circuit is exported the pixel of the nonpolarity counter-rotating row of driving.
Because the data drive circuit of LCD is before the data voltage of pre-output for the pixel that drives nonpolarity counter-rotating row, voltage on these many data lines is all adjusted to same predetermined voltage, namely for the pixel of nonpolarity counter-rotating row, its charging voltage also as the charging voltage of the pixel of reversal of poles row, has the process that gradually changes.Therefore, the charging voltage of the pixel of corresponding nonpolarity counter-rotating row is reduced, and then make that for same grey menu, the pixel stored charge amount difference of reversal of poles row and nonpolarity counter-rotating row reduces, thereby phenomenon of picture flicker when improving this LCD demonstration image.
Further, this second triggering indicates and comprises that further a plurality of second property adjusted triggerings indicate, each second output property triggering indicates respectively, and corresponding one second property adjusted triggering indicates, this a plurality of second property adjusted triggering indicates and was used for before this data drive circuit is exported the data voltage of the capable pixel of driving stage sex reversal in advance, trigger the voltage of this data drive circuit on will these many data lines and all adjust to this predetermined voltage, wherein, this second property adjusted triggering indicate trigger the voltage of this data drive circuit on will this many data lines and all adjust to this predetermined voltage after, this second output property triggering indicates and just triggers the data voltage that this data drive circuit is exported the capable pixel of driving stage sex reversal.That is, this data drive circuit also can all be adjusted to this predetermined voltage with the voltage on these many data lines before the data voltage of the capable pixel of pre-output driving stage sex reversal.
Because the data drive circuit of LCD is before the data voltage of output for the pixel of the capable and nonpolarity counter-rotating row of driving stage sex reversal, all the voltage on many data lines is all adjusted to same predetermined voltage, therefore, the Changing Pattern of the charging voltage of the pixel of the pixel of reversal of poles row and nonpolarity counter-rotating row is basic identical.Thereby, make that for same grey menu, the pixel stored charge amount difference of reversal of poles row and nonpolarity counter-rotating row reduces, and then phenomenon of picture flicker when improving this LCD demonstration image.
About detail of the present invention, see also each following embodiment.
See also Fig. 1, it is the structural representation of LCD first embodiment of the present invention.This LCD 100 comprises the sweep trace G that a display control circuit 10, a liquid crystal panel 12, scan driving circuit 14, a data drive circuit 16, a public voltage generating circuit 18, multirow are parallel to each other
1～G
L(L is natural number, and L＞1), multiple row is parallel to each other and respectively with this fine scanning line G
1～G
LThe data line D that insulation is intersected
1～D
M(M is natural number, and M＞1).This fine scanning line G
1～G
LWith this multi-column data line D
1～D
MThis liquid crystal panel 12 is divided into a plurality of pixels 127.Each pixel 127 comprises a thin film transistor (TFT) 121, a pixel electrode 123, one and the public electrode 125 that is oppositely arranged of this pixel electrode 123 and be sandwiched in liquid crystal molecule between this pixel electrode 123 and this public electrode 125.The grid g of this thin film transistor (TFT) 121 and this sweep trace G
LConnect the source electrode s of this thin film transistor (TFT) 121 and this data line D
MConnect, the drain electrode d of this thin film transistor (TFT) 121 is connected with this pixel electrode 123, and the public electrode 125 of these a plurality of pixels 127 is shared.
This display control circuit 10 comprises a sequential control circuit 130.This sequential control circuit 130 is used for receiving outside view data and pixel clock signal CLK, according to the corresponding a plurality of data-signals (as: RGB DATA signal) that produce of this view data, one first control signal CONT1, and the second control signal CONT2, and according to corresponding one first load control signal LD1 and the one second load control signal LD2 of producing of this pixel clock signal CLK, and with this first control signal CONT1, this first load control signal LD1, this second load control signal LD2 and this data-signal offer this data drive circuit 16, and this second control signal CONT2 is offered this scan drive circuit 14.This pixel clock signal CLK is the square-wave pulse signal that changes in the cycle, and supposes that its cycle is T.This pixel clock signal CLK is used for this data-signal of control and is transferred to liquid crystal panel 12 in order.The frequency of this pixel clock signal CLK is relevant with the mode of operation of this liquid crystal panel 12, and the resolution of this liquid crystal panel 12 is more high, and the frequency of this pixel clock signal CLK is also more high.In delegation, the quantity of the pixel 127 that has in the number of the period T of this pixel clock signal CLK and these liquid crystal panel 12 delegation equates.This first load control signal LD1 and this second load control signal LD2 are square-wave pulse signal.
This scan drive circuit 14 receives this second control signal CONT2, and corresponding output scanning voltage, and this scanning voltage is loaded on the grid g of corresponding thin film transistor (TFT) 101 by this fine scanning line GL, and corresponding thin film transistor (TFT) 121 is opened.
This data drive circuit 16 receives this first control signal CONT1, this first load control signal LD1, this second load control signal LD2 and this a plurality of data-signals, and these a plurality of data-signals of conversion are corresponding data voltage.Wherein, this first load control signal LD1 and this second load control signal LD2 are used for outputing to as this data drive circuit 16 trigger pip of the data voltage of each row pixel 127.When this data drive circuit 16 received this first load signal LD1 or this second load control signal LD2, it exported this data voltage, and this data voltage is loaded on the source electrode s of corresponding thin film transistor (TFT) 121 by these many data line DM.If this moment, this thin film transistor (TFT) 121 was in conducting state, then this data voltage can be sent to the drain electrode d of this thin film transistor (TFT) 121 and be loaded on this pixel electrode 123.This public voltage generating circuit 18 is used for providing a common electric voltage (Vcom) to this public electrode 125.Therefore, can produce an electric field between this pixel electrode 123 and this public electrode 125 with the rotation of control liquid crystal molecule, thereby make this liquid crystal panel 12 show image.In order to protect liquid crystal molecule can not be damaged, the direction of this electric field needs cyclical variation.
Describe for convenient, when the data voltage that is loaded into this pixel electrode 123 is higher than the common electric voltage of its public electrode 125, defining the voltage that this pixel 127 loads is positive polarity voltage, and the data voltage that definition is loaded into this pixel electrode 123 is the positive polarity data voltage; When the data voltage that is loaded into this pixel electrode 123 was lower than the common electric voltage of its public electrode 125, defining the voltage that this pixel 127 loads was reverse voltage, and the data voltage that definition is loaded into this pixel electrode 123 is the negative polarity data voltage.When the absolute value of positive polarity voltage equated with the absolute value of reverse voltage, this pixel 127 showed same gray level.
See also Fig. 2, when it is this LCD 100 demonstrations one frame picture, the synoptic diagram of 127 on-load voltage polarity of its pixel.This LCD 100 adopts the work of two-wire point inversion driving mode, namely the polarity of capable 127 on-load voltages of pixel with each same column during 4i+2 is capable of the 4i+1 of this LCD 100 is consistent, the polarity of capable 127 on-load voltages of pixel with each same column during 4i+4 is capable of 4i+3 is consistent, and the polarity of capable 127 on-load voltages of pixel with each same column during 4i+3 is capable of 4i+2 is opposite, and the polarity of 127 on-load voltages of same delegation pixel of adjacent two row is opposite arbitrarily.Wherein, i is the integer more than or equal to zero.The polarity of 127 on-load voltages of each pixel is reversed frame by frame.
When this LCD 100 shows a frame picture, except the 1st row pixel 127 of this liquid crystal panel 12, to offer current line opposite with the polarity of the data voltage of the same row pixel 127 of previous row when this data drive circuit 26, then defines current behavior reversal of poles row; If to offer current line identical with the polarity of the data voltage of the same row pixel 127 of previous row when this data drive circuit 26, then define the nonpolarity counter-rotating row of current behavior.
Further, for the 1st row pixel 127 of this liquid crystal panel 12, when this liquid crystal panel 12 shows the 1st frame picture, before this data drive circuit 16 output data voltages to the 1 row pixel 127, because these many data line D
MOn on-load voltage not, therefore, when the data voltage of corresponding the 1st row pixel 127 of these data drive circuit 16 outputs to these many data line D
MThe time, this data voltage is at these many data line D
MOn need to rise to target data voltage gradually from 0 volt, therefore, the 1st behavior reversal of poles row of corresponding the 1st frame display frame of definition; When this liquid crystal panel 12 shows that (j is natural number to the j frame, and j＞1) during picture, if last 1 row of corresponding j-1 frame picture is identical with the polarity of 127 loaded data voltages of same row pixel of the 1st row of corresponding j frame picture, then define the nonpolarity counter-rotating row of the 1st behavior of corresponding j frame picture, on the contrary, then define the 1st behavior reversal of poles row of corresponding j frame picture.
Below in conjunction with the concept of reversal of poles row and nonpolarity counter-rotating row, at length introduce this first load control signal LD1 and this second load control signal LD2.This sequential control circuit 130 is according to the drive pattern of LCD and corresponding this first load control signal LD1 and this second load control signal LD2 of producing of this pixel clock signal CLK that receives thereof.This first load control signal LD1 is used for the data voltage of the capable pixel 127 of the corresponding driving stage sex reversal of these data drive circuit 16 outputs of control.This second load control signal LD2 not only is used for the corresponding data voltage that drives the pixel 127 of nonpolarity counter-rotating row of these data drive circuit 16 outputs of control, also be used for this data drive circuit 16 output data voltages after the pixel 127 of reversal of poles row and at the output data voltage before the pixel 127 of nonpolarity counter-rotating row, controlling this data drive circuit 16 should many data line D
MOn voltage all adjust to same predetermined voltage.This predetermined voltage should satisfy following requirement: when the corresponding positive polarity data voltage that drives the pixel 127 of nonpolarity counter-rotating row of these data drive circuit 16 outputs arrives these many data line D
MThe time, these many data line D
MOn voltage be elevated to target data voltage gradually by this predetermined voltage; On the contrary, the negative polarity data voltage that drives the pixel 127 of nonpolarity counter-rotating row when these data drive circuit 16 output correspondences arrives these many data line D
MThe time, these many data line D
MOn voltage drop to target data voltage gradually by this predetermined voltage.And then, make the data voltage of the pixel 127 that corresponding driving stage sex reversal is capable at these many data line D
MOn the data voltage of Changing Pattern and the pixel 127 of the nonpolarity counter-rotating row of corresponding driving at these many data line D
MOn the difference of Changing Pattern reduce.Correspondingly, the pixel 127 of this reversal of poles row reduces with the difference of the pixel 127 stored charge amounts of this nonpolarity counter-rotating row.Wherein, the span of this predetermined voltage is: more than or equal to the difference of common electric voltage and 2 volts and less than common electric voltage and 2 volts of sums.
Further, the negative edge of the high level pulse of this first load control signal LD1 preferably indicates as the first second output property triggering that triggers in indicating, and it is for the data voltage of the pixel 127 that triggers the corresponding reversal of poles row of these data drive circuit 16 outputs.The rising edge of the high level pulse of this second load control signal LD2 preferably triggers first property adjusted triggering that indicates as second and indicates, and it is used for triggering this data drive circuit 16 and begins to adjust these many data line D
MOn the size of voltage, and the size of the width of its high level pulse is this data drive circuit 16 corresponding these many data line D of adjustment
MOn time of voltage; The negative edge of the high level pulse of this second load control signal LD2 preferably indicates as the first first output property triggering that triggers in indicating, and it is used for triggering this data drive circuit 16 and stops to adjust these many data line D
MOn voltage, and trigger the data voltage of the pixel 127 of the corresponding nonpolarity counter-rotating row of this data drive circuit 16 outputs.
Particularly, when the high level pulse of this first load control signal LD1 that receives when this data drive circuit 16 is in negative edge, this data drive circuit 16 output data voltages and by these many data line D
MBe loaded into corresponding pixel electrode 123.At this moment, the pixel electrode 123 of loading data voltage is the pixel electrode 123 of reversal of poles row.When the high level pulse of this second load control signal LD2 that receives when this data drive circuit 16 was in rising edge, this data drive circuit 16 began to adjust these many data line D
MOn voltage, and the high level pulse of this second load control signal LD2 negative edge when arriving, should many data line D
MOn voltage all adjust to this predetermined voltage.The adjustment mode can be: will every two adjacent data line D
MBe divided into one group, 16 controls of this data drive circuit are with two data line D in every group
MShort circuit is because two adjacent data line D
MThe polarity of last loaded data voltage is opposite, therefore, shares by electric charge, makes all data line D
MOn voltage all be adjusted to this predetermined voltage.When the high level pulse of this second load control signal LD2 that receives when this data drive circuit 16 is in negative edge, the data line D of these data drive circuit 16 control phase short circuits
MDisconnect each other, and these many data line D of control
MWith the corresponding connection of a plurality of output pin (not shown) of this data drive circuit 16, thereby this data drive circuit 26 begins to arrive these many data line D by the data voltage that these a plurality of output pin outputs are used for the pixel 127 of the nonpolarity counter-rotating row of driving
M, and be loaded into corresponding pixel electrode 123 by this thin film transistor (TFT) 121.At this moment, the pixel electrode 123 of loading data voltage is the pixel electrode 123 of nonpolarity counter-rotating row.
In addition, because in any delegation, the quantity of the pixel 127 that has in the number of cycles of this pixel clock signal CLK and these liquid crystal panel 12 delegation equates, and this first, second load control signal LD1, LD2 are the pulse signal of the data voltage of the pixel 127 of these data drive circuit 16 corresponding reversal of poles row of output of control and nonpolarity counter-rotating row, therefore, the width between any two adjacent high level pulses of each load control signal LD1, LD2 all is the integral multiple of the period T of this pixel clock signal CLK.Correspondingly, according to the size of the period T of this pixel clock signal, the width of the width of per two adjacent high level pulses of the width of the high level pulse of this first, second load control signal LD1, LD2, this first load control signal LD1 and per two adjacent high level pulses of this second load control signal LD2 all is adopted as what of period T of this pixel clock signal and doubly represents.
This sequential control circuit 130 is according to the width of per two adjacent high level pulses of the width of per two adjacent high level pulses of the width of the high level pulse of cycle of this pixel clock signal CLK, this first, second load control signal LD1, LD2, this first load control signal LD1 and this second load control signal LD2, and then corresponding this first, second load control signal LD1, the LD2 of producing.
Type of drive for the counter-rotating of two-wire point, this sequential control circuit 130 is given this data drive circuit 16 by this second load control signal of output LD2, and then make this data drive circuit 16 under the control of the high level pulse of this second load control signal LD2, can either realize these many data line D
MOn voltage adjust, also can realize exporting the data voltage of the pixel 127 that drives nonpolarity counter-rotating row.Further, for other not mentioned in this manual inversion driving mode (inversion driving mode that is limited to the branch that reversal of poles row and nonpolarity counter-rotating row are arranged), inner parameter by this sequential control circuit 130 of artificial adjustment, can make this sequential control circuit 130 produce the second corresponding load control signal LD2 of inversion driving mode that adopts with this LCD 100, this data drive circuit 16 can either be realized equally to these many data line D under the control of this second corresponding load control signal LD2
MOn voltage adjust, also can realize exporting the data voltage of the pixel 127 that drives nonpolarity counter-rotating row.And then when this LCD 100 showed same grey menu, each row pixel 127 stored charge amount was basic identical.Thereby, reduce the film flicker phenomenon of this LCD 100.
Please consult Fig. 3 simultaneously, it is the driving sequential chart of this LCD 100.Show that with this LCD 100 same grey menu is example, its principle of work is as follows:
This public voltage generating circuit 18 continues outputting common voltage to this public electrode 125.
The sequential control circuit 130 of this display control circuit 10 receives outside picture signal and pixel clock signal CLK, and a plurality of data-signals of corresponding output, the first control signal CONT1, the second control signal CONT2, the first load control signal LD1 and the second load control signal LD2.Wherein, the width of the high level pulse of this second load control signal LD2 is preferably 30T.Because the size of the width of the high level pulse of this first load control signal LD1 is adjusted this data line D for this data drive circuit 16
MOn voltage and inoperative, therefore, the width of the high level pulse of this first load control signal LD1 and identical the getting final product of width of the high level pulse of load control signal of the prior art.
This scan drive circuit 14 receives this second control signal CONT2, and corresponding output scanning voltage, and this scanning voltage is by this fine scanning line G
LBe loaded on the grid g of corresponding thin film transistor (TFT) 101, corresponding thin film transistor (TFT) 121 is opened.
This data drive circuit 16 receives this first control signal CONT1, this first load control signal LD1 and this second load control signal LD2 and this a plurality of data-signals, and changes the data voltage that these a plurality of data-signals are correspondence.What receive when this data drive circuit 16 is the high level pulse of this first load control signal LD1 and this first load control signal LD1 when being in negative edge, and these data drive circuit 16 outputs are used for the data voltage of the capable pixel 127 of driving stage sex reversal to these many data line D
M, these many data line D
MOn voltage begin to taper to target data voltage.Wherein, these many data line D
MOn a certain moment of voltage in the process that gradually changes, the scanning voltage of this scan drive circuit 14 output gate turn-on is given corresponding sweep trace G
L, make and this sweep trace G
LThin film transistor (TFT) 121 conductings that are connected, then these many data line D
MOn data voltage can be sent to the drain electrode d of this thin film transistor (TFT) 121 and be loaded on this pixel electrode 123.After the data voltage loaded on this pixel electrode 123, the scanning voltage that these scan drive circuit 14 output grids end is given this corresponding sweep trace G
L, make and this sweep trace G
LThe thin film transistor (TFT) 121 that is connected ends.What receive when this data drive circuit 16 is the high level pulse of this second load control signal LD2 and this second load control signal LD2 when being in rising edge, and this data drive circuit 16 begins to adjust these many data line D
MOn voltage, and when the high level pulse of this second load control signal LD2 is in negative edge, make these many data line D
MOn voltage all reach same predetermined voltage, and when the high level pulse of this second load control signal LD2 is in negative edge, these data drive circuit 16 outputs are used for driving the data voltage of pixel 127 of corresponding nonpolarity counter-rotating row to these many data line D
M, these many data line D
MOn voltage taper to required target data voltage equally.If this moment, this thin film transistor (TFT) 121 was in open mode, then this data voltage can be sent to the drain electrode d of this thin film transistor (TFT) 121 and be loaded on this pixel electrode 123, thereby this liquid crystal panel 12 realizes that picture shows.Wherein, by the waveform of the data voltage among Fig. 3 as can be seen, after a certain pixel 127 of reversal of poles row is applied in the data voltage of positive polarity, apply the data line D of pixel 127 corresponding connections of the data voltage of positive polarity with this
MOn voltage at first drop to this predetermined voltage, when the pixel 127 of next nonpolarity counter-rotating row is recharged, begin to rise to target data voltage then again.On the contrary, this data line D
MOn voltage at first rise to this predetermined voltage, and then drop to target data voltage.
Because the data drive circuit 16 of this LCD 100 is after output is used for the data voltage of the capable pixel 127 of driving stage sex reversal, and be used for driving in output before the data voltage of pixel 127 of nonpolarity counter-rotating row, should many data line D
MOn voltage all adjust to same predetermined voltage, namely for the pixel 127 of nonpolarity counter-rotating row, its charging voltage also as the charging voltage of the pixel 127 of reversal of poles row, has the process that gradually changes.Therefore, the charging voltage of the pixel 127 of corresponding nonpolarity counter-rotating row is reduced, and then make that for same grey menu, the pixel 127 stored charge amount differences of reversal of poles row and nonpolarity counter-rotating row reduce, thereby phenomenon of picture flicker when improving these LCD 100 demonstration images.
Yet, in the above-described embodiment, though scintillation is improved to a great extent, still still have the problem of flicker.Above-mentioned LCD 100 is to utilize the high level pulse of the second load control signal LD2 to realize discharging and recharging of data voltage, and the width of the high level pulse of this second load control signal LD2 is fixed, but the frame rate of external image signal and disunity.For different frame rates, the cycle of this pixel clock signal CLK is different, and for different frame rates, these many data line D
MOn the speed that discharges and recharges of data voltage can be different.Wherein, along with the increase of frame rate, these many data line D
MOn voltage to be charged to the speed of target data voltage slack-off, and also slack-off by two data line short circuits being made target data voltage discharge into the speed of this predetermined voltage.Therefore, if for different frame rates, the width of the high level pulse of the second load control signal LD2 of these sequential control circuit 130 outputs is all identical, for the picture signal of higher frame rate, and the data line D of the mutual short circuit that this data drive circuit 16 is controlled
MOn voltage when not reaching this predetermined voltage, just finish discharge.Correspondingly, the pixel 127 of this reversal of poles row still exists than evident difference with the charging voltage of the pixel 127 of this nonpolarity counter-rotating row, and then for the picture signal of different frame rates, the user can see that still there is phenomenon of picture flicker in this LCD 100.Particularly the developing direction of following LCD will trend towards 120HZ and 60HZ, even one LCD have two or more refreshing frequencys, as, adopt moving estimation/motion compensation (Motion Estimate/Motion Compensation, ME/MC) LCD of technology, the user is just easier to see phenomenon of picture flicker.
In order to make that this LCD 100 can both have good display for the picture signal of different frame rates, reduce phenomenon of picture flicker, the embodiment of described LCD below the present invention further proposes.
See also Fig. 4, it is the structural representation of LCD second embodiment of the present invention.This LCD 200 comprises the sweep trace G ' that a display control circuit 20, a liquid crystal panel 22, scan driving circuit 24, a data drive circuit 26, a public voltage generating circuit 28, multirow are parallel to each other
1～G '
L(L is natural number, and L＞1), multiple row is parallel to each other and respectively with this fine scanning line G '
1～G '
LThe data line D ' that insulation is intersected
1～D '
M(M is natural number, and M＞1).This fine scanning line G '
1～G '
LWith this multi-column data line D '
1～D '
MThis liquid crystal panel 22 is divided into a plurality of pixels 227.Each pixel 227 comprises a thin film transistor (TFT) 221, a pixel electrode 223, one and the public electrode 225 that is oppositely arranged of this pixel electrode 223 and be sandwiched in liquid crystal molecule between this pixel electrode 223 and this public electrode 225.The grid g ' of this thin film transistor (TFT) 221 and this sweep trace G '
LConnect the source electrode s ' of this thin film transistor (TFT) 221 and this data line D '
MConnect, the drain electrode d ' of this thin film transistor (TFT) 221 is connected with this pixel electrode 223, and the public electrode 225 of these a plurality of pixels 227 is shared.
Wherein, this liquid crystal panel 20, this scan drive circuit 24, this data drive circuit 26, this public voltage generating circuit 28, this fine scanning line G '
1～G '
L, this multi-column data line D '
1～D '
MAnd the structure of this pixel 227 and function all liquid crystal panel 10, scan drive circuit 14, data drive circuit 16, public voltage generating circuit 18, the fine scanning line G of the liquid of corresponding and first embodiment
1～G
L, multi-column data line D
1～D
MAnd the structure of pixel 127 is identical with function, and therefore, structure and function about said modules repeat no more herein.
The display control circuit 20 of this LCD 200 further comprises a frequency detector 210 and a storer 220.This storer 220 comprises a look-up table 222, and this look-up table 222 stores different frame rates, reaches the width of the high level pulse of the first load signal LD1 ' corresponding with each frame rate and the second load signal LD2 '.Wherein, the width of the high level pulse of this first load signal LD1 ' and the second load signal LD2 ' adopts the multiple in the cycle of pixel clock signal CLK ' to represent.This frequency detector 210 is used for the frame rate of the external image signal that this display control circuit 20 of detecting receives, and the corresponding frame rate that will detect is exported to this sequential control circuit 230.This sequential control circuit 230 is according to the frame rate that receives, correspondence is searched the width of the high level pulse of first, second load signal LD1 ', LD2 ' corresponding with the frame rate that receives in this look-up table 222, and according to the width between per two adjacent high level pulses of the size in cycle of corresponding pixel clock signal CLK ', this first load signal LD1 ', and per two adjacent high level pulses of this second load signal LD2 ' between width, corresponding this first load control signal LD1 ' and this second load control signal LD2 ' of generating.Wherein, the negative edge of the high level pulse of this first load control signal LD1 ' preferably indicates as the first second output property triggering that triggers in indicating; The negative edge of the high level pulse of this second load control signal LD2 ' preferably triggers the first output property triggering that indicates as first and indicates; The rising edge of the high level pulse of this second load control signal LD2 ' preferably triggers first property adjusted triggering that indicates as second and indicates.
For different frame rates, the width of the high level pulse of this second load control signal LD2 ' is different, and increases along with the increase of frame rate; For same frame rate, the width of the high level pulse of this second load control signal LD2 ' is identical.Because this first load control signal LD1 ' adjusts these many data line D ' to this data drive circuit 26
MOn voltage and inoperative, therefore, for same frame rate and different frame rates, the width of the high level pulse of this first load control signal LD1 ' can be all identical, also can be different.Easy for calculating, for same frame rate and different frame rates, select the width of high level pulse of this first load control signal LD1 ' all identical.
In addition, the size of representing the cycle of pixel clock signal CLK ' with T '.Because the width of the high level pulse of this first, second load control signal LD1 ', LD2 ' all adopts the multiple in the cycle of this pixel clock signal CLK ' to represent, and the cycle of the pixel clock signal CLK ' that this display control circuit 20 receives reduces along with the increase of frame rate, therefore, for the second load control signal LD2 ', the width that is stored in the high level pulse of the second load control signal LD2 ' in this look-up table 222 increases with respect to the increase along with frame rate of the multiple in the cycle of pixel clock signal CLK '.
Seeing also Fig. 5, is the synoptic diagram of this look-up table 222.For clear more the present invention is described compactly, existing frame rate with the picture signal that is transferred to this LCD 200 respectively is that 60HZ and 75HZ are that example describes.When this LCD 200 shows same grey menu, for the difference of the pixel 227 stored charge amounts that make reversal of poles row and nonpolarity counter-rotating row reduces, through repeatedly measuring, when frame rate was 60HZ, the width of the high level pulse of this second load control signal LD2 ' was preferably 25T '.When frame rate was 75HZ, the width of the high level pulse of this second load control signal LD2 ' was preferably 35T '.And for this frame rate 60HZ and 75HZ, the width of the high level pulse of this first load control signal LD1 ' all is chosen as 30T '.Then with this frame rate 60HZ and 70HZ, and the width of the high level pulse of this first, second load control signal LD1 ', LD2 ' is stored in this look-up table 222 in advance.
See also Fig. 6, Fig. 6 is the process flow diagram that this LCD 200 is improved the driving method of film flicker phenomenon when showing image.This driving method comprises the steps:
Step S1: receive picture signal and pixel clock signal CLK ';
Step S2: the frame rate of detecting this picture signal;
Step S3: according to the frame rate that detects, correspondence is searched the width of the high level pulse of the width of high level pulse of first corresponding with the frame rate that detects in the look-up table 222 load control signal LD1 ' and the second load control signal LD2 ';
Step S4: according to the size in cycle of this pixel clock signal CLK ', width between per two adjacent high level pulses of the first load control signal LD1 ', width between per two adjacent high level pulses of the second load control signal LD2 ', the width of the width of the high level pulse of the first load control signal LD1 ' that finds and the high level pulse of the second load control signal LD2 ', corresponding the generation first load control signal LD1 ' and the second load control signal LD2 ', and export this first load control signal LD1 ' and arrive data drive circuit 26 with this second load control signal LD2 ';
Step S5: this data drive circuit 26 receives this load control signal LD1 ' and this second load control signal LD2 ', the negative edge of the high level pulse of this load control signal LD1 ' triggers the data voltage that these data drive circuit 26 outputs drive the pixel 227 of corresponding reversal of poles row, and the rising edge of the high level pulse of this second load control signal LD2 ' triggers this data drive circuit 26 and begins to adjust these many data line D '
MOn voltage, and when the negative edge of the high level pulse of this second load control signal LD2 ' arrives, should many data line D '
MOn voltage all adjust to predetermined voltage, next, the negative edge of the high level pulse of this second load control signal LD2 ' triggers the data voltage that 26 outputs of this data drive circuit drive the pixel 227 of corresponding nonpolarity counter-rotating row.
See also Fig. 7 and Fig. 8, Fig. 7 is the driving sequential chart of the refreshing frequency of this LCD 200 when being 60HZ.Fig. 8 is the driving sequential chart of the refreshing frequency of this LCD 200 when being 75HZ.Show that with this LCD 200 same grey menu is example, the driving method that specifies this LCD 200 is as follows:
This display control circuit 20 receives outside picture signal and pixel clock signal CLK ', the frame rate of these frequency detector 210 these picture signals of detecting, when its frame rate that detects is 60HZ, it is that the width of the high level pulse of the first corresponding load control signal LD1 ' of 60HZ is 30T ' that this sequential control circuit 230 is searched in this look-up table 222 with frame rate, the width of the high level pulse of this second load control signal LD2 ' is 25T ', correspondence produces this first load control signal LD1 ' and this second load control signal LD2 ' then, and exports this first load control signal LD1 ' and arrive this data drive circuit 26 with this second load control signal LD2 '.
When the frame rate that detects this picture signal when this frequency detector 210 is 75HZ, it is that the width of the high level pulse of the first corresponding load control signal LD1 ' of 75HZ is 30T ' that this sequential control circuit 230 is searched in this look-up table 222 with frame rate, the width of the high level pulse of this second load control signal LD2 ' is 35T ', correspondence produces this first load control signal LD1 ' and this second load control signal LD2 ' then, and exports this first load control signal LD1 ' and arrive this data drive circuit 26 with this second load control signal LD2 '.
In addition, this sequential control circuit 230 also exports one first control signal CONT1 ' and data-signal (as: RGB DATA ') arrives this data drive circuit 26, and exports one second control signal CONT2g ' to this scan drive circuit 24.These data drive circuit 26 these data-signals of conversion are corresponding data voltage and export this data voltage to these many data line D '
M, when the scanning voltage of these scan drive circuit 24 outputs passes through this sweep trace G '
NBe loaded on the grid g ' of corresponding thin film transistor (TFT) 221, when corresponding thin film transistor (TFT) 221 was opened, these a plurality of data voltages were by these many data line D '
MBe loaded on the pixel electrode 223 of corresponding pixel 227.Simultaneously, public voltage generating circuit 28 continues outputting common voltage to the public electrode 225 of this corresponding pixel 227, thereby liquid crystal panel 22 realizes that picture shows.
Wherein, when the high level pulse of this first load control signal LD1 ' that receives when this data drive circuit 26 was initially located in negative edge, this data drive circuit 26 began to export data voltage for the pixel 227 that drives corresponding reversal of poles row to this multi-column data line D '
M, and the high level pulse of this second load control signal LD2 ' that receives when this data drive circuit 26 is when being initially located in rising edge, these data drive circuit 26 controls make every two adjacent data line D '
MShort circuit, and then, these many data line D '
MBegin discharge, and when the high level pulse of this second load control signal LD2 ' is initially located in negative edge, the data line D ' of these data drive circuit 26 control phase short circuits
MDisconnect each other, and these many data line D ' of control
MWith the corresponding connection of a plurality of output pin (not shown) of this data drive circuit 26, at this moment, these many data line D '
MOn voltage all be same predetermined voltage.In addition, under the triggering of the negative edge of the high level pulse of this second load control signal LD2 ', this data drive circuit 26 is used for driving the data voltage of the pixel 227 of nonpolarity counter-rotating row by its a plurality of output pins outputs.Wherein, the span of this predetermined voltage is: more than or equal to the difference of common electric voltage and 2 volts and less than common electric voltage and 2 volts of sums.
For different frame rates, the width of each high level pulse by adjusting this second load control signal LD2 ', thereby make this data drive circuit 26 after output is used for the data voltage of the capable pixel 227 of driving stage sex reversal, and before the data voltage of output for the pixel 227 that drives nonpolarity counter-rotating row, can control this data drive circuit 26 should many data line D '
MOn voltage all adjust to this predetermined voltage, thereby make the data voltage of data voltage and the pixel 227 that drives nonpolarity counter-rotating row of the pixel 227 that the driving stage sex reversal is capable at data line D '
MOn Changing Pattern be tending towards identical.Therefore, when this thin film transistor (TFT) 221 receives the scanning voltage of gate turn-on, store the quantity of electric charge of pixel 227 of reversal of poles row into to store the quantity of electric charge of nonpolarity counter-rotating row into basic identical, and then, for different frame rates, these LCD 200 film flicker phenomenons are less.
Because the frame rate of 20 pairs of picture signals that receive of this display control circuit is detected, for different frame rates, it outputs to the width difference of high level pulse of the second load control signal LD2 ' of this data drive circuit 26, and increase along with the increase of frame rate, to control this data drive circuit 26 before the output data voltage arrives the pixel 227 of nonpolarity counter-rotating row, should many data line D '
MOn voltage all be adjusted into this predetermined voltage, and then make the data voltage of data voltage and the pixel 227 of corresponding reversal of poles row of pixel 227 of corresponding nonpolarity counter-rotating row at these many data line D '
MOn the Changing Pattern basically identical, thereby make that the pixel 227 stored charge amounts of this reversal of poles row and this nonpolarity counter-rotating row are basic identical.Therefore, this LCD 200 when receiving the picture signal of different frame frequency, phenomenon of picture flicker in the time of can both improving it and show image.
For above-mentioned LCD 200, because this first load control signal LD1 ' is also inoperative for the adjustment of this predetermined voltage, therefore, for different frame rates, the width that stored correspondence constitutes the high level pulse of this first load control signal LD1 ' in this look-up table 222 also can be not limited to 30T '.Equally, the width of the high level pulse of this second load control signal LD2 ' also can be other numerical value.For a person skilled in the art, because the different and corresponding experiments of measuring condition difference of the relevant configuration of LCD, all may cause testing drawing the clock quantity different with the clock quantity of this case instructions record.Therefore, can not be limited with the numerical value of this instructions record.
See also Fig. 9, Fig. 9 is the driving sequential chart of LCD the 3rd embodiment of the present invention.The structure of this LCD (not shown) and this LCD 200 is roughly the same, and its difference only is: for same frame rate, the sequential control circuit of the LCD of the 3rd embodiment only produces a load control signal LD "." the control data drive circuit was all adjusted to predetermined voltage with the voltage on these many data lines to this load control signal LD before the data voltage of the pixel of the every row of output.This load control signal LD " the rising edge of high level pulse trigger this data drive circuit the voltage on these many data lines adjusted; and at this load control signal LD " the negative edge of high level pulse when arriving, the voltage on these many data lines is adjusted to this predetermined voltage.And at this load control signal LD " the negative edge of high level pulse trigger down the data voltage of the pixel of this data drive circuit output driving corresponding line.
Wherein, export before the data voltage of the capable pixel of driving stage sex reversal this load control signal LD in advance at this data drive circuit " be used for triggering the voltage of this data drive circuit on will this many data lines adjusts to the rising edge of the high level pulse of predetermined voltage and preferably triggers second property adjusted triggering sign that indicates as second; " negative edge that is used for the data voltage of the capable pixel of this data drive circuit output driving stage sex reversal of triggering preferably triggers the second output property triggering sign that indicates as first to this load control signal LD; Export before the data voltage of the pixel that drives nonpolarity counter-rotating row this load control signal LD in advance " being used for triggering the voltage of this data drive circuit on will this many data lines adjusts to the rising edge of the high level pulse of predetermined voltage and preferably triggers first property adjusted triggering sign that indicates as second at this data drive circuit; This load control signal LD " is used for triggering this data drive circuit and exports the first output property triggering sign that the negative edge of the data voltage of the pixel that drives nonpolarity counter-rotating row preferably indicates as first triggering.
The present invention is not limited to above-mentioned embodiment, and this LCD 100,200 type of drive can also add some inversion driving mode of two lines etc. for one.Wherein, this some inversion driving mode that adds two lines is: this LCD 100, that 200 4i+2 is capable is identical with same row pixel 127,227 polarity of voltages that load during 4i+3 is capable, 4i+1 is capable, and polarity with the same row pixel 127 during 4i+4 is capable, 227 on-load voltages is identical, and the capable polarity with the same row pixel 127 during 4i+3 is capable, 227 on-load voltages of 4i+2 is opposite, and pixel 127,227 on-load voltage polarity of the same delegation of adjacent two row are opposite arbitrarily.The polarity of each pixel 127,227 on-load voltages is reversed frame by frame.Wherein, i is the integer more than or equal to zero.
This LCD 100,200 can adopt the every triplex row of polarity or more some inversion driving mode and two row or the capable inversion driving modes of multirow of multirow.
In a kind of change embodiment, this sequential control circuit 130 is according to the size of the period T of the drive pattern of this LCD 100 and this pixel clock signal CLK, correspondence only produces a load control signal LD, and the waveform of this load control signal LD specifically as shown in figure 10.In fact, this load control signal LD is the first load control signal LD1 and the second load control signal LD2 signal after synthetic.Therefore, this data drive circuit 16 is according to this load control signal LD, both can be corresponding the data voltage of output polarity counter-rotating row and the pixel 127 of nonpolarity counter-rotating row, also can be before the data voltage of the pixel 127 of the nonpolarity counter-rotating row of pre-output, should many data line D
MOn voltage all adjust to this predetermined voltage.
Similar to above-mentioned change embodiment, in another kind change embodiment, for the picture signal of same frame rate, this sequential control circuit 230 also only produces a load control signal LD ' according to this LCD 200, and the waveform of this load control signal LD ' specifically as shown in figure 11.Frame rate with 75HZ is example, and this load control signal LD ' is the signal after the first load control signal LD1 ' shown in Fig. 8 synthesizes with the second load control signal LD2 '.For different frame rates, this sequential control circuit 230 produces different load control signal LD ', and wherein, along with the increase of frame rate, these many data line D ' are adjusted in this load control signal LD ' control
MOn voltage to the width of the high level pulse of this predetermined voltage also along with increase so that for same grey menu, the stored quantity of electric charge of the pixel of corresponding reversal of poles row and nonpolarity counter-rotating row 227 is basic identical.
See also Figure 12, it is the driving sequential chart of this LCD 200 another embodiment.For different frame rates, this predetermined voltage also can be for differing less and equal-sized positive polarity predetermined voltage and negative polarity predetermined voltage with this common electric voltage.When the data voltage of these data drive circuit 26 pre-output cathodes before the pixel 227 of this nonpolarity counter-rotating row, the data line D ' that it will be connected with the pixel 227 of the data voltage of this prestrain positive polarity
MOn voltage all adjust to this positive polarity predetermined voltage; On the contrary, this data drive circuit 26 data line D ' that will be connected with the pixel 227 of the data voltage of prestrain negative polarity
MOn voltage all adjust to this negative polarity predetermined voltage.Wherein, the span of this positive polarity predetermined voltage is: more than or equal to common electric voltage and less than common electric voltage and 2 volts of sums; The span of this negative polarity predetermined voltage is: more than or equal to the difference of common electric voltage and 2 volts and less than common electric voltage.
Equally, for this LCD 100, this predetermined voltage also can be for differing less and equal-sized positive polarity predetermined voltage and negative polarity predetermined voltage with this common electric voltage.
See also Figure 13, it is the driving sequential chart of this LCD 200 another embodiment.For different frame rates, the rising edge of the high level pulse of this first load control signal LD1 ' can substitute its negative edge and trigger the second output property triggering sign that indicates as first, in order to trigger the data voltage that these data drive circuit 26 outputs drive the pixel 227 of corresponding reversal of poles row.Frame rate with 60HZ is example, and when the high level pulse of this first load control signal LD1 ' that receives when this data drive circuit 26 was in rising edge, 26 output of this data drive circuit data voltage was to the pixel 227 of corresponding reversal of poles row.
Equally, for this LCD 100, the rising edge of the high level pulse of this first load control signal LD1 also can substitute its negative edge, in order to trigger the data voltage that these data drive circuit 16 outputs drive the pixel 127 of corresponding reversal of poles row.
This predetermined voltage also can be preferably ground voltage.
In addition, except the rising edge or negative edge of the high level pulse of first, second load control signal, first described in this case triggers to indicate with second and triggers to indicate and also can be other locational points or one section pulse of first, second load control signal.
Claims (16)
1. LCD, it comprises:
Liquid crystal panel, it comprises the multi-strip scanning line, many data lines that intersect with the insulation of this multi-strip scanning line and a plurality of pixels that defined by this multi-strip scanning line and these many data lines, and these a plurality of pixels are divided into the pixel of reversal of poles row and the pixel of nonpolarity counter-rotating row according to type of drive;
Display control circuit, it receives picture signal and generates clock signal and data-signal according to this picture signal;
Data drive circuit, it receives this clock signal and this data-signal to form a plurality of data voltages;
It is characterized in that: this data drive circuit is before the data voltage of the pixel of the nonpolarity counter-rotating row of pre-output driving, voltage on these many data lines is all adjusted to predetermined voltage, so that for same grey menu, the pixel stored charge amount of this reversal of poles row is considered as identical with the pixel stored charge amount of this nonpolarity counter-rotating row;
Wherein, also output load control signal of this display control circuit is to this data drive circuit, this load control signal has a plurality of first and triggers sign and a plurality of second triggering sign, these a plurality of first triggering signs are divided into a plurality of first property exported triggerings signs of exporting the data voltage of the pixel that drives nonpolarity counter-rotating row for this data drive circuit of triggering, indicate with a plurality of second output property triggerings for the data voltage that triggers the capable pixel of this data drive circuit output driving stage sex reversal, this second triggering indicates and comprises that a plurality of first property adjusted triggerings indicate, each first output property triggering indicates respectively, and corresponding one first property adjusted triggering indicates, this a plurality of first property adjusted triggering indicates and was used for before this data drive circuit is exported the data voltage of the pixel that drives nonpolarity counter-rotating row in advance, trigger the voltage of this data drive circuit on will these many data lines and all adjust to this predetermined voltage, wherein, this first property adjusted triggering indicate trigger the voltage of this data drive circuit on will this many data lines and all adjust to this predetermined voltage after, this first output property triggering indicates and just triggers the data voltage that this data drive circuit is exported the pixel of the nonpolarity counter-rotating row of driving.
2. LCD as claimed in claim 1 is characterized in that: this data drive circuit is before the data voltage of the capable pixel of pre-output driving stage sex reversal, and the voltage on also will these many data lines is all adjusted to this predetermined voltage.
3. LCD as claimed in claim 2, it is characterized in that: this second triggering indicates and comprises that further a plurality of second property adjusted triggerings indicate, each second output property triggering indicates respectively, and corresponding one second property adjusted triggering indicates, this a plurality of second property adjusted triggering indicates and was used for before this data drive circuit is exported the data voltage of the capable pixel of driving stage sex reversal in advance, trigger the voltage of this data drive circuit on will these many data lines and all adjust to this predetermined voltage, wherein, this second property adjusted triggering indicate trigger the voltage of this data drive circuit on will this many data lines and all adjust to this predetermined voltage after, this second output property triggering indicates and just triggers the data voltage that this data drive circuit is exported the capable pixel of driving stage sex reversal.
4. LCD as claimed in claim 1, it is characterized in that: this load control signal is square-wave pulse signal, this first output property triggering is denoted as the negative edge of the high level pulse of this load control signal, this second output property triggering is denoted as the negative edge of the high level pulse of this load control signal, this first property adjusted triggering is denoted as the rising edge of the high level pulse of this load control signal, wherein, the width of the high level pulse of this load control signal is adjusted voltage on these many data lines to time of this predetermined voltage for this data drive circuit of control.
5. LCD as claimed in claim 1, it is characterized in that: this load control signal is square-wave pulse signal, this first output property triggering is denoted as the negative edge of the high level pulse of this load control signal, this second output property triggering is denoted as the rising edge of the high level pulse of this load control signal, this first property adjusted triggering is denoted as the rising edge of the high level pulse of this load control signal, wherein, the width of the high level pulse of this load control signal is adjusted voltage on these many data lines to time of this predetermined voltage for this data drive circuit of control.
6. LCD as claimed in claim 3, it is characterized in that: this load control signal is square-wave pulse signal, this first output property triggering is denoted as the negative edge of the high level pulse of this load control signal, this second output property triggering is denoted as the negative edge of the high level pulse of this load control signal, this first property adjusted triggering is denoted as the rising edge of the high level pulse of this load control signal, this second property adjusted triggering is denoted as the rising edge of the high level pulse of this load control signal, wherein, the width of the high level pulse of this load control signal is adjusted voltage on these many data lines to time of this predetermined voltage for this data drive circuit of control.
7. LCD as claimed in claim 1, it is characterized in that: this load control signal comprises one first load control signal and one second load control signal, this first load control signal and this second load control signal all are square-wave pulse signal, wherein, this first output property triggering is denoted as the negative edge of the high level pulse of this second load control signal, this second output property triggering is denoted as the negative edge of the high level pulse of this first load control signal, this first property adjusted triggering is denoted as the rising edge of the high level pulse of this second load control signal, and the width of the high level pulse of this second load control signal is adjusted voltage on these many data lines to time of predetermined voltage for this data drive circuit of control.
8. LCD as claimed in claim 1, it is characterized in that: this load control signal comprises one first load control signal and one second load control signal, this first load control signal and this second load control signal all are square-wave pulse signal, wherein, this first output property triggering is denoted as the negative edge of the high level pulse of this second load control signal, this second output property triggering is denoted as the rising edge of the high level pulse of this first load control signal, this first property adjusted triggering is denoted as the rising edge of the high level pulse of this second load control signal, and the width of the high level pulse of this second load control signal is adjusted voltage on these many data lines to time of this predetermined voltage for this data drive circuit of control.
9. LCD as claimed in claim 3, it is characterized in that: this load control signal comprises one first load control signal and one second load control signal, this first load control signal and this second load control signal all are square-wave pulse signal, wherein, this first output property triggering is denoted as high level pulse following to the edge of this second load control signal, this second output property triggering is denoted as the negative edge of the high level pulse of this first load control signal, this first property adjusted triggering is denoted as the rising edge of the high level pulse of this second load control signal, this second property adjusted triggering is denoted as the rising edge of the high level pulse of this first load control signal, this first load control signal, the width of the high level pulse of second load control signal is adjusted voltage on these many data lines to time of this predetermined voltage for this data drive circuit of control.
10. LCD as claimed in claim 3, it is characterized in that: this display control circuit is detected the frame rate of this picture signal, for same frame rate, the width of the high level pulse of this load control signal is identical, for different frame rates, the width difference of the high level pulse of this load control signal.
11. LCD as claimed in claim 10 is characterized in that: for different frame rates, the width of the high level pulse of this load control signal increases along with the increase of frame rate.
12. as any described LCD among the claim 7-8, it is characterized in that: this display control circuit is detected the frame rate of this picture signal, for same frame rate, the width of the high level pulse of this second load control signal is identical, for different frame rates, the width difference of the high level pulse of this second load control signal.
13. LCD as claimed in claim 12 is characterized in that: for different frame rates, the width of the high level pulse of this second load control signal increases along with the increase of frame rate.
14. LCD as claimed in claim 1, it is characterized in that: this LCD further comprises a public voltage generating circuit, this public voltage generating circuit provides common electric voltage to arrive this a plurality of pixels, and this predetermined voltage is more than or equal to the difference of common electric voltage and 2 volts and smaller or equal to common electric voltage and 2 volts of sums; Perhaps this predetermined voltage is ground voltage; Perhaps this predetermined voltage is that two polarity are opposite, and equal-sized positive polarity predetermined voltage and negative polarity predetermined voltage, before the data voltage of the pre-output cathode of this data drive circuit arrives the pixel of this nonpolarity counter-rotating row, its will with data line that the pixel of the data voltage of prestrain positive polarity is connected on voltage all adjust to this positive polarity predetermined voltage, on the contrary, this data drive circuit will with data line that the pixel of the data voltage of prestrain negative polarity is connected on voltage all adjust to this negative polarity predetermined voltage, wherein, this positive polarity predetermined voltage is greater than common electric voltage and smaller or equal to common electric voltage and 2 volts of sums, and this negative polarity predetermined voltage is more than or equal to the difference of common electric voltage and 2 volts and less than common electric voltage.
15. as claim 7 or 8 described LCD, it is characterized in that: this display control circuit also is used for receiving a pixel clock signal, this pixel clock signal is the square-wave pulse signal that changes one-period, for different frame rates, the frequency of the pixel clock signal that this display control circuit receives increases along with the increase of frame rate, this display control circuit comprises a storer, the a plurality of different frame rates of storage in this storer, and the width of the high level pulse of this first load control signal of corresponding each frame rate and this second load control signal, wherein, the width of the high level pulse of this first load control signal and this second load control signal is represented with the multiple in the cycle of this pixel clock signal.
16. LCD as claimed in claim 15, it is characterized in that: this display control circuit is according to the frame rate that detects, correspondence is searched the width of the high level pulse of first corresponding with this frame rate that detects in this storer load control signal and this second load control signal, and then corresponding generation first load control signal and second load control signal, and export this first load control signal and arrive this data drive circuit with this second load control signal.
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| TWI464723B (en) | 2012-11-12 | 2014-12-11 | Novatek Microelectronics Corp | Display apparatus |
| CN103839526A (en) * | 2012-11-22 | 2014-06-04 | 联咏科技股份有限公司 | Display apparatus |
| CN104361876B (en) | 2014-12-08 | 2016-10-26 | 京东方科技集团股份有限公司 | A kind of driving method, drive circuit and display device |
| CN104766583B (en) * | 2015-04-27 | 2017-07-04 | 京东方科技集团股份有限公司 | A kind of compensation method of polarity inversion, device and liquid crystal display |
| CN105761690B (en) * | 2016-05-04 | 2018-08-14 | 深圳市华星光电技术有限公司 | The driving method of display panel and display device including it |
| CN106652931B (en) * | 2016-11-03 | 2019-05-07 | 深圳市华星光电技术有限公司 | Display driver circuit, drive control method, voltage supply chip and display equipment |
| CN106683629B (en) * | 2016-12-28 | 2019-10-25 | 武汉华星光电技术有限公司 | The driving device and driving method of liquid crystal display panel |
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| CN112735349B (en) * | 2020-12-31 | 2022-04-22 | 成都中电熊猫显示科技有限公司 | Liquid crystal display and driving method thereof |
| CN112669784B (en) * | 2021-01-07 | 2022-07-19 | 三星半导体(中国)研究开发有限公司 | Liquid crystal display device and method of driving the same |
| CN114203128B (en) * | 2021-12-17 | 2022-11-15 | 武汉京东方光电科技有限公司 | Display panel driving method and circuit and display device |
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| US20040017344A1 (en) * | 2002-07-25 | 2004-01-29 | Takahiro Takemoto | Liquid-crystal display device and driving method thereof |
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