CN104350595A - 克服分划板区域限制的大型硅中介板 - Google Patents

克服分划板区域限制的大型硅中介板 Download PDF

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CN104350595A
CN104350595A CN201380029354.2A CN201380029354A CN104350595A CN 104350595 A CN104350595 A CN 104350595A CN 201380029354 A CN201380029354 A CN 201380029354A CN 104350595 A CN104350595 A CN 104350595A
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wafer
silicon
intermediate plate
substrate
integrated circuit
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CN104350595B (zh
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宋浩宇
曹玮
牛瑞
安瓦尔·***
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Huawei Technologies Co Ltd
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Abstract

一种多晶片集成电路组件包括一个大于在制造“有源区域”中使用的典型分划板大小的中介基板，在有源区域中，硅穿孔(TSV)和互连导体在所述中介板中形成。同时，每个晶片使其外部电源/地线和I/O信号线路连接集中在晶片的较小区域中。所述晶片设置或安装在所述中介板上，使得这些(具有电路/地线/IO连接的)较小区域覆盖所述中介板的有源区域。在这种构造中，多个具有相当大于所述中介板的有源区域的总区域的晶片可以安装在所述中介板上(以及利用有源区域进行连接)。

Description

克服分划板区域限制的大型硅中介板
相关申请案交叉申请
本发明要求2012年7月17日递交的发明名称为“克服分划板区域限制的大型硅中介板”的第13/551466号美国专利申请案的在先申请优先权，其以全文引入的方式并入本文本中
技术领域
本发明涉及互连技术，尤其涉及在多晶片集成电路封装中使用的方法和硅中介板结构。
背景技术
2D集成电路封装(2D IC封装)是一种单一封装，通过安装多个半导体晶圆/晶片/芯片并将它们水平地互连而构成，以用作单个设备或***。3D集成电路封装(3D IC封装)或3维堆栈集成电路封装(3DS IC封装)是一种单一集成封装，通过垂直堆叠各个半导体晶圆/晶片/芯片并将它们互连而构成，以用作单个设备或***。在许多设计中，硅穿孔(TSV)技术能够使多个半导体晶圆/晶片/芯片之间互连并将大量功能并入相对较小的封装中。应了解，晶圆/晶片/芯片可以是异质的。仅供参考，3D集成电路(3D IC)是一种单一晶圆/晶片/芯片，该单一晶圆/晶裸片/芯片具有一个或多个垂直和水平集成在单一电路中的有源电子部件。
近来，已经开发出一种不同的多晶片封装。这种类型的封装有时称为2.5D集成电路封装(2.5D IC封装)。在2.5D IC封装中，多个晶圆/晶片/芯片安装在“中介板”结构上。多个晶片通过使用TSV技术放置在负责晶片之间互连的无源硅中介板以及外部I/O上。这种设计优于3D IC封装，因为这种设计成本较低并且具有更好的热性能。应了解，每个“晶片”可以是2D IC封装或甚至是3D IC或3D IC封装。
参考图1，提供一种图示常规2.5D IC封装100的横截面图。该2.5D IC封装100包括多个晶片102，其具有多个到中介基板104的电连接110(例如微焊球)用于承载电源、地线和/或其他信号。中介基板104可以由任何提供多个电导体的合适的材料构造，多个电导体经由中介基板从一侧延伸到另一侧。中介基板104还包括多个到封装基板106的连接112(例如凸块)。封装基板106包括多个连接114(例如BGA焊球)。
中介基板104之内包含多个经由中介基板和在其中延伸的电导体线路(未示出)。构造这些导体用于提供连接110和连接112之间和之中想要的互连图案或连接矩阵。在一项实施例中，基板104是使用TSV技术构造的硅中介板。
受光刻分划板大小(掩模和图案大小)的限制，可以实现的最大硅中介层基板大小约为25mm×31mm。在潜在的高端网络应用中，如果使用2.5D IC封装，多个大的裸硅片将需要并排放置在中介基板上。这将需要使用更大的中介基板(例如45mm×45mm)。然而，这种大小的中介基板要么不容易制造要么需要专用光刻工艺，这将显著增加成本(并可能降低产量)。
相应地，需要一种使用常规或当前光刻技术将在制造多晶片封装中使用的方法和中介基板封装构造。
发明内容
根据一项实施例，提供一种具有一个基板的多晶片集成电路组件，所述基板具有多个连接；以及一种设置在所述基站上方的硅中介板。所述硅中介板包括第一部分和第二部分，其中第一部分具有多个与所述基板的多个连接电接触的硅穿孔。第二部分邻近所述第一部分并且不具有硅穿孔。多个集成电路晶片设置在所述硅中介板上方并且横向彼此相邻，其中每个晶片与所述多个硅穿孔中的一个或多个电接触，所述多个硅穿孔用于充当所述晶片和所述基板之间的互连。所述多个晶片中的一个晶片的至少一部分设置在上方并由所述硅中介板的第二部分支撑。
根据另一项实施例，提供一种具有一个基板的多晶片集成电路组件，所述基板具有多个互连导体；以及一种设置在所述基板上方的内插器基板。所述内插器基板具有位于中心的第一部分和与所述第一部分相邻的第二部分。所述第一部分包括多个硅穿孔和多个互连导体，而第二部分不具有硅穿孔和互连导体。该组件还包括第一多个连接，其电耦接于所述基板的互连导体和所述多个硅穿孔。多个集成电路晶片设置在所述硅中介板上方并且横向彼此相邻，其中每个晶片与所述多个硅穿孔中的一个或多个电接触，所述多个硅穿孔用于充当所述晶片和所述基板之间的互连。第二多个连接分别电耦接于所述多个硅穿孔中的每个硅穿孔和所述多个晶片中的每个晶片。所述多个晶片中的一个晶片的至少一部分延伸越过所述内插器基板的第一部分的***。
附图说明
为了更完整地理解本发明及其优点，现在参考以下结合附图进行的描述，其中：
图1描绘了现有技术多晶片封装结构；
图2A和图2B描绘了本发明所述的示例多晶片集成电路组件；以及
图3描绘了在分割之前包含多个硅中介板的晶圆。
具体实施方式
总体而言，本发明描述和教示了新的2.5D IC封装组件的设计和构造，该新的2.5D IC封装组件通过使用具有常规大小的“有源区域”的较大型的硅中介板来使得封装尺寸整体上更大。如图1所示，现有技术受到安装在硅中介板上的晶片的限制，这些晶片的总区域少于硅中介板的区域。因此，如果晶片较大，其与其他晶片到2.5D IC封装组件的组合性受到限制。通过在“有源区域”上仅对齐多个晶片的几个部分，较大晶片和/或较多数目的晶片可以组合并组装成单一封装。
由于本专利文档的编写目的，硅中介板中的术语“有源区域”指的是出现TSV和其他互连导体(例如，电源、地线和其他信号)以及使用光刻分划板(也称为光掩模)形成的区域。
图2A和图2B分别描绘了本本发明所述的示例多晶片集成电路组件200的俯视图和横截面视图。
组件200包括内插器结构210，该内插器结构具有第一部分210a和第二部分210b。多个集成电路晶片220(220a到220d)放置在上方并安装在内插器结构210上，如图所示，并且通过导电连接270电连接到内插器结构210。连接270很容易被所属领域的技术人员了解，并且可以构造成内焊球、微焊球或者一些其他的导电结构。内插器结构210可以由能够提供TSV和其他在其中延伸的互连导体的任何合适的材料构造。在一项实施例中，内插器结构210是由硅构造的。
在晶片220和硅中介板210之间可包括用于支撑一部分晶片220的可选支撑结构272，该可选支撑结构272延伸越过硅中介板210的第一部分210a的***。该支撑结构可以构造成内焊球、微焊球或者一些其他结构。在一项实施例中，为了便于制造和组装，结构272与连接270相同。应了解，在一项实施例中，结构272可以称为“假”内焊球或假连接。在另一项实施例中，假连接272与晶片220中的电源、地线和信号通路电隔离。
硅中介板210放置在上方并安装在基板230上，如图所示，并且通过导电连接280电耦接到基板230。连接280很容易被所属领域的技术人员了解，并且可以构造成内焊球(例如C4内焊球)或一些其他导电结构。基板230的下面是多个连接290，其很容易被所属领域的技术人员了解，并且可以构造成外焊球或一些其他导电结构。各种互连导体292放置在基板230内并在连接280和连接290之间提供电连接。
类似于支撑结构272，在硅中介板210和基板之间可包括用以支撑部分硅中介板210的可选支撑结构282，该可选支撑结构282延伸越过硅中介板210的第一部分210a的***。支撑结构282可以构造成凸块或一些其他结构。在一项实施例中，为了便于制造和组装，结构282与连接280相同。应了解，在一项实施例中，结构282可以称为“假”内焊球或假连接。在另一项实施例中，假连接282与硅中介板210和基板230中的导电通路电隔离。
多个TSV240和多个互连导体或通道242(尽管仅示出了一些)形成并放置于硅中介板210的第一部分210之内。构造TSV240和互连导体242用于在多个晶片220之间和之中以及在多个晶片220和基板230之间提供一个想要的互连图案或模型。第一部分210a(或区域)称为内插器210的“有源区域”。相反，硅中介板210的第一部分210b不包括任何用于连接晶片220或基板230的TSV或其他导体(即，没有这些结构)。
参考图2A，所示硅中介板210的大小为m×n。第一部分210a的大小为a×b，其限定了整个m×n区域的子区域。a×b大小定义了有源区域(部分210a)并且还基本上对应于在制造工艺中使用的分划板大小以形成有源区域内的TSV240和互连导体242。在现有技术中，硅中介板的区域大小受分划板大小(a×b大小)的限制。
根据本发明，多个晶片220中的一个或多个用于使它们的电源/地线和外部I/O信号线路连接集中在晶片220的区域之内。例如，晶片220a、220b、220c和220d分别在区域212a、212b、212c和212d(其在a×b区域的部分210a之内)内具有它们的电力/接地和外部I/O信号线路连接。每个晶片布置在组件220之内，这样分配这些连接(内焊球)，使得所有连接(内焊球)在第一部分210a(如图2A所示，由区域a×b限定)之内。如前所述，TSV240和互连导体242都在该有源区域/部分硅中介板210(部分210a)中制造。因此，整个硅中介板210的大小可以被认为与m×n一样大，但是有效/有源区域(a×b)可以为使用当前技术可以制造出的较小尺寸。
在各项实施例中，每个晶片220使它们各自的电源/地线和I/O信号线路分别集中在晶片220的第一区域212a、212b、212c和212d之内，而且每个第一区域的大小/量级大大小于各个晶片的整体区域。在本文中，当第一区域小于整体区域的大约75％或更小时，第一区域大大小于晶片的整体区域。在其他项实施例中，第一区域可以是总区域的60％、50％、40％、30％或甚至20％。
现参考图3，示出了含有多个在硅晶片上形成的硅中介板210的硅晶圆300。应了解，形成TSV240和互连导体242的制造工艺仅仅应用于每个内插器的第一部分210。应了解，如现有技术中已知的，执行常规工艺以构造具有想要的TSV240和互连导体242的图案的硅中介板210。在制造之后，晶圆300沿虚线分割。
现返回参考图2B，TSV240和互连导体242(未全部示出)集中在第一部分210，且电源/地线和外部I/O线路分散在封装基板230。
出于清晰目的，并没有示出或描述组件200内所有的元件，而仅仅示出那些理解本发明必需的元件。在其他项实施例中，一个或多个晶片220可以是2D集成电路(2D IC)、2D IC封装、3D集成电路(3D IC)或3D IC封装，或上述项的任意组合。
阐述本专利文档使用的某些词和短语的定义是有利的。术语“包括”、“包含”及其派生词表示包括但不限于。术语“或者”是包容性的，表示和/或。短语“相关联”、“与之关联”及其派生词可以表示包含、包含在、互连、含有、含在、连接至或相连接、耦接至或相耦接、可互相传播、互相协作、交错、并置、接近、绑定至或被绑定、具有、具有一种属性等等。
然而本发明已描述某些实施例和相关方法，这些实施例和方法的替代和改变对本领域技术人员而言是显而易见的。相应地，示例实施例的上述描述不能定义或约束本发明。其它变化、替代和改变的示例可以在不脱离本文精神和范围的情况下，由以下权利要求确定。

Claims (14)

1.一种多晶片集成电路组件，其特征在于，包括：
一个具有多个连接的基板；
一个设置在所述基板上方的硅中介板，所述硅中介板具有第一部分和第二部分，所述第一部分包括多个与所述基板的所述多个连接电接触的硅穿孔，所述第二部分邻近所述第一部分并且不具有硅穿孔；
多个集成电路晶片设置在所述硅中介板上方并且横向彼此相邻，每个晶片与所述多个硅穿孔中的一个或多个电接触，其中所述多个硅穿孔用于充当所述晶片和所述基板之间的互相连接；
其中所述多个晶芯片中的一个晶片的至少一部分设置在上方并由所述硅中介板的所述第二部分支撑。
2.根据权利要求1所述的多晶片组件，其特征在于，进一步包括：
多个设置在所述硅中介板的所述第二部分和由所述硅中介板的所述第二部分支撑的所述多个晶片中的一个晶片的部分之间的第一支撑构件。
3.根据权利要求1所述的多晶片组件，其特征在于，所述硅中介板的所述第一部分进一步包括：
多个与多个晶片中的一个或多个电接触的互连导体，以及所述第二部分没有互连导体。
4.根据权利要求1所述的多晶片集成电路组件，其特征在于，所述多个晶片中的至少一个晶片包括2D集成电路晶片。
5.根据权利要求1所述的多晶片集成电路组件，其特征在于，至少一个所述多个晶片包括3D集成电路。
6.根据权利要求1所述的多晶片电路组件，其特征在于，所述多个晶片中的每个晶片覆盖所述硅中介板的所述第一部分以及覆盖所述硅中介板的所述第二部分。
7.根据权利要求1所述的多晶片集成电路组件，其特征在于，所述多个晶片的每个晶片使其各自的电源/地和I/O信号线路集中在所述晶片的第一区域内，所述第一区域大大小于所述晶片的总区域。
8.一种多晶片集成电路组件，其特征在于，包括：
一个具有多个互连导体的基板；
一个设置在所述基板上方的硅中介板，所述硅中介板具有位于中间的第一部分和邻近所述第一部分的第二部分，所述第一部分包括多个硅穿孔和多个互连导体，以及所述第二部分没有硅穿孔和互连导体；
第一多个连接，其电耦接所述基板的互连导体和所述多个硅穿孔；
多个设置在所述硅中介板上方并且横向彼此相邻的集成电路晶片，每个晶片与所述多个硅穿孔中的一个或多个电接触，其中所述硅穿孔用于充当所述晶片和所述基板之间的互相连接。
第二多个连接，其电耦接所述多个硅穿孔中的每个硅穿孔与所述多个芯片中的每个芯片；以及
所述多个芯片中的一个芯片的至少一部分延伸越过所述中介基板的第一部分的***。
9.根据权利要求8所述的多晶片组件，其特征在于，进一步包括：
设置在所述硅中介板上方的所述第二部分以及用于支持所述多个延伸越过所述中介基板的所述第一部分的晶片中的一个晶片的一部分的支撑构件。
10.根据权利要求9所述的多晶片组件，其特征在于，进一步包括：
设置在所述基板上方以及用于支撑所述中介基板的所述第二部分的第二支撑构件。
11.根据权利要求8所述的多晶片组件，其特征在于，进一步包括：
第三多个连接，所述第三多个连接包括第一连接和第二连接，分别用于将所述中介基板中的多个互连导体中的一个电耦接到第一晶片和第二晶片。
12.根据权利要求8所述的多晶片集成电路组件，其特征在于，所述中介基板包括硅基板。
13.根据权利要求8所述的多晶片电路组件，其特征在于，所述多个晶片中的每个晶片覆盖所述中介基板的所述第一部分以及覆盖所述中介基板板的所述第二部分。
14.根据权利要求8所述的多晶片集成电路组件，其特征在于，所述多个晶片中的每个晶片使其各自的电源/地和I/O信号线路集中在所述晶片的第一区域内，所述第一区域大大小于所述晶片的总区域。
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