CN104333369B - A kind of DDR3 PHY SSTL15 output driving circuits - Google Patents
A kind of DDR3 PHY SSTL15 output driving circuits Download PDFInfo
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- CN104333369B CN104333369B CN201410589755.XA CN201410589755A CN104333369B CN 104333369 B CN104333369 B CN 104333369B CN 201410589755 A CN201410589755 A CN 201410589755A CN 104333369 B CN104333369 B CN 104333369B
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Abstract
The invention provides a kind of DDR3 PHY SSTL15 output driving circuits, the output driving circuit includes：At least one output module, each described output module parallel connection；Wherein, each output module includes：Preceding drive circuit and back driving circuit；Preceding drive circuit includes：Six NOT gates, four NAND gates, two circuits of multiselect one, n the first output conversion circuits and n the second output conversion circuits, back driving circuit include：N NMOS group, n PMOS group and two diodes.The DDR3 PHY SSTL15 output driving circuits that the present invention is provided, which are realized, can export DDR3 PHY SSTL15 data to be sent.And transmission state and reception state can be respectively at, by preceding driving circuit output data to be sent during in the state of transmission, back driving circuit output high-impedance state is used for impedance matching during in reception state.
Description
Technical field
The present invention relates to electronic technology field, more particularly, to a kind of DDR3 PHY SSTL15 output driving circuits.
Background technology
DDR3 PHY are for connection to the indispensable bridge of DDR3SDAM memories and DDR3 storage controls.DDR3 PHY bags
Include DDL, PLL, transmitter, receiver, SSTL input driving circuits, SSTL output driving circuits etc..Wherein, SSTL outputs are driven
Dynamic circuit is mainly used in exporting DDR3 PHY data to be sent.
SSTL 15 is a kind of the more commonly used SSTL interfaces, however, inventor it has been investigated that, in the prior art simultaneously
In the absence of DDR3 PHY SSTL15 output driving circuits.
The content of the invention
Present invention solves the technical problem that being to provide a kind of DDR3 PHY SSTL15 output driving circuits, to realize energy
Enough export DDR3 PHY SSTL15 data to be sent.
In addition, the technical problem that the present invention can also be solved is, the DDR3 PHY SSTL15 output drivings that the present invention is provided
Circuit, can be respectively at transmission state and reception state, data to be sent be exported when in the state of transmission, when in reception
High-impedance state is exported during state, for impedance matching.
Therefore, the technical scheme that the present invention solves technical problem is：
A kind of DDR3 PHY SSTL15 output driving circuits, the output driving circuit includes：At least one output mould
Block, each described output module parallel connection；
Wherein, each output module includes：Preceding drive circuit and back driving circuit；The preceding drive circuit includes：
First NOT gate, the second NOT gate, the 3rd NOT gate, the 4th NOT gate, the 5th NOT gate, the 6th NOT gate, the first NAND gate, the second NAND gate,
3rd NAND gate, the 4th NAND gate, the circuit of the first multiselect one, the circuit of the second multiselect one, n the first output conversion circuits and n are individual
Second output conversion circuit；n≥1；The back driving circuit includes：N NMOS groups, n PMOS groups, the first diode and second
Diode；Each NMOS groups include at least one NMOS tube, and each PMOS groups include at least one PMOS；
Two inputs of first NAND gate are respectively used to receive output module enable signal and transmission state is enabled
Signal；Wherein, when the output module is enabled state, it is high level that the output module, which enables signal, when the output
When module is disabled status, it is low level that the output module, which enables signal,；It is described when the output module is transmission state
It is high level that transmission state, which enables signal, and when the output module is reception state, it is low that the transmission state, which enables signal,
Level；
The output end of first NAND gate connects the input of first NOT gate, and the output end of first NOT gate connects
Connect the first input end of second NAND gate and the input of second NOT gate；
Second input of second NAND gate receives the data to be sent of the output driving circuit, described second with
The output end of NOT gate connects the first input end of the circuit of the first multiselect one；Second input of the circuit of the first multiselect one
Connect ground voltage；
The output end of second NOT gate connects the first input end of the 3rd NAND gate；The of 3rd NAND gate
Two inputs receive the data to be sent, and the output end of the 3rd NAND gate connects the first of the circuit of the second multiselect one
Input；The second input connection supply voltage of the circuit of second multiselect one；
Two inputs of the 4th NAND gate are respectively used to receive the output module enable signal and reception state
Enable signal；Wherein, when the output module is reception state, it is high level that the reception state, which enables signal, when described
When output module is transmission state, it is low level that the reception state, which enables signal,；
The output end of 4th NAND gate connects the input of the 3rd NOT gate；The output end of 3rd NOT gate connects
Connect the selection end and the selection end of the circuit of the second multiselect one of the circuit of the first multiselect one；When the electricity of the first multiselect one
The selection termination on road receives low level, and the data that first input end is received are exported by output end, when the electricity of the first multiselect one
The selection termination on road receives high level, and the data that the second input is received are exported by output end；When the electricity of the second multiselect one
The selection termination on road receives low level, and the data that first input end is received are exported by output end, when the electricity of the second multiselect one
The selection termination on road receives high level, and the data that the second input is received are exported by output end；
The input of 4th NOT gate is used to receive the first output conversion circuit enable signal；Wherein, when the first output
When change-over circuit is enabled state, it is high level that first output conversion circuit, which enables signal, when the first output conversion circuit
During for disabled status, it is low level that first output conversion circuit, which enables signal,；
Each first output conversion circuit includes a NAND gate and a level shifting circuit, wherein, should with it is non-
The first input end of door connects the output end of the circuit of the first multiselect one, the second input connection the described 4th of the NAND gate
The output end of NOT gate, the output end of the NAND gate connects the input of the level shifting circuit, and the level shifting circuit is used to adjust
Economize on electricity presses to adapt to external voltage；
The input of 5th NOT gate is used to receive the second output conversion circuit enable signal, the output end of the 5th NOT gate
Connect the input of the 6th NOT gate；Wherein, when the second output conversion circuit is enabled state, the second output conversion
It is high level that circuit, which enables signal, and when the second output conversion circuit is disabled status, second output conversion circuit is enabled
Signal is low level；
Each second output conversion circuit includes a NAND gate and a level shifting circuit, wherein, should with it is non-
The first input end of door connects the output end of the circuit of the second multiselect one, the second input connection the described 6th of the NAND gate
The output end of NOT gate, the output end of the NAND gate connects the input of the level shifting circuit, and the level shifting circuit is used to adjust
Economize on electricity presses to adapt to external voltage；
All PMOSs in each PMOS groups constitute a series circuit, one end connection of the series circuit described the
The negative pole and supply voltage of one diode, the other end of the series circuit connect the positive pole of first diode and described
The negative pole of second diode；In the series circuit, the grid of each PMOS connects the grid tie point of the group；It is each described
The grid tie point of PMOS groups connects the defeated of the level shifting circuit in different first output conversion circuits respectively
Go out end；
All NMOS tubes in each NMOS groups constitute a series circuit, one end connection of the series circuit described the
The positive pole and ground voltage of two diodes, the other end of the series circuit connect the positive pole and described the of first diode
The negative pole of two diodes；In the series circuit, the grid of each NMOS tube connects the grid tie point of the group；Each NMOS
The grid tie point of group connects the output end of the level shifting circuit in different second output conversion circuits respectively；
When the output driving circuit is transmission state, each described level conversion electricity in each described output module
The output end on road is the output end of the output driving circuit；When the output driving circuit is reception state, described in each
The back driving circuit in output module is used for impedance matching.
It is preferred that, each first output conversion circuit and each second output conversion circuit also include a side
Along rate control circuits；The input of the edge rate control circuit connects the NAND gate in the output conversion circuit belonging to it
Output end, the output end of the edge rate control circuit connects the level shifting circuit in the output conversion circuit belonging to it
Input；
Each edge rate control circuit includes the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS
Pipe, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 7th NOT gate and the 8th NOT gate；
The source electrode of first PMOS, the source electrode of the 3rd PMOS, the source electrode connection electricity of the 4th PMOS
Source voltage；The draining of first PMOS, the draining of the 3rd PMOS, the 4th PMOS drain electrode connection it is described
The source electrode of second PMOS；The source electrode of first NMOS tube connects the draining of second NMOS tube, the 3rd NMOS tube
Drain electrode and the 4th NMOS tube drain electrode；The source electrode of second NMOS tube, the source electrode of the 3rd NMOS tube and described
The source electrode connection ground voltage of 4th NMOS tube；Grid, the grid of the second PMOS, the first NMOS of first PMOS
The grid of pipe connects the grid of second NMOS tube, is used as the input of the edge rate control circuit；Described second
The drain electrode of drain electrode connection first NMOS tube of PMOS, is used as the output end of the edge rate control circuit；
The input of 7th NOT gate is used for receiving velocity control signal, and the output end connection of the 7th NOT gate is described
The input of 8th NOT gate, the output end of the 8th NOT gate connects the grid of the 3rd PMOS, the 4th PMOS
Grid, the grid of the grid of the 3rd NMOS tube and the 4th NMOS tube.
It is preferred that, the n is specially 4.
It is preferred that, the n PMOS groups include four PMOSs, i.e. the 5th PMOS, the 6th PMOS, the 7th respectively
PMOS and the 8th PMOS, two PMOSs, i.e. the 9th PMOS and the tenth PMOS, a PMOS, i.e., the 11st
PMOS and a PMOS, i.e. the 12nd PMOS；The n NMOS groups include four NMOS tubes, i.e. the 5th NMOS respectively
Pipe, the 6th NMOS tube, the 7th NMOS tube and the 8th NMOS tube, two NMOS tubes, i.e. the 9th NMOS tube and the tenth NMOS tube, one
NMOS tube, i.e. the 11st NMOS tube and NMOS tube, i.e. the 12nd NMOS tube；
The source electrode of drain electrode connection the 6th PMOS of 5th PMOS, the drain electrode connection of the 6th PMOS
The source electrode of 7th PMOS, the source electrode of drain electrode connection the 8th PMOS of the 7th PMOS, the described 9th
The source electrode of drain electrode connection the tenth PMOS of PMOS, the source electrode of the 5th PMOS connects the 9th PMOS
Source electrode, the source electrode of the 11st PMOS, the source electrode of the 12nd PMOS, supply voltage and first diode
Negative pole；The draining of drain electrode connection the tenth PMOS of 8th PMOS, the drain electrode of the 11st PMOS, institute
State the negative pole of the draining of the 12nd PMOS, the positive pole of first diode and second diode；
The source electrode of 5th NMOS tube connects the drain electrode of the 6th NMOS tube, the source electrode connection of the 6th NMOS tube
The drain electrode of 7th NMOS tube, the source electrode of the 7th NMOS tube connects the drain electrode of the 8th NMOS tube, the described 9th
The source electrode of NMOS tube connects the drain electrode of the tenth NMOS tube, drain electrode connection the 9th NMOS tube of the 5th NMOS tube
Drain electrode, the draining of the 11st NMOS tube, the draining of the 12nd NMOS tube, the negative pole of second diode and described
The positive pole of first diode；The source electrode of 8th NMOS tube connects source electrode, the 11st NMOS of the tenth NMOS tube
The source electrode of pipe, the source electrode of the 12nd NMOS tube, the positive pole of ground voltage and second diode.
It is preferred that, the back driving circuit also includes a NMOS tube and a PMOS, wherein, the grid of the PMOS
The negative pole of first diode, the positive pole of drain electrode connection first diode of the PMOS are connected with source electrode；The NMOS
The grid and source electrode of pipe connect the positive pole of second diode, and the drain electrode of the NMOS tube connects the negative of second diode
Pole.
It is preferred that, the level shifting circuit is used for the IO voltages that the supply voltage is converted to chip.
It is preferred that, the output driving circuit includes 7 output modules.
According to the above-mentioned technical solution, the DDR3 PHY SSTL15 output driving circuits that the present invention is provided include forerunner
Dynamic circuit and back driving circuit, DDR3 PHY SSTL15 data to be sent can be exported by realizing.Also, in the present invention
DDR3 PHY SSTL15 output driving circuits can be respectively at transmission state and reception state, logical when in the state of transmission
Preceding driving circuit output data to be sent are crossed, back driving circuit exports high-impedance state when in reception state, for impedance
Match somebody with somebody.
Brief description of the drawings
The structural representation of the specific embodiment for the output driving circuit that Fig. 1 provides for the present invention；
The structural representation of preceding drive circuit in the output driving circuit that Fig. 2 and Fig. 3 provides for the present invention；
The structural representation for the forward position rate control circuits that Fig. 4 and Fig. 5 provides for the present invention；
The structural representation of back driving circuit in the output driving circuit that Fig. 6 provides for the present invention.
Embodiment
DDR (Double Data Rate, i.e. Double Data Rate synchronous DRAM) 3PHY (Physical
Layer, i.e. physical layer) it is for connection to the indispensable bridge of DDR3SDAM memories and DDR3 storage controls.While PHY's sets
There is provided the industrial interface DDR PHY Interface (DFI) of standard and storage control for meter needs compatibility JESD79-3 standard
It is attached.
DDR3 PHY include DDL (Data Definition Language, i.e. database schema definitional language), PLL
(Phase Locked Loop, i.e. phaselocked loop), transmitter, receiver, SSTL input driving circuits, SSTL output driving circuits
Etc..Wherein, DLL and PLL are mainly used in carrying out the conversion of clock zone, and transmitters and receivers are used to send and receive data,
And the serioparallel exchange of data is realized, and SSTL output driving circuits (also referred to as SSTL output circuits) are mainly used in exporting DDR3
PHY data to be sent.
SSTL 15 is a kind of the more commonly used SSTL interfaces, however, inventor it has been investigated that, in the prior art simultaneously
In the absence of DDR3 PHY SSTL15 output driving circuits.
Therefore, present invention solves the technical problem that being to provide a kind of DDR3 PHY SSTL15 output driving circuits (i.e.
DDR3 PHY SSTL15 output circuits), it can export DDR3 PHY SSTL15 data to be sent to realize.
Referring to Fig. 1, the invention provides the specific embodiment of DDR3 PHY SSTL15 output driving circuits, this implementation
In example, the output driving circuit includes：At least one output module, each described output module parallel connection.Such as Fig. 1
In, thus it is shown that output driving circuit includes the situation of 7 parallel output modules.
The knot of one of output module is only introduced because the circuit of each output module is identical, therefore in the present embodiment
Structure.
Wherein, each output module includes：Preceding drive circuit and back driving circuit.
As shown in Figures 2 and 3, preceding drive circuit includes：It is first NOT gate d1, the second NOT gate d2, the 3rd NOT gate d3, the 4th non-
Door d4, the 5th NOT gate d5, the 6th NOT gate d6, the first NAND gate c1, the second NAND gate c2, the 3rd NAND gate c3, the 4th NAND gate
C4, the circuit mux1 of the first multiselect one, mux2, n the first output conversion circuits of one circuit of the second multiselect and n second output conversion
Circuit；n≥1.In fig. 2, using n as 4, that is, including four the first output conversion circuits and four second output conversion electricity
Exemplified by road.
First NAND gate c1 two inputs are respectively used to receive output module enable signal EN_STR and transmission state
Enable signal OUT_EN.Wherein, when output module is enabled state, it is high level that output module, which enables signal EN_STR, when
When output module is disabled status, it is low level that output module, which enables signal EN_STR,；When output module is transmission state, hair
It is high level to send state to enable signal OUT_EN, and when output module is reception state, transmission state enables signal OUT_EN and is
Low level.
It should be noted that in the present embodiment, each output module has a module to enable signal EN_STR, when
When EN_STR is high level, the output module is in opening, is opened so as to control to be in whole output driving circuit
Open the quantity of the output module of state.
First NAND gate c1 output end connects the first NOT gate d1 input, the first NOT gate d1 output end connection second
The input of NAND gate c2 first input end and the second NOT gate d2.
Second NAND gate c2 the second input receives the data DATA to be sent of the output driving circuit of the present embodiment, the
Two NAND gate c2 output end connection the first multiselect one circuit mux1 first input end；The second of the circuit mux1 of first multiselect one
Input connection ground voltage VSS.
Second NOT gate d2 output end connects the 3rd NAND gate c3 first input end.3rd NAND gate c3 the second input
End receives the data DATA to be sent of the output driving circuit of the present embodiment, and the 3rd NAND gate c3 output end connects the second multiselect
One circuit mux2 first input end；The circuit mux2 of second multiselect one the second input connection supply voltage VDD.
4th NAND gate c4 two inputs are respectively used to receive output module enable signal EN_STR and reception state
Enable signal CAL_EN；Wherein, when output module is reception state, it is high level that reception state, which enables signal CAL_EN, when
When output module is transmission state, it is low level that reception state, which enables signal CAL_EN,.
4th NAND gate c4 output end connects the 3rd NOT gate d3 input；3rd NOT gate d3 output end output signal
MUX_EN, and output end connection the first multiselect one circuit mux1 selection end and the circuit mux2 of the second multiselect one selection
End；When the circuit mux1 of the first multiselect one selection termination receives low level, pass through the circuit mux1 of the first multiselect one output end
The data that first input end is received are exported, that is, have selected first input end as input.When the circuit of the first multiselect one
Mux1 selection termination receives high level, and the number that the second input is received is exported by the circuit mux1 of the first multiselect one output end
According to, that is, the second input is have selected as input.Low level is received when the circuit mux2 of the second multiselect one selection is terminated,
The data that first input end is received are exported by the circuit mux2 of the second multiselect one output end, that is, have selected first input end
It is used as input.When the circuit mux2 of the first multiselect one selection termination receives high level, pass through the circuit mux2's of the second multiselect one
Output end exports the data that the second input is received, that is, have selected the second input as input.
4th NOT gate d4 input be used for receive the first output conversion circuit enable signal PU_ODT, due in Fig. 2 with n
Exemplified by 4, therefore PU_ODT is specially PU_ODT<3:0>；Wherein, when the first output conversion circuit is enabled state, first
It is high level that output conversion circuit, which enables signal PU_ODT, and when the first output conversion circuit is disabled status, the first output turns
It is low level to change circuit and enable signal PU_ODT.
Each first output conversion circuit includes a NAND gate and a level shifting circuit, wherein, the NAND gate
First input end connection the first multiselect one circuit mux1 output end, the second input of the NAND gate connects the 4th NOT gate d4's
Output end, the output end of the NAND gate connects the input of the level shifting circuit.For example include four first outputs in Fig. 2 altogether
Change-over circuit, this four first output conversion circuits include NAND gate c5 and level shifting circuit 1, NAND gate c6 and level respectively
Change-over circuit 2, NAND gate c7 and level shifting circuit 3, NAND gate c8 and level shifting circuit 4.Wherein, NAND gate c5, with it is non-
Door c6, NAND gate c7 and NAND gate c8 first input end are all connected with the circuit mux1 of the first multiselect one output end, NAND gate c5,
NAND gate c6, NAND gate c7 and NAND gate c8 the second input connect the first output conversion circuit and enable signal PU_ODT respectively
<0>、PU_ODT<1>、PU_ODT<2>And PU_ODT<3>.Wherein, the level shifting circuit is used to adjust voltage to adapt to outside
Voltage, in fact, level shifting circuit can (input the supply voltage VDD IO for being converted to VDDIO voltages, i.e. chip defeated
Go out) voltage.Generally internal power source voltage VDD can be lower than outside VDDIO voltages, thus level shifting circuit can be by
Low voltage transition is high voltage.
5th NOT gate d5 input be used for receive the second output conversion circuit enable signal PD_ODT, due in Fig. 2 with n
Exemplified by 4, therefore PD_ODT is specially PD_ODT<3:0>.5th NOT gate d5 output end connects the 6th NOT gate d6 input；
Wherein, when the second output conversion circuit is enabled state, it is high level that the second output conversion circuit, which enables signal, when second defeated
When going out change-over circuit for disabled status, it is low level that the second output conversion circuit, which enables signal,.
Each second output conversion circuit includes a NAND gate and a level shifting circuit, wherein, the NAND gate
First input end connection the second multiselect one circuit mux2 output end, the second input of the NAND gate connects the 6th NOT gate d6's
Output end, the output end of the NAND gate is connected includes four second outputs altogether in the input of the level shifting circuit, such as Fig. 2
Change-over circuit, this four second output conversion circuits include NAND gate c9 and level shifting circuit 5, NAND gate c10 and electricity respectively
Flat change-over circuit 6, NAND gate c11 and level shifting circuit 7, NAND gate c12 and level shifting circuit 8.Wherein, NAND gate c9,
NAND gate c10, NAND gate c11 and NAND gate c12 first input end are all connected with the circuit mux2 of the second multiselect one output end, with
NOT gate c9, NAND gate c10, NAND gate c11 and NAND gate c12 the second input connect the second output conversion circuit enable respectively
Signal PD_ODT<0>、PD_ODT<1>、PD_ODT<2>And PD_ODT<3>.Wherein, the level shifting circuit is used to adjust voltage
To adapt to external voltage, in fact, level shifting circuit can be that supply voltage VDD is converted into VDDIO voltages, i.e. chip
IO voltages.Generally internal power source voltage VDD can be lower than outside VDDIO voltages, thus level shifting circuit can be by
Low voltage transition is high voltage.
As shown in fig. 6, back driving circuit includes：N NMOS group, n PMOS group, the first diode ESD1 and the two or two pole
Pipe ESD2；Each NMOS groups include at least one NMOS tube, and each PMOS groups include at least one PMOS.
All PMOSs in each PMOS groups constitute a series circuit, one end connection the one or two of the series circuit
Pole pipe ESD1 negative pole and supply voltage, the other end of the series circuit connects the first diode ESD1 positive pole and second
Diode ESD2 negative pole；In the series circuit, the grid of each PMOS is connected to the grid tie point in the group；Each
The grid tie point of PMOS groups connects the output end of the level shifting circuit in the first different output conversion circuits respectively.
All NMOS tubes in each NMOS groups constitute a series circuit, one end connection the two or two of the series circuit
Pole pipe ESD2 positive pole and ground voltage, the other end of the series circuit connects the first diode ESD1 and the second diode
ESD2 negative pole；In the series circuit, the grid of each NMOS tube to the grid tie point in the group；The grid of each NMOS groups
Tie point connects the output end of the level shifting circuit in the second different output conversion circuits respectively.
Wherein, the first diode ESD1 and the second diode ESD2 common port are the output end of back driving circuit.
In figure 6, it is specially a kind of 4 preferred embodiment to be actually illustrated that n.In this preferred embodiment, include altogether
Four NMOS groups and four PMOS groups, wherein, four PMOS groups include respectively four PMOSs (P5, P6, P7 and P8), two
PMOS (P9 and P10), a PMOS (P11) and a PMOS (P12)；Four NMOS groups include four NMOS tubes respectively
(N5, N6, N7 and N8), two NMOS tubes (N9 and N10), a NMOS tube (N11) and a NMOS tube (N12).
Wherein, PMOS P5 drain electrode connection PMOS P6 source electrode, PMOS P6 drain electrode connection PMOS P7 source
Pole, PMOS P7 drain electrode connection PMOS P8 source electrode, PMOS P9 drain electrode connection PMOS P10 source electrode, PMOS
P5 source electrode connection PMOS P9 source electrode, PMOS P11 source electrode, PMOS P12 source electrode, supply voltage VDD and the
One diode ESD1 negative pole.PMOS P8 drain electrode connection PMOS P10 drain electrode, PMOS P11 drain electrode, PMOS
P12 drain electrode and the first diode ESD1 positive pole and the second diode ESD2 negative pole.PMOS P5 grid, PMOS P7
Grid, PMOS P7 grid and PMOS P8 grid be all connected with level shifting circuit in the first output conversion circuit
The output signal PU_LVL of output end<3>.PMOS P9 grid and PMOS P10 grid are all connected with the first output conversion electricity
The output signal PU_LVL of the output end of level shifting circuit in road<2>, PMOS P11 grid connection the first output conversion
The output signal PU_LVL of the output end of level shifting circuit in circuit<1>, the PMOS P12 output turn of grid connection first
The output signal PU_LVL of the output end of the level shifting circuit changed in circuit<0>.
NMOS tube N5 source electrode connection NMOS tube N6 drain electrode, NMOS tube N6 source electrode connection NMOS tube N7 drain electrode,
NMOS tube N7 source electrode connection NMOS tube N8 drain electrode, NMOS tube N9 source electrode connection NMOS tube N10 drain electrode, NMOS tube N5's
Drain electrode connection NMOS tube N9 drain electrode, NMOS tube N11 drain electrode, NMOS tube N12 drain electrode, the second diode ESD2 negative pole and
First diode ESD1 positive pole.NMOS tube N8 source electrode connection NMOS tube N10 source electrode, NMOS tube N11 source electrode, NMOS tube
The positive pole of N12 source electrode, ground voltage VSS and the second diode ESD2.NMOS tube N5 grid, NMOS tube N7 grid,
NMOS tube N7 grid and NMOS tube N8 grid are all connected with the output end of the level shifting circuit in the second output conversion circuit
Output signal PD_LVL<3>.NMOS tube N9 grid and NMOS tube N10 grid are all connected with the second output conversion circuit
The output signal PD_LVL of the output end of level shifting circuit<2>, NMOS tube N11 grid connected in the second output conversion circuit
Level shifting circuit output end output signal PD_LVL<1>, NMOS tube N12 grid the second output conversion circuit of connection
In level shifting circuit output end output signal PD_LVL<0>.
Optionally, as shown in fig. 6, back driving circuit also includes a NMOS tube (N13) and a PMOS (P13), its
In, PMOS P13 grid and source electrode connect the first diode ESD1 negative pole, and PMOS P13 drain electrode connects the one or two pole
Pipe ESD1 positive pole.NMOS tube N13 grid and source electrode connects the second diode ESD1 positive pole, and NMOS tube N13 drain electrode connects
Connect the second diode ESD2 negative pole.
In the present embodiment, when output driving circuit is transmission state, it is high electricity that the state that sends, which enables signal OUT_EN,
Flat, it is low level that reception state, which enables signal CAL_EN, now, and the 3rd NOT gate d3 output signal MUX_EN is low level, the
The circuit mux1 of one multiselect one and the circuit mux2 of the second multiselect one select data DATA to be sent for input signal, and now each
The output end of each level shifting circuit in individual output module is the output end of the output driving circuit of the present embodiment, the output
End output data DATA to be sent.And when output driving circuit is reception state, it is low that the state that sends, which enables signal OUT_EN,
Level, it is high level that reception state, which enables signal CAL_EN, now, and MUX_EN is high level, the circuit mux1 of the first multiselect one and
The circuit mux2 of second multiselect one selects ground voltage VSS and supply voltage VDD to be input signal respectively, now each level conversion electricity
The output signal on road can drag down the NMOS tube in the NMOS groups in back driving circuit, and the PMOS in PMOS groups is drawn high, therefore,
Each NMOS group and PMOS groups are turned on, now the back driving circuit output high-impedance state in each output module, for impedance matching.
According to the above-mentioned technical solution, before the DDR3 PHY SSTL15 output driving circuits that the present embodiment is provided include
Drive circuit and back driving circuit, DDR3 PHY SSTL15 data to be sent can be exported by realizing.Also, in the present invention
DDR3 PHY SSTL15 output driving circuits can be respectively at transmission state and reception state, when in send state when
By preceding driving circuit output data to be sent, back driving circuit exports high-impedance state when in reception state, for impedance
Matching.
The present embodiment has not only filled up blank at present in DDR3 PHY SSTL15 output driving circuit design aspects, and
And have further the advantage that：
1st, DDR3 SSTL15 output driving circuits need to realize that transmission rate is 1600MHZ, in the state of such high speed
Under, power consumption control becomes particularly important.And the output driving circuit in the present embodiment not only meets the requirement of DDR3 standards, speed
1600MHZ is reached, good physical characteristic is realized, the eye pattern that emulation testing goes out meets industry eye pattern standard.
2nd, the output driving circuit in the present embodiment, is also achieved in back driving circuit by PMOS groups and NMOS groups
ESD is protected, this that area can be saved by the way of metal-oxide-semiconductor compared to existing ESD protections.
3rd, the output driving circuit of the present embodiment, has given up the individually designed impedance matching circuit of needs, but driven by after
Circuit it is compatible under reception state be impedance matching circuit, this way saves the area and power consumption of chip.
4th, all control circuits have been put into preceding drive circuit by the output driving circuit of the present embodiment, and such way can make
Obtaining the design of back driving circuit becomes succinct, effectively saves chip area and design complexities.
In the present embodiment, edge rate control circuit can also be increased, so as to be controlled to data transmission bauds.Specifically
Ground, each first output conversion circuit and each second output conversion circuit also include an edge rate control electricity
Road；The input of the edge rate control circuit connects the output end of the NAND gate in the output conversion circuit belonging to it, should
The output end of edge rate control circuit connects the input of the level shifting circuit in the output conversion circuit belonging to it.
Because the structure of each edge rate control circuit is identical, therefore one of edge rate control is only introduced below
The structure of circuit.
As shown in Figure 4 and Figure 5, each edge rate control circuit includes the first PMOS P1, the second PMOS P2, the 3rd
PMOS P3, the 4th PMOS P4, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4,
Seven NOT gate d7 and the 8th NOT gate d8.
First PMOS P1 source electrode, the 3rd PMOS P3 source electrode, the 4th PMOS P4 source electrode connection supply voltage
VDD；First PMOS P1 drain electrode, the 3rd PMOS P3 drain electrode, the 4th PMOS P4 drain electrode connects the second PMOS P2
Source electrode；First NMOS tube N1 source electrode connects the second NMOS tube N2 drain electrode, the 3rd NMOS tube N3 drain electrode and the 4th NMOS
Pipe N4 drain electrode；The source electrode connection ground electricity of second NMOS tube N2 source electrode, the 3rd NMOS tube N3 source electrode and the 4th NMOS tube N4
Press VSS；First PMOS P1 grid, the second PMOS P2 grid, the first NMOS tube N1 grid connect the second NMOS tube
N2 grid, is used as the input of the edge rate control circuit；Second PMOS P2 the first NMOS tube N1's of drain electrode connection
Drain electrode, is used as the output end of edge rate control circuit.
7th NOT gate d7 input is used for receiving velocity control signal SR<1:0>, the 7th NOT gate d7 output end connection
8th NOT gate d8 input.8th NOT gate d8 output end connects the 3rd PMOS P3 grid, the 4th PMOS P4 grid
The grid of pole, the 3rd NMOS tube N3 grid and the 4th NMOS tube N4.The signal of 8th NOT gate d8 outputs is SRP<1:0>And SRN
<1:0>.In Fig. 4, the 3rd PMOS P3 grid connection speed control signal SRP<1>, the 4th PMOS P4 grid connection
Rate controlled signal SRP<0>.3rd NMOS tube N3 grid connection speed control signal SRN<1>, the 4th NMOS tube N4 grid
Pole connection speed control signal SRN<0>.
If signal rate is transmitted the too fast signal that may result in and rebounded on the transmission line.Work as SR<1>It is right during for high level
The SRP answered<1>And SRN<1>For high level；Work as SR<0>During for high level, corresponding SRP<0>And SRN<0>For high level.Cause
This adds the quantity of pull-up PMOS and pull-down NMOS pipe, increases electric current, such edge is just when SR signals are high level
Meeting steepening, corresponding transmission rate will accelerate.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (7)
1. a kind of DDR3 PHY SSTL15 output driving circuits, it is characterised in that the output driving circuit includes：At least one
Individual output module, each described output module parallel connection；
Wherein, each output module includes：Preceding drive circuit and back driving circuit；The preceding drive circuit includes：First
NOT gate, the second NOT gate, the 3rd NOT gate, the 4th NOT gate, the 5th NOT gate, the 6th NOT gate, the first NAND gate, the second NAND gate, the 3rd
NAND gate, the 4th NAND gate, the circuit of the first multiselect one, the circuit of the second multiselect one, n the first output conversion circuits and n individual second
Output conversion circuit；n≥1；The back driving circuit includes：N NMOS group, n PMOS group, the first diode and the two or two pole
Pipe；Each NMOS groups include at least one NMOS tube, and each PMOS groups include at least one PMOS；
Two inputs of first NAND gate are respectively used to receive output module enable signal and transmission state enables signal；
Wherein, when the output module is enabled state, it is high level that the output module, which enables signal, when the output module is
During disabled status, it is low level that the output module, which enables signal,；When the output module is transmission state, the transmission shape
It is high level that state, which enables signal, and when the output module is reception state, it is low level that the transmission state, which enables signal,；
The output end of first NAND gate connects the input of first NOT gate, the output end connection institute of first NOT gate
State the first input end of the second NAND gate and the input of second NOT gate；
Second input of second NAND gate receives the data to be sent of the output driving circuit, second NAND gate
Output end connect the first input end of the circuit of the first multiselect one；The second input connection of the circuit of first multiselect one
Ground voltage；
The output end of second NOT gate connects the first input end of the 3rd NAND gate；The second of 3rd NAND gate is defeated
Enter end and receive the data to be sent, the output end of the 3rd NAND gate connects the first input of the circuit of the second multiselect one
End；The second input connection supply voltage of the circuit of second multiselect one；
Two inputs of the 4th NAND gate are respectively used to receive the output module enable signal and reception state is enabled
Signal；Wherein, when the output module is reception state, it is high level that the reception state, which enables signal, when the output
When module is transmission state, it is low level that the reception state, which enables signal,；
The output end of 4th NAND gate connects the input of the 3rd NOT gate；The output end connection institute of 3rd NOT gate
State the selection end and the selection end of the circuit of the second multiselect one of the circuit of the first multiselect one；When the circuit of the first multiselect one
Selection termination receives low level, the data that first input end is received is exported by output end, when the circuit of the first multiselect one
Selection termination receives high level, and the data that the second input is received are exported by output end；When the circuit of the second multiselect one
Selection termination receives low level, the data that first input end is received is exported by output end, when the circuit of the second multiselect one
Selection termination receives high level, and the data that the second input is received are exported by output end；
The input of 4th NOT gate is used to receive the first output conversion circuit enable signal；Wherein, when the first output conversion
When circuit is enabled state, it is high level that first output conversion circuit, which enables signal, when the first output conversion circuit is taboo
When using state, it is low level that first output conversion circuit, which enables signal,；
Each first output conversion circuit includes a NAND gate and a level shifting circuit, wherein, the NAND gate
First input end connects the output end of the circuit of the first multiselect one, and the second input of the NAND gate connects the 4th NOT gate
Output end, the output end of the NAND gate connects the input of the level shifting circuit, and the level shifting circuit is used to adjust electricity
Press to adapt to external voltage；
The input of 5th NOT gate is used to receive the second output conversion circuit enable signal, the output end connection of the 5th NOT gate
The input of 6th NOT gate；Wherein, when the second output conversion circuit is enabled state, second output conversion circuit
Enable signal is high level, and when the second output conversion circuit is disabled status, second output conversion circuit enables signal
For low level；
Each second output conversion circuit includes a NAND gate and a level shifting circuit, wherein, the NAND gate
First input end connects the output end of the circuit of the second multiselect one, and the second input of the NAND gate connects the 6th NOT gate
Output end, the output end of the NAND gate connects the input of the level shifting circuit, and the level shifting circuit is used to adjust electricity
Press to adapt to external voltage；
All PMOSs in each PMOS groups constitute a series circuit, one end connection the described 1st of the series circuit
The negative pole and supply voltage of pole pipe, the other end of the series circuit connect the positive pole and described second of first diode
The negative pole of diode；In the series circuit, the grid of each PMOS connects the grid tie point of the group；Each PMOS groups
Grid tie point connect the output end of the level shifting circuit in different first output conversion circuits respectively；
All NMOS tubes in each NMOS groups constitute a series circuit, one end connection the described 2nd 2 of the series circuit
The positive pole and ground voltage of pole pipe, the other end of the series circuit connect the positive pole and the described 2nd 2 of first diode
The negative pole of pole pipe；In the series circuit, the grid of each NMOS tube connects the grid tie point of the group；Each NMOS groups
Grid tie point connects the output end of the level shifting circuit in different second output conversion circuits respectively；
When the output driving circuit is transmission state, each level shifting circuit in each described output module
Output end is the output end of the output driving circuit；When the output driving circuit is reception state, each described output
The back driving circuit in module is used for impedance matching.
2. output driving circuit according to claim 1, it is characterised in that each first output conversion circuit and every
Individual second output conversion circuit also includes an edge rate control circuit；The input of the edge rate control circuit connects
The output end of the NAND gate in the output conversion circuit belonging to it is connect, the output end of the edge rate control circuit connects its institute
The input of level shifting circuit in the output conversion circuit belonged to；
Each edge rate control circuit include the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS,
First NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 7th NOT gate and the 8th NOT gate；
The source electrode of first PMOS, the source electrode of the 3rd PMOS, the source electrode connection power supply electricity of the 4th PMOS
Pressure；The draining of first PMOS, the draining of the 3rd PMOS, the drain electrode connection described second of the 4th PMOS
The source electrode of PMOS；The source electrode of first NMOS tube connects the draining of second NMOS tube, the leakage of the 3rd NMOS tube
Pole and the drain electrode of the 4th NMOS tube；The source electrode and the described 4th of the source electrode of second NMOS tube, the 3rd NMOS tube
The source electrode connection ground voltage of NMOS tube；The grid of first PMOS, the grid of the second PMOS, first NMOS tube
Grid connects the grid of second NMOS tube, is used as the input of the edge rate control circuit；Second PMOS
Drain electrode connection first NMOS tube drain electrode, be used as the output end of the edge rate control circuit；
The input of 7th NOT gate is used for receiving velocity control signal, the output end connection the described 8th of the 7th NOT gate
The input of NOT gate, the output end of the 8th NOT gate connects grid, the grid of the 4th PMOS of the 3rd PMOS
The grid of pole, the grid of the 3rd NMOS tube and the 4th NMOS tube.
3. output driving circuit according to claim 1 or 2, it is characterised in that the n is specially 4.
4. output driving circuit according to claim 3, it is characterised in that the n PMOS groups include four respectively
PMOS, i.e. the 5th PMOS, the 6th PMOS, the 7th PMOS and the 8th PMOS, two PMOSs, i.e. the 9th PMOS
With the tenth PMOS, a PMOS, i.e. the 11st PMOS and a PMOS, i.e. the 12nd PMOS；The n
NMOS groups include respectively four NMOS tubes, i.e. the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube and the 8th NMOS tube, two
NMOS tube, i.e. the 9th NMOS tube and the tenth NMOS tube, a NMOS tube, i.e. the 11st NMOS tube and NMOS tube, the i.e. the tenth
Two NMOS tubes；
The source electrode of drain electrode connection the 6th PMOS of 5th PMOS, the drain electrode connection of the 6th PMOS is described
The source electrode of 7th PMOS, the source electrode of drain electrode connection the 8th PMOS of the 7th PMOS, the 9th PMOS
Drain electrode connection the tenth PMOS source electrode, the source electrode of the 5th PMOS connect the source electrode of the 9th PMOS,
The source electrode of 11st PMOS, the source electrode of the 12nd PMOS, supply voltage and first diode it is negative
Pole；The draining of drain electrode connection the tenth PMOS of 8th PMOS, the draining of the 11st PMOS, described the
The negative pole of the draining of 12 PMOSs, the positive pole of first diode and second diode；
The source electrode of 5th NMOS tube connects the drain electrode of the 6th NMOS tube, and the source electrode connection of the 6th NMOS tube is described
The drain electrode of 7th NMOS tube, the source electrode of the 7th NMOS tube connects the drain electrode of the 8th NMOS tube, the 9th NMOS tube
Source electrode connect the drain electrode of the tenth NMOS tube, the drain electrode of drain electrode connection the 9th NMOS tube of the 5th NMOS tube,
The draining of 11st NMOS tube, the draining of the 12nd NMOS tube, the negative pole of second diode and described first
The positive pole of diode；The source electrode of 8th NMOS tube connects the source electrode of the tenth NMOS tube, the 11st NMOS tube
Source electrode, the source electrode of the 12nd NMOS tube, the positive pole of ground voltage and second diode.
5. output driving circuit according to claim 1 or 2, it is characterised in that the back driving circuit also includes one
NMOS tube and a PMOS, wherein, the grid and source electrode of the PMOS connect the negative pole of first diode, the PMOS
Drain electrode connection first diode positive pole；The grid and source electrode of the NMOS tube connect the positive pole of second diode,
The negative pole of drain electrode connection second diode of the NMOS tube.
6. output driving circuit according to claim 1 or 2, it is characterised in that the level shifting circuit is used for institute
State the IO voltages that supply voltage is converted to chip.
7. output driving circuit according to claim 1 or 2, it is characterised in that the output driving circuit is defeated including 7
Go out module.
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| CN201410589755.XA CN104333369B (en) | 2014-07-08 | 2014-10-28 | A kind of DDR3 PHY SSTL15 output driving circuits |
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| CN201410589755.XA CN104333369B (en) | 2014-07-08 | 2014-10-28 | A kind of DDR3 PHY SSTL15 output driving circuits |
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| CN102522113A (en) * | 2011-09-28 | 2012-06-27 | 华为技术有限公司 | SDRAM bridge circuit |
| CN203658909U (en) * | 2013-12-04 | 2014-06-18 | 安徽虹庄微电子有限公司 | USB3.0 FPGA development board |
| CN103871474A (en) * | 2012-12-14 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Read operation control signal generator and operating method thereof |
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| US7664216B2 (en) * | 2004-08-05 | 2010-02-16 | Micron Technology, Inc. | Digital frequency locked delay line |
| KR100714874B1 (en) * | 2005-09-27 | 2007-05-07 | 삼성전자주식회사 | Delay line circuit having adjustable delay step and delay cell for the same |
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| CN102522113A (en) * | 2011-09-28 | 2012-06-27 | 华为技术有限公司 | SDRAM bridge circuit |
| CN103871474A (en) * | 2012-12-14 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Read operation control signal generator and operating method thereof |
| CN203658909U (en) * | 2013-12-04 | 2014-06-18 | 安徽虹庄微电子有限公司 | USB3.0 FPGA development board |
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