CN104298174A - Motion control card, system and method for detecting and comparing tracks on basis of PCIe - Google Patents
Motion control card, system and method for detecting and comparing tracks on basis of PCIe Download PDFInfo
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- CN104298174A CN104298174A CN201410502309.0A CN201410502309A CN104298174A CN 104298174 A CN104298174 A CN 104298174A CN 201410502309 A CN201410502309 A CN 201410502309A CN 104298174 A CN104298174 A CN 104298174A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
- G05B19/414—Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
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Abstract
The invention discloses a motion control card, system and method for detecting and comparing tracks on the basis of PCIe. The motion control card and system comprise an FPGA, an optical coupling isolation circuit, a PCIE interface and a power supply. The optical coupling isolation circuit inputs data signals into the FPGA. The PCIE interface is connected to the FPGA. The power supply is connected to the FPGA. The method comprises the steps that the FPGA directly collects actual output signals of motion board cards in a moving process and stores the signals in an FIFO opened up in the FPGA; the FPGA uploads the collected actual output signals to a memory of a host computer through the PCIE interface; errors are determined; comparison and correction are carried out, and finally sample data are identical with original data through repeated modification, operation and check, and a successive approach process. The speed fitted curve of the actual output is obtained through sampling on the actual output of the motion board cards and processing on sampling data, quantitative analysis is carried out on the fitted curve and a speed mode requested by a user, and whether a jumping phenomenon exists or not can be checked out conveniently, and the user is reminded to correct loopholes in an algorithm.
Description
Technical field
The present invention relates to automatic control technology field, specifically, is that the track of Based PC Ie detects the motion control card and method that compare.
Background technology
Directly workpiece is processed for exporting " process data " after the treated device process of movement locus in current control system, because track handled in actual condition is various, may there is saltus step because of unkownable factors in machining locus, affect processing effect, causes waste product.
Middle and high end general controls card basic framework is that DSP+FPGA mode realizes on the market at present in addition, and DSP is responsible for parsing and the speed planning of processing graphic pattern, and FPGA is responsible for the exercise data of DSP being converted into actual pulse and exports.Due to the process errors of digital signal and the difference of each wiring board, the ideal curve error that the pulsating wave frequency of actual output and user can be caused to set is too large, namely also user sets process velocity there is any discrepancy, especially in variable motion, due to the data prediction error of calculation, acceleration and speed flex point in motion process can be caused to occur saltus step, be reacted to final driving and can produce impact in motion process, affect processing effect.
The normal machining locus detecting system that adopts is collected " process data " before reality is to work pieces process at present, judge whether to occur saltus step, avoid directly on workpiece, trying processing and cause waste, but the machining locus detecting system that prior art uses adopts the special equipment that arranges to read related data from control card, need special external inspection equipment, tested by oscillograph, need to rely on human eye to differentiate the quality of operation curve, accuracy is not high.
Summary of the invention
The track of Based PC Ie is the object of the present invention is to provide to detect the motion control card, the system and method that compare, by sampling to the actual output of motion board, sampled data is processed, obtain the actual velocity fitting curve exported, the velocity mode that this matched curve requires with user is carried out quantitative analysis, can check out whether there is " saltus step " phenomenon easily, the leak on reminding user correction algorithm or other problems.
The present invention is achieved through the following technical solutions: the track of Based PC Ie detects the motion control card compared, comprise FPGA, optical coupling isolation circuit, PCIE interface and power supply, the data-signal of motion board to be tested adopts the mode of optically-coupled Isolation input to input in FPGA by described optical coupling isolation circuit, described PCIE interface connects FPGA, and described power supply connects FPGA.
Further, to better implement the present invention, also comprise pilot lamp, described pilot lamp connects FPGA.
Further, to better implement the present invention, input filter circuit, pulse acquisition circuit, data-carrier store, data interaction circuit, RAM is provided with in described FPGA, described optical coupling isolation circuit connects input filter circuit, described input filter circuit connects pulse acquisition circuit, described pulse acquisition circuit is connection data storer and data interaction circuit respectively, and described RAM is connection data storer and data interaction circuit respectively, and described data interaction circuit connects PCIE interface.
Further, to better implement the present invention, the master chip of described FPGA adopts XC6SLX45T.
The track detecting system of Based PC Ie, the track comprising Based PC Ie detects motion control card, main frame, motion board and the raw data source of comparing, described main frame is by the mutual circuit of PCIE interfacing data, described motion board connects main frame respectively, described maneuvering board cartoon crosses optical coupling isolation circuit by output Puled input to be tested in FPGA, be loaded with data acquisition system (DAS), data conversion system, data simulation system and data analysis system in described main frame, raw data is loaded in main frame by described raw data source.
The track of Based PC Ie detects the method compared, and comprises the following steps:
Steps A, FPGA directly gather real output signal in motion board motion process, are stored in and open up in the FIFO of FPGA inside;
The real output signal that steps A is gathered by the PCIE bus on PCIE interface by step B, FPGA is uploaded to host memory;
In step C, data conversion system in main frame, the data be stored in host memory are converted to the Velocity-time value table of collecting sample, and the raw data actual computation of originating provided by raw data the Velocity-time value table of complete operation, the Velocity-time value table of collecting sample determines error with carrying out contrast in the data acquisition system (DAS) of Velocity-time value table in main frame of complete operation, data conversion system, data simulation system, data analysis system;
Step D, determine error after readjust the speed of motion board, and repeat steps A, step B, step C, carry out sampling contrast and revise, by repeatedly revising computing and checking, the process of Approach by inchmeal, finally reach sampled notebook data identical with raw data, do one's utmost to reduce error, ensure that the perfection of motion board runs.
Further, described method to better implement the present invention, comprises the following steps:
1), FPGA directly to gather in motion board motion process the actual pulsewidth and the cycle parameter that export pulse, is stored in and opens up in the FIFO of FPGA inside;
2), the pulsewidth gathered in motion process and cycle data are uploaded to host memory by the PCIE bus on PCIE interface by FPGA;
3) in the data conversion system, in main frame, the data be stored in host memory are converted to the Velocity-time value table of collecting sample, and the raw data actual computation of originating provided by raw data the Velocity-time value table of complete operation, the Velocity-time value table of collecting sample determines error with carrying out contrast in the data acquisition system (DAS) of Velocity-time value table in main frame of complete operation, data conversion system, data simulation system, data analysis system;
4) speed of motion board is readjusted after, determining error, and repeat step 1), step 2), step 3), carry out sampling contrast and revise, by repeatedly revising computing and checking, the process of Approach by inchmeal, finally reach sampled notebook data identical with raw data, do one's utmost to reduce error, ensure that the perfection of motion board runs.
Further, described method to better implement the present invention, the realization of described step 3) specifically divides the following two kinds mode:
3.1), to the Velocity-time value table of collecting sample and Velocity-time value table two group data described point on time shaft identical point of complete operation, two curve movements are drawn out;
3.2), by the velocity amplitude of raw data and the velocity amplitude size of collecting sample in contrast synchronization motor point, appearance " error " part is indicated after exceeding setting range, concrete grammar is as follows: the error threshold values arranging test data and reference data, on a timeline, when certain point tolerance exceedes this threshold values, mark position and the velocity information in this motor point.
Further, described method to better implement the present invention, the realization of described step C specifically divides the following two kinds mode:
C.1), to the Velocity-time value table of collecting sample and Velocity-time value table two group data described point on time shaft identical point of complete operation, two curve movements are drawn out;
C.2), by the velocity amplitude in the raw data in contrast synchronization motor point and the velocity amplitude size of collecting sample, appearance " error " part is indicated after exceeding setting range, concrete grammar is as follows: the error threshold values arranging test data and reference data, on a timeline, when certain point tolerance exceedes this threshold values, mark position and the velocity information in this motor point.
The present invention compared with prior art, has the following advantages and beneficial effect:
(1) the present invention is by sampling to the actual output of motion board, sampled data is processed, obtain the actual velocity fitting curve exported, the velocity mode that this matched curve requires with user is carried out quantitative analysis, can check out whether there is " saltus step " phenomenon easily, the leak on reminding user correction algorithm or other problems.
(2) track of Based PC Ie of the present invention detects the motion control card compared, FPGA is adopted to carry out image data caching process, because the high speed of FPGA, high reliability communicate with PCIe, the track improving Based PC Ie of the present invention detects speed and the reliability of the motion control card compared.
(3) configuration circuit of the present invention, increases the number of resources of fpga chip further, thus improves data processing amount.
(4) the present invention adopts PCIE to communicate and can provide higher transmission data and quality.
(5) the track detecting system of Based PC Ie of the present invention, completes the process to sampled data, obtains the actual velocity fitting curve exported, the velocity mode that this matched curve requires with user is carried out quantitative analysis; To track fitting, the analysis of organizing preprocessed signal and actual acquisition signal more.
(6) track of Based PC Ie of the present invention detects the method compared, adopt simulation process technology, automatically collection, conversion, analytical technology, to track fitting, the analysis of organizing preprocessed signal and actual acquisition signal more, reach the directly perceived object accurately judged, and leak on automatically prompting user correction algorithm or other problems.
Accompanying drawing explanation
The track of Fig. 1 Based PC Ie of the present invention detects the circuit diagram of the motion control card compared.
Fig. 2 is the circuit diagram of the track detecting system of Based PC Ie of the present invention.
Fig. 3 is the track comparison diagram of arc-shaped.
Fig. 4 is the track comparison diagram of linearity.
Fig. 5 is that sampling error analyzes diagram.
Embodiment
The applicant to identify oneself in technical field technician in conjunction with existing known technology, and can realize the present invention according to the content disclosed in present specification.
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment 1:
The track of Based PC Ie detects the motion control card compared, as shown in Figure 1 and Figure 2, comprise FPGA, optical coupling isolation circuit, PCIE interface and power supply, the data-signal of motion board to be tested adopts the mode of optically-coupled Isolation input to input in FPGA by described optical coupling isolation circuit, described PCIE interface connects FPGA, and described power supply connects FPGA.
Maneuvering board to be tested is stuck in and carries out in the course of work, form real output signal (axle Puled input and direction of principal axis input), real output signal carries out coupling by photoelectric isolating circuit and is input in FPGA, filtering, data acquisition, data storage is completed in FPGA, interrupt notification PC is produced when RAM is full, PC reads the data in RAM by PCIe agreement, is transferred out PCIe data-signal in order to post-processed by PCIE data communication protocol by PCIE interface.
Embodiment 2:
The present embodiment is at the enterprising one-step optimization in the basis of embodiment 1, shown in composition graphs 1, Fig. 2, comprise FPGA, optical coupling isolation circuit, PCIE interface and power supply, the data-signal of motion board to be tested adopts the mode of optically-coupled Isolation input to input in FPGA by described optical coupling isolation circuit, described PCIE interface connects FPGA, described power supply connects FPGA, and also comprise the pilot lamp be connected on FPGA, pilot lamp preferably adopts LED.
Maneuvering board to be tested is stuck in and carries out in the course of work, form real output signal (the axle pulse data representated by axle Puled input, the direction of principal axis data of direction of principal axis input), real output signal carries out coupling by photoelectric isolating circuit and is input in FPGA, sampling and data storage is carried out in FPGA, by PCIE data communication protocol, PCIe data-signal is transferred out in order to post-processed by PCIE interface, LED is used for state instruction, two red and green color lamps are at least set, be used to indicate some common communication states, one is power light, it is green light during normal voltage, overvoltage or under-voltage time be red light, one is PCIe relay indicating light, it is green light during PCIe proper communication, having abnormal is red light.
Embodiment 3:
The present embodiment is at the enterprising one-step optimization in the basis of above-described embodiment, shown in composition graphs 1, Fig. 2, comprise FPGA, optical coupling isolation circuit, PCIE interface and power supply, the data-signal of motion board to be tested adopts the mode of optically-coupled Isolation input to input in FPGA by described optical coupling isolation circuit, described PCIE interface connects FPGA, the master chip that described power supply connects FPGA, described FPGA adopts XC6SLX45T.
Maneuvering board to be tested is stuck in and carries out in the course of work, form real output signal (the axle pulse data representated by axle Puled input, the direction of principal axis data of direction of principal axis input), real output signal carries out coupling by photoelectric isolating circuit and is input in FPGA, filtering is completed in FPGA, data acquisition, data store, interrupt notification PC is produced when RAM is full, PC reads the data in RAM by PCIe agreement, by PCIE data communication protocol, PCIe data-signal is transferred out in order to post-processed by PCIE interface, the master chip of described FPGA adopts the XC6SLX45T of xilinx company, it has more than 40,000 logical block, comprise 270,000 6 input look-up tables, 540000 triggers.
Embodiment 4:
The present embodiment is at the enterprising one-step optimization in the basis of above-mentioned any embodiment, input filter circuit, pulse acquisition circuit, data-carrier store, data interaction circuit, RAM is provided with in described FPGA, described optical coupling isolation circuit connects input filter circuit, described input filter circuit connects pulse acquisition circuit, described pulse acquisition circuit is connection data storer and data interaction circuit respectively, described RAM is connection data storer and data interaction circuit respectively, and described data interaction circuit connects PCIE interface.
In use, the real output signal that FPGA gathers is the high level time value of pulse and whole recurrence interval value, for 32bit data, the operations such as filtering, data acquisition, data storage are carried out in FPGA inside, after an end-of-pulsing, these two data are stored in internal RAM, RAM is filled with rear notice main frame and is read by PCIe, and this data transformations is that velocity amplitude is analyzed by main frame.
Embodiment 5:
The track detecting system of Based PC Ie, the track comprising Based PC Ie detects motion control card, main frame, motion board and the raw data source of comparing, described main frame is by the mutual circuit of PCIE interfacing data, described motion board connects main frame respectively, described maneuvering board cartoon crosses optical coupling isolation circuit by output Puled input to be tested in FPGA, be loaded with data acquisition system (DAS), data conversion system, data simulation system and data analysis system in described main frame, raw data is loaded in main frame by described raw data source.
Real output signal (the axle pulse data representated by axle Puled input that maneuvering board card is sent in the course of the work, the direction of principal axis data of direction of principal axis input), the signal gathered is based on pulsewidth and cycle data, after FPGA-PCIE board (track of Based PC Ie detects the motion control card compared) acquisition process, PCIE data communication protocol is utilized to be transferred in main frame by PCIe data-signal by PCIE interface, in main frame, the data acquisition system (DAS) of main frame reads data to PC memory by PCIe from the RAM of FPGA; The pulse-width data read and high level data are converted into speed in frequency by data conversion system; Namely data simulation system goes out actual motion curve by image data Plotting data and draws out complete curve movement by original complete data; Two curves carry out contrasting and marking according to certain error criterion by data analysis system; Raw data is mainly the data etc. of processed file resolution data, speed prediction process data, DSP write FPGA, load in main frame by raw data source, described Various types of data completes described point by software systems in main frame, draw its trace graphics, and the real output signal class data gathered also will complete described point, draw its trace graphics, both can analyze each group of data deviation after contrasting, " saltus step " phenomenon whether is there is, the leak on reminding user correction algorithm or other problems to check out easily; User can be again downloaded in motion board after adjusting for certain speed flex point of certain section of speed and again move, and again analyzes, until approach with setting value; Wherein main frame can select the host computer that equipment uses, and also can be that other PCs compared are detected for track in outside, PC can comprise PC, laptop computer.
Embodiment 6:
The track of Based PC Ie detects the method compared, and comprises the following steps:
Steps A, FPGA directly gather real output signal in motion board motion process, are stored in and open up in the FIFO of FPGA inside;
The real output signal that steps A is gathered by the PCIE bus on PCIE interface by step B, FPGA is uploaded to host memory;
Step C, in data conversion system in main frame, the data be stored in host memory are converted to the Velocity-time value table of collecting sample, and the raw data actual computation of originating provided by raw data the Velocity-time value table of complete operation, the Velocity-time value table of collecting sample utilizes with the Velocity-time value table of complete operation the data acquisition system (DAS) be carried in main frame in main frame, data conversion system, data simulation system, trajectory analysis track in data analysis system carries out contrast and determines error (i.e. sample speed and complete travelling speed are formed the speed difference of rate curve corresponding point),
Step D, determine error after readjust the speed of motion board, and repeat steps A, step B, step C, carry out sampling contrast and revise, by repeatedly revising computing and checking, the process of Approach by inchmeal, finally reach sampled notebook data identical with raw data, do one's utmost to reduce error, ensure that the perfection of motion board runs.
Sample frequency and sampling precision:
As shown in Figure 5, the highest frequency detecting the motion control card compared when the track of Based PC Ie is 2MHz, sampled signal is target according to controller pulsed frequency limit 2MHz, under this frequency, error orientates 10% as temporarily, go to adopt 2M frequency F2 with 40M frequency F1, A point rising edge is adopted as low level, but horse back is actual afterwards becomes high level, but this high level only has to C point just by real record, the cycle length of the high level 40M fewer than actual value sampled can be made to this, same at B point not counting high level, high level count value can be made than an actual value few 40M cycle again, error under extreme case is this two clock period, i.e. 2 * 1/40M=0.05us.
After sampling, data store and sample with gradation:
Data after sampling TL represents the sampling period count value that high level or low level continue;
If sample frequency is 40MHz, then under 2MHz pulsed frequency, go the pulse of sampling 2M with the frequency of 40M, each 40M rising edge clock place, judge 2M be high level then count value add 1, like this, when the dutycycle of 2M pulse is 50%, namely high level is 250ns, low level 250ns, and the 40M cycle is 25ns, altogether needs counting 250/25=10 time like this in the high level time of 1 2M, 10 TL values for this reason, computing formula is TL=sample frequency/(being sampled frequency * 2);
If pulsed frequency is reduced to 100K, then TL=40M/200K=200;
If pulsed frequency is reduced to 1Hz, then TL=40M/2=20,000,000;
Namely this time value is preserved with 32 bit data storeies;
Store data when having gathered 2M pulsewidth postscript number simultaneously, these data are two 32bit, one is high level lasting time value, a total periodic quantity in position, therefore data volume is 2*4/ (1/ treats measured frequency)=8* treats measured frequency (MB/s)=2*4Byte/ (1/2M)=16MB/s;
If actual processing average pulse frequency is 200K, then average data rate is 200*2*4=1.6MB/s; The data volume of 1 minute is: 1.6MB/s*60s=96MB; Message transmission rate is 8 * 200K=1.6MB/s;
In actual applications, the data volume of 1 minute can meet the needs that we analyze track and speed, and for the processed file more than 1 minute, sampling analysis is carried out in our segmentation;
Even processed file is 2 minutes, the first time store sample service data of the 1st minute; The second time sampling service data of second minute; The sampling time of FPGA and the DSP of motion start time and motion board arrange synchronously;
FPGA opens up the data volume of 10KB, and according to the mean value of 1.6MB/s, the data of the storage 6.25ms that coexists, under current control card hardware condition, the cycle of software twi-read is lower than 1ms.If the counting-rate meter pressing peak value 2MHz calculates data volume, 16MB/s, the data of the storage 0.625ms that coexists, software read cycle is lower than 500us; Software by read data conversion storage in internal memory, by 1 minute data amount 96MB, current main frame be its open up reserved in save as 128M, the data volume of lower 1 minute can be stored; Pulsed frequency reaches 400K, can preserve the data of at least 30s.
Embodiment 7:
The present embodiment is at the enterprising one-step optimization in the basis of above-described embodiment, comprises the following steps:
1), FPGA directly to gather in motion board motion process the actual pulsewidth and the cycle parameter that export pulse, is stored in and opens up in the FIFO of FPGA inside;
2), the pulsewidth gathered in motion process and cycle data are uploaded to host memory by the PCIE bus on PCIE interface by FPGA;
3) in the data conversion system, in main frame, the data be stored in host memory are converted to the Velocity-time value table of collecting sample, and the raw data actual computation of originating provided by raw data the Velocity-time value table of complete operation, the Velocity-time value table of collecting sample utilizes the trajectory analysis track in the data acquisition system (DAS) be carried in main frame, data conversion system, data simulation system, data analysis system to carry out contrast with the Velocity-time value table of complete operation to determine error in main frame;
4) speed of motion board is readjusted after, determining error, and repeat step 1), step 2), step 3), carry out sampling contrast and revise, by repeatedly revising computing and checking, the process of Approach by inchmeal, the identical actual speed of time value place motion and velocity error (+/-10% in a critical field of complete rate curve corresponding point, can adjust as required), finally reach sampled notebook data identical with raw data, do one's utmost to reduce error, ensure that the perfection of motion board runs.
Embodiment 8:
The present embodiment is at the enterprising one-step optimization in the basis of above-described embodiment, and the realization of described step 3) specifically divides the following two kinds mode:
3.1), to the Velocity-time value table of collecting sample and Velocity-time value table two group data described point on time shaft identical point of complete operation, draw out two curve movements, reach intuitive judgment and occur error part;
3.2), by the velocity amplitude of raw data and the velocity amplitude size of collecting sample in contrast synchronization motor point, " error " part is there is when indicating after the poor setting range that outpaces (velocity contrast on the speed time point corresponding to complete rate curve of matching after gathering), concrete grammar is as follows: the error threshold values arranging test data and reference data, on a timeline, when certain point tolerance exceedes this threshold values, mark position and the velocity information in this motor point (movement velocity on corresponding time point).
If Fig. 3 track comparison diagram that is arc-shaped, Fig. 4 are linearity shown in track comparison diagram, difference between contrast track (raw data track) and racing track (sampled data track), namely the error threshold values Δ S between sampled data and raw data, when Δ S is greater than setting value, (setting value is 10% of complete value, can adjust as required) namely indicate, represent that exercise data error is excessive, with to be adjusted herein.
Embodiment 9:
The present embodiment is at the enterprising one-step optimization in the basis of embodiment 6, and the realization of described step C specifically divides the following two kinds mode:
C.1), to the Velocity-time value table of collecting sample and Velocity-time value table two group data described point on time shaft identical point of complete operation, draw out two curve movements, reach intuitive judgment and occur error part;
C.2), by the velocity amplitude of raw data and the velocity amplitude size of collecting sample in contrast synchronization motor point, " error " part is there is when indicating after the poor setting range that outpaces (velocity contrast on the speed time point corresponding to complete rate curve of matching after gathering), concrete grammar is as follows: the error threshold values arranging test data and reference data, on a timeline, when certain point tolerance exceedes this threshold values, mark position and the velocity information in this motor point (movement velocity on corresponding time point).
If the track comparison diagram of Fig. 3, arc-shaped, Fig. 4 are linearity shown in track comparison diagram, difference between contrast track (raw data track) and racing track (sampled data track), namely the error threshold values Δ S between sampled data and raw data, when Δ S is greater than setting value, (setting value is 10% of complete value, can adjust as required) namely indicate, represent that exercise data error is excessive, with to be adjusted herein.
The present invention is by sampling to the actual output of motion board, sampled data is processed, obtain the actual velocity fitting curve exported, the velocity mode that this matched curve requires with user is carried out quantitative analysis, can check out whether there is " saltus step " phenomenon easily, the leak on reminding user correction algorithm or other problems.
The above is only preferred embodiment of the present invention, and not do any pro forma restriction to the present invention, every any simple modification, equivalent variations done above embodiment according to technical spirit of the present invention, all falls within protection scope of the present invention.
Claims (9)
1. the track of Based PC Ie detects the motion control card compared, it is characterized in that: comprise FPGA, optical coupling isolation circuit, PCIE interface and power supply, the data-signal of motion board to be tested adopts the mode of optically-coupled Isolation input to input in FPGA by described optical coupling isolation circuit, described PCIE interface connects FPGA, and described power supply connects FPGA.
2. the track of Based PC Ie according to claim 1 detects the motion control card compared, and it is characterized in that: also comprise pilot lamp, and described pilot lamp connects FPGA.
3. the track of Based PC Ie according to claim 1 and 2 detects the motion control card compared, it is characterized in that: in described FPGA, be provided with input filter circuit, pulse acquisition circuit, data-carrier store, data interaction circuit, RAM, described optical coupling isolation circuit connects input filter circuit, described input filter circuit connects pulse acquisition circuit, described pulse acquisition circuit is connection data storer and data interaction circuit respectively, described RAM is connection data storer and data interaction circuit respectively, and described data interaction circuit connects PCIE interface.
4. the track of Based PC Ie according to claim 1 and 2 detects the motion control card compared, and it is characterized in that: the master chip of described FPGA adopts XC6SLX45T.
5. the track detecting system of Based PC Ie, it is characterized in that: the track comprising Based PC Ie detects motion control card, main frame, motion board and the raw data source of comparing, described main frame is by the mutual circuit of PCIE interfacing data, described motion board connects main frame respectively, described maneuvering board cartoon crosses optical coupling isolation circuit by output Puled input to be tested in FPGA, be loaded with data acquisition system (DAS), data conversion system, data simulation system and data analysis system in described main frame, raw data is loaded in main frame by described raw data source.
6. the track of Based PC Ie detects the method compared, and it is characterized in that: comprise the following steps:
Steps A, FPGA directly gather real output signal in motion board motion process, are stored in and open up in the FIFO of FPGA inside;
The real output signal that steps A is gathered by the PCIE bus on PCIE interface by step B, FPGA is uploaded to host memory;
In step C, data conversion system in main frame, the data be stored in host memory are converted to the Velocity-time value table of collecting sample, and the raw data actual computation of originating provided by raw data the Velocity-time value table of complete operation, the Velocity-time value table of collecting sample determines error with carrying out contrast in the data acquisition system (DAS) of Velocity-time value table in main frame of complete operation, data conversion system, data simulation system, data analysis system;
Step D, determine error after readjust the speed of motion board, and repeat steps A, step B, step C, carry out sampling contrast and revise, by repeatedly revising computing and checking, the process of Approach by inchmeal, finally reach sampled notebook data identical with raw data, do one's utmost to reduce error, ensure that the perfection of motion board runs.
7. the track of Based PC Ie according to claim 6 detects the method compared, and it is characterized in that: comprise the following steps:
1), FPGA directly to gather in motion board motion process the actual pulsewidth and the cycle parameter that export pulse, is stored in and opens up in the FIFO of FPGA inside;
2), the pulsewidth gathered in motion process and cycle data are uploaded to host memory by the PCIE bus on PCIE interface by FPGA;
3) in the data conversion system, in main frame, the data be stored in host memory are converted to the Velocity-time value table of collecting sample, and the raw data actual computation of originating provided by raw data the Velocity-time value table of complete operation, the Velocity-time value table of collecting sample determines error with carrying out contrast in the data acquisition system (DAS) of Velocity-time value table in main frame of complete operation, data conversion system, data simulation system, data analysis system;
4) speed of motion board is readjusted after, determining error, and repeat step 1), step 2), step 3), carry out sampling contrast and revise, by repeatedly revising computing and checking, the process of Approach by inchmeal, finally reach sampled notebook data identical with raw data, do one's utmost to reduce error, ensure that the perfection of motion board runs.
8. the track of Based PC Ie according to claim 7 detects the method compared, and it is characterized in that: the realization specifically point the following two kinds mode of described step 3):
3.1), to the Velocity-time value table of collecting sample and Velocity-time value table two group data described point on time shaft identical point of complete operation, two curve movements are drawn out;
3.2), by the velocity amplitude of raw data and the velocity amplitude size of collecting sample in contrast synchronization motor point, appearance " error " part is indicated after exceeding setting range, concrete grammar is as follows: the error threshold values arranging test data and reference data, on a timeline, when certain point tolerance exceedes this threshold values, mark position and the velocity information in this motor point.
9. the track of Based PC Ie according to claim 6 detects the method compared, and it is characterized in that: the realization specifically point the following two kinds mode of described step C:
C.1), to the Velocity-time value table of collecting sample and Velocity-time value table two group data described point on time shaft identical point of complete operation, two curve movements are drawn out;
C.2), by the velocity amplitude in the raw data in contrast synchronization motor point and the velocity amplitude size of collecting sample, appearance " error " part is indicated after exceeding setting range, concrete grammar is as follows: the error threshold values arranging test data and reference data, on a timeline, when certain point tolerance exceedes this threshold values, mark position and the velocity information in this motor point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410502309.0A CN104298174B (en) | 2014-09-26 | 2014-09-26 | Method for detecting and comparing tracks on basis of PCIe |
Applications Claiming Priority (1)
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