CN104272432A - 放热基板及其制造方法 - Google Patents

放热基板及其制造方法 Download PDF

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CN104272432A
CN104272432A CN201380024083.1A CN201380024083A CN104272432A CN 104272432 A CN104272432 A CN 104272432A CN 201380024083 A CN201380024083 A CN 201380024083A CN 104272432 A CN104272432 A CN 104272432A
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heat release
silicon
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CN104272432B (zh
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秋山昌次
久保田芳宏
川合信
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Shin Etsu Chemical Co Ltd
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Abstract

本发明涉及放热基板，其特征在于，是由2层组成的复合基板，表层(第一层)1由单晶硅构成，处理基板(第二层)2由热导率比第一层高的材料构成，本发明涉及的放热基板给予高的放热性。

Description

放热基板及其制造方法
技术领域
本发明涉及包含具有高放热性的硅复合基板的放热基板及其制造方法。
背景技术
近年来，硅半导体器件伴随设计规则的微细化，其性能日益提高。但是，其相反面是，来自各个晶体管、连接晶体管间的金属配线的放热成为了问题。为了应对该问题，也出现了在器件的制作后将硅的里面变薄(百-几百μm左右)，将巨大的风扇安装到芯片上，促进放热，或者缠绕水冷管。
但是，实际上，即使将硅变薄，制作器件的区域(器件活性层)从表面最多为几μm，这以外的区域作为“热滞留区”发挥作用，因此从放热的观点出发，不能不说效率差。此外，近年来，高性能处理器等中使用的SOI晶片等具有在器件活性层的正下方经由绝缘层的结构，该绝缘层(SiO2)也是热传导性极差的物质，因此从放热的观点出发，是难以处理的材料。
从放热的观点出发，可以说希望在器件活性层的正下方配置放热性优异的材料。
发明内容
发明要解决的课题
本发明鉴于上述实际情况而完成，目的在于提供给予高的放热性的放热基板及其制造方法。
用于解决课题的手段
本发明人为了实现上述目的进行了深入研究，结果发现，以下的2层或3层结构的基板具有高的放热性，完成了本发明。
即，本发明提供下述放热基板及其制造方法。
[1]放热基板，其特征在于，是由2层组成的复合基板，表层(第一层)由单晶硅构成，处理(handle)基板(第二层)由热导率比第一层高的材料构成。
[2][1]所述的放热基板，其特征在于，第二层的材料由氮化铝、碳化硅、金刚石的任一种构成。
[3]放热基板，其特征在于，是由3层组成的复合基板，表层(第一层)由单晶硅构成，处理基板(第二层)由热导率比第一层高的材料构成，并且中间层(第三层)由与第二层的热导率同等的材料或热导率比其高的材料构成。
[4][3]所述的放热基板，其特征在于，第二层、第三层的材料从氮化铝、碳化硅、金刚石中选择。
[5][1]所述的放热基板，其特征在于，将第一层(硅层)和第二层贴合，将第一层(硅层)变薄而成。
[6][3]所述的放热基板，其特征在于，将第一层(硅层)、中间层(第三层)和第二层贴合，将第一层(硅层)变薄而成。
[7]放热基板的制造方法，其中，将由单晶硅构成的硅层和由热导率比硅层高的材料构成的处理基板贴合后，将硅层变薄，制成由成为表层的第一层(硅层)和第二层(处理基板)的2层的复合材料构成的放热基板。
[8]放热基板的制造方法，其中，将由单晶硅构成的硅层、由热导率比硅层高的材料构成的处理基板和由与处理基板的热导率同等的材料或热导率比其高的材料构成的中间层贴合以成为硅层、中间层、处理基板的层叠结构后，将硅层变薄，制成由成为表层的第一层(硅层)、第三层(中间层)和第二层(处理基板)的3层的复合材料构成的放热基板。
[9][7]或[8]所述的放热基板的制造方法，其特征在于，通过研削、研磨将硅层变薄。
[10][7]或[8]所述的放热基板的制造方法，其特征在于，采用离子注入剥离法将硅层变薄。
[11][7]～[10]的任一项所述的放热基板的制造方法，其特征在于，作为上述贴合前处理，实施等离子体活性化、离子束处理或臭氧处理。发明的效果
本发明涉及的放热基板给予高的放热性。
附图说明
图1是表示本发明的复合基板的一实施例的断面图。
图2是表示本发明的复合基板的另一实施例的断面图。
图3表示2层结构的复合基板的制作方法的一例，(a)是准备各层的状态、(b)是贴合的状态、(c)是将第一层变薄的状态的断面图。
图4表示2层结构的复合基板的另一制作方法，(a)是准备各层的状态、(b)是贴合的状态、(c)是将第一层变薄的状态的断面图。
图5表示3层结构的复合基板的制作方法的一例，(a)是准备各层的状态、(b)是贴合的状态、(c)是将第一层变薄的状态的断面图。
图6表示3层结构的复合基板的另一制作方法，(a)是准备各层的状态、(b)是贴合的状态、(c)是将第一层变薄的状态的断面图。
图7是表示本发明的实施例的热导率的坐标图。
图8是表示本发明的比较例的热导率的坐标图。
具体实施方式
本发明的放热基板以单晶硅作为表层(第一层)，具有2层结构(图1)或3层结构(图2)。
其中，结构由2层构成的情况下，在硅(第一层)1的下层(第二层)2配置热导率比硅高的层。
结构由3层构成的情况下，硅(第一层)1之下的第三层3的热导率比第一层1高，而且该第三层3的热导率比第二层2高，或者具有大致相同的值。此外，第二层2的热传导度比第一层1高。第二层的热传导最高的理由在于，由于设想第一层中产生的热在晶体管附近产生，因此通过将该热均等地在芯片面内传导，模拟地促进放热作用。
两种情况下，有几个第二层、第三层的候补材料，但由于用于半导体用途，因此难以采用金属材料。作为适合半导体用途的材料，可列举金刚石、氮化铝、碳化硅。硅、金刚石、氮化铝、碳化硅、SiO2的热导率分别如下所述，是测定法采用后述的激光闪光法得到的值。
Si：1.5W/cm·K
金刚石：10～20W/cm·K
氮化铝：1.5～2.0W/cm·K
碳化硅：2.0～3.8W/cm·K
SiO2：0.015W/cm·K
其中，SiO2的热导率极端地差，可知作为放热基板用途不适合。
有几种制作上述的层叠结构的方法。结构为2层结构的情况下，有通过将成为给体基板(硅晶片)的基板与处理基板贴合而制作的方法。结构为3层基板的情况下，是在给体或处理(基板)、或者两者上将成为第三层的材料成膜，将两基板贴合的方法等。
这种情况下，对于硅基板能够使用变薄直至所需的厚度的产物。作为将成为第一层的硅层变薄直至所需的厚度的方法，可列举将硅晶片采用研削-研磨而变薄的方法；在贴合前在硅晶片中实施离子注入，贴合后进行剥离的方法(离子注入剥离法，例如SiGen法等离子注入机械剥离法)。
其中，图3表示2层结构的制作方法的一例，(a)准备第一层(Si)1和第二层2，(b)将它们贴合，(c)接下来通过研削、研磨，将第一层1变薄直至所需的厚度。
图4表示2层结构的另一制作方法，首先，(a)从第一层(Si)1的一面形成离子注入区域1离子，(b)将该第一层1的离子注入区域1离子侧与第二层2贴合，接下来，(c)在第一层1的离子注入区域1离子剥离，得到变薄的第一层(硅层)1a与第二层2层叠的复合基板。离子注入区域1离子的形成方法并无特别限定，例如，用能够从第一层1的表面到所需的深度形成离子注入区域1离子的注入能量，注入规定的线量的氢离子或稀有气体离子。从离子注入的第一层1表面到离子注入区域1离子的深度(即，离子打入深度)对应于变薄的第一层的所需的厚度。此外，离子注入区域1离子的厚度(即，离子分布厚度)，优选通过机械冲击等能够容易地剥离的厚度。
图5表示3层结构的制作方法的一例，首先，(a)准备第一层(Si)1、第二层2、第三层3，(b)将它们贴合，接下来，(c)通过研削、研磨将第一层(Si)1变薄直至所需的厚度。
这种情况下，(i)可在第二层2上将第三层3成膜，将其与第一层1贴合，(ii)也可在第一层1将第三层3成膜的产物与第二层2贴合，(iii)还可将第一层1、第二层2上分别将第三层3成膜的产物贴合。
图6表示3层结构的另一制作方法，首先，(a)从第一层(Si)1的贴合面侧形成离子注入区域1离子，(b)将第一层1的离子注入区域1离子侧与第三层3、第二层2贴合，接下来，(c)在第一层1的离子注入区域1离子进行剥离。这种情况下，(i)可将在第二层2上将第三层3成膜的产物与第一层1的离子注入区域1离子侧贴合，(ii)也可将在第一层1的离子注入区域1离子侧的面将第三层3成膜的产物与第二层2贴合，(iii)还可在第一层1的离子注入区域1离子侧的面和第二层2上分别将第三层3成膜，将它们贴合。这种情形的离子注入区域1离子的形成方法、离子打入深度、离子分布厚度与图4的情形相同。
其中，第一层的单晶硅的厚度优选为1～20μm，特别优选为1～10μm。此外，第二层的厚度优选为1～800μm，特别优选为100～750μm，第三层的厚度优选为1～30μm。
再有，本发明并不特别限定于上述制作方法。此外，贴合前为了增加结合强度，也可实施已知的表面活性化(臭氧水处理、UV臭氧处理、离子束处理、等离子体处理等)的任一种。
实施例
以下示出实施例和比较例，对本发明具体地说明，但本发明并不受下述实施例限制。
[实施例]
作为实施例，测定了下述的复合材料的热导率。测定方法为激光闪光法(根据JIS R 1611-1997)。其是通过对表面的单晶硅均匀照射脉冲激光而瞬间加热，观察里面的温度变化而得到的。复合基板的情况下，热导率是与基板全体由均一的材料制成近似的情形的值。
你·Si/SiC(Si层为厚1.0μm，SiC基板为厚625μm)
·Si/SiC/AlN(Si层为厚1μm，SiC层为厚1.0μm，AlN基板为厚625μm)
·Si/金刚石/SiC(Si层为厚1μm，金刚石层为厚1.0μm，SiC基板为厚625μm)
·Si/金刚石/AlN(Si层为厚1μm，金刚石层为厚1.0μm，AlN基板为厚625μm)
再有，上述复合材料的制作方法如下所述。
·对于Si/SiC，采用上述的图3的方法制作。
·对于Si/SiC/AlN，采用上述的图4的方法制作。
·对于Si/金刚石/SiC和Si/金刚石/AlN，分别采用上述的图6(i)的方法制作。
再有，上述的任何情况下，都在贴合前对两基板的表面实施了提高接合强度的等离子体活性化处理。
将结果示于图7。值如下所述。
·Si/SiC：1.85W/cm·K
·Si/SiC/AlN：1.75W/cm·K
·Si/金刚石/SiC：2.2W/cm·K
·Si/金刚石/AlN：1.78W/cm·K
在全部的情况下，能够确认具有比硅单体高的放热性。
[比较例]
作为比较例，测定了下述的材料的热导率。测定方法是与上述相同的激光闪光法。其是通过对表面均匀照射脉冲激光而瞬间加热，观察里面的温度变化而得到的。复合基板(SOI)的情况下，是与基板全体由均一的材料制成近似的情形的值。
·硅(厚625μm)
·SOI晶片(SOI层1μm、Box层0.5μm、处理晶片625μm)
该SOI晶片是通过将作为在表面形成了硅氧化膜的单晶硅晶片的处理晶片与作为形成了离子注入区域的硅基板的给体晶片经由硅氧化膜贴合后，在离子注入区域将给体晶片机械剥离，将硅薄膜转印于处理晶片侧而得到的。
·氮化铝(采用CVD法制作：厚625μm)
·碳化硅(采用CVD法制作：厚625μm)
将结果示于图8。值如下所述。
·硅(Si)：1.5W/cm·K
·SOI晶片：0.6W/cm·K
·氮化铝(AlN)：1.8W/cm·K
·碳化硅(SiC)：2.3W/cm·K
关于金刚石，由于块体基板的获得困难，以下记载推定值。
·金刚石：11W/cm·K
附图标记说明
1  第一层(Si)
1a  变薄的第一层(硅层)
1离子  离子注入区域
2  第二层
3  第三层

Claims (11)

1.放热基板，其特征在于，是由2层组成的复合基板，表层(第一层)由单晶硅构成，处理基板(第二层)由热导率比第一层高的材料构成。
2.权利要求1所述的放热基板，其特征在于，第二层的材料由氮化铝、碳化硅、金刚石的任一种构成。
3.放热基板，其特征在于，是由3层组成的复合基板，表层(第一层)由单晶硅构成，处理基板(第二层)由热导率比第一层高的材料构成，并且中间层(第三层)由与第二层的热导率同等的材料或热导率比其高的材料构成。
4.权利要求3所述的放热基板，其特征在于，第二层、第三层的材料从氮化铝、碳化硅、金刚石中选择。
5.权利要求1所述的放热基板，其特征在于，将第一层(硅层)和第二层贴合，将第一层(硅层)变薄而成。
6.权利要求3所述的放热基板，其特征在于，将第一层(硅层)、中间层(第三层)和第二层贴合，将第一层(硅层)变薄而成。
7.放热基板的制造方法，其特征在于，将由单晶硅构成的硅层和由热导率比硅层高的材料构成的处理基板贴合后，将硅层变薄，制成由成为表层的第一层(硅层)和第二层(处理基板)的2层的复合材料构成的放热基板。
8.放热基板的制造方法，其中，将由单晶硅构成的硅层、由热导率比硅层高的材料构成的处理基板和由与处理基板的热导率同等的材料或热导率比其高的材料构成的中间层贴合以成为硅层、中间层、处理基板的层叠结构后，将硅层变薄，制成由成为表层的第一层(硅层)、第三层(中间层)和第二层(处理基板)的3层的复合材料构成的放热基板。
9.权利要求7或8所述的放热基板的制造方法，其特征在于，通过研削、研磨将硅层变薄。
10.权利要求7或8所述的放热基板的制造方法，其特征在于，采用离子注入剥离法将硅层变薄。
11.权利要求7～10的任一项所述的放热基板的制造方法，其特征在于，作为上述贴合前处理，实施等离子体活性化、离子束处理或臭氧处理。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990215A (zh) * 2015-03-02 2016-10-05 北大方正集团有限公司 Soi基片的制作方法和soi基片

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6208572B2 (ja) * 2013-12-19 2017-10-04 イビデン株式会社 ＳｉＣウェハの製造方法、ＳｉＣ半導体の製造方法及び黒鉛炭化珪素複合基板
KR102471159B1 (ko) 2015-10-12 2022-11-25 삼성전자주식회사 이미지 센서 및 그 제조 방법
JP6281848B2 (ja) * 2016-01-21 2018-02-21 たまき 野間 放熱塗料
US10062636B2 (en) * 2016-06-27 2018-08-28 Newport Fab, Llc Integration of thermally conductive but electrically isolating layers with semiconductor devices
JP6854895B2 (ja) * 2017-07-14 2021-04-07 信越化学工業株式会社 高熱伝導性のデバイス基板およびその製造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5373171A (en) * 1987-03-12 1994-12-13 Sumitomo Electric Industries, Ltd. Thin film single crystal substrate
JPH11255599A (ja) * 1998-03-11 1999-09-21 Kobe Steel Ltd 単結晶ダイヤモンド合成用基板
US20060113546A1 (en) * 2002-10-11 2006-06-01 Chien-Min Sung Diamond composite heat spreaders having low thermal mismatch stress and associated methods
JP2009076694A (ja) * 2007-09-20 2009-04-09 Panasonic Corp 窒化物半導体装置およびその製造方法
JP2009231506A (ja) * 2008-03-21 2009-10-08 Shin Etsu Chem Co Ltd 貼り合わせ基板の製造方法
EP2211380A2 (en) * 2009-01-15 2010-07-28 Shin-Etsu Chemical Co., Ltd. Method of Manufacturing Laminated Wafer by High Temperature Laminating Method
US20100219418A1 (en) * 2007-05-31 2010-09-02 Chien-Min Sung Diamond led devices and associated methods
JP2010189234A (ja) * 2009-02-19 2010-09-02 Shin-Etsu Chemical Co Ltd 低応力・拡散バリアー膜を備えた熱伝導部材
EP2246878A1 (en) * 2009-04-30 2010-11-03 Shin-Etsu Chemical Co., Ltd. Method for preparing soi substrate having backside sandblasted

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766971B2 (ja) * 1989-06-07 1995-07-19 シャープ株式会社 炭化珪素半導体装置
US7132309B2 (en) * 2003-04-22 2006-11-07 Chien-Min Sung Semiconductor-on-diamond devices and methods of forming
US6793759B2 (en) * 2001-10-09 2004-09-21 Dow Corning Corporation Method for creating adhesion during fabrication of electronic devices
JP4219838B2 (ja) * 2004-03-24 2009-02-04 シャープ株式会社 半導体基板の製造方法、並びに半導体装置の製造方法
US7605055B2 (en) * 2005-06-02 2009-10-20 S.O.I.Tec Silicon On Insulator Technologies Wafer with diamond layer
US7984408B2 (en) * 2006-04-21 2011-07-19 International Business Machines Corporation Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering
US7799599B1 (en) * 2007-05-31 2010-09-21 Chien-Min Sung Single crystal silicon carbide layers on diamond and associated methods
US7846767B1 (en) * 2007-09-06 2010-12-07 Chien-Min Sung Semiconductor-on-diamond devices and associated methods
JP5248838B2 (ja) * 2007-10-25 2013-07-31 信越化学工業株式会社 半導体基板の製造方法
US8785261B2 (en) * 2010-09-23 2014-07-22 Intel Corporation Microelectronic transistor having an epitaxial graphene channel layer
US8410508B1 (en) * 2011-09-12 2013-04-02 SemiLEDs Optoelectronics Co., Ltd. Light emitting diode (LED) package having wavelength conversion member and wafer level fabrication method

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5373171A (en) * 1987-03-12 1994-12-13 Sumitomo Electric Industries, Ltd. Thin film single crystal substrate
JPH11255599A (ja) * 1998-03-11 1999-09-21 Kobe Steel Ltd 単結晶ダイヤモンド合成用基板
US20060113546A1 (en) * 2002-10-11 2006-06-01 Chien-Min Sung Diamond composite heat spreaders having low thermal mismatch stress and associated methods
US20100219418A1 (en) * 2007-05-31 2010-09-02 Chien-Min Sung Diamond led devices and associated methods
JP2009076694A (ja) * 2007-09-20 2009-04-09 Panasonic Corp 窒化物半導体装置およびその製造方法
JP2009231506A (ja) * 2008-03-21 2009-10-08 Shin Etsu Chem Co Ltd 貼り合わせ基板の製造方法
EP2211380A2 (en) * 2009-01-15 2010-07-28 Shin-Etsu Chemical Co., Ltd. Method of Manufacturing Laminated Wafer by High Temperature Laminating Method
JP2010189234A (ja) * 2009-02-19 2010-09-02 Shin-Etsu Chemical Co Ltd 低応力・拡散バリアー膜を備えた熱伝導部材
EP2246878A1 (en) * 2009-04-30 2010-11-03 Shin-Etsu Chemical Co., Ltd. Method for preparing soi substrate having backside sandblasted

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990215A (zh) * 2015-03-02 2016-10-05 北大方正集团有限公司 Soi基片的制作方法和soi基片
CN105990215B (zh) * 2015-03-02 2019-04-26 北大方正集团有限公司 Soi基片的制作方法和soi基片

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