CN104270152B - The insensitive common mode charge control devices of PVT for charge coupling assembly line analog to digital converter - Google Patents
The insensitive common mode charge control devices of PVT for charge coupling assembly line analog to digital converter Download PDFInfo
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Abstract
The present invention relates to a kind of circuit arrangement that can be used for control charge coupling assembly line analog to digital converter internal common mode electric charge.Including two output common mode tunable charge transmission circuits（BBD）, a common mode detection adjustment circuit, a shut-off voltage duplicate circuit.It is an object of the present invention to suppress to common mode charge problem caused by existing electric charge transmission technology, the purpose of accurate adjustment common mode charge is reached by 2 kinds of adjustment modes.The first adjustment mode changes the large signal characteristic of common source and common grid amplifier by adjusting the underlayer voltage of common source and common grid amplifier input pipe, so as to change whole BBD pass break-point voltage.The second way changes the large signal characteristic of common source and common grid amplifier by changing parallel transistor M4 grid voltage, so as to change whole BBD pass break-point voltage.Both modes are respectively intended to tackle foregoing two kinds of common mode charge errors.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to one kind can be used for control charge coupling assembly line modulus to turn
The circuit arrangement of parallel operation internal common mode electric charge.
Technical background
In charge coupling assembly line analog to digital converter, the charge packet that charge coupled sampling-holding circuit samples to obtain will
It is sent in the sub- level production line circuit of subsequent stages Charged Couple and is compared quantification treatment step by step.For real using fully differential structure
For existing charge coupling assembly line analog to digital converter, signal transacting is in two signal condition complementary pairs centered on common-mode signal
Synchronously carried out on the positive and negative signal transacting path claimed, final process is finally used as using the difference of two signalling channel results
As a result.Input voltage signal is converted to two charge packets of fully differential form first, respectively for subsequent stages fully differential electric charge coupling
Zygote level production line circuit quantification treatment, finally obtains quantization output result.
In above-mentioned charge coupling assembly line analog to digital converter, the sub- level production line circuit of subsequent stages Charged Couple is to input electricity
Its common mode charge bag size typically keeps equal constant when pocket is handled.Under the conditions of existing CMOS technology, due to work
Skill fluctuates the presence of randomness and other kinds irrational factors, the sub- level production line circuit of Charged Couples at different levels realized
Common mode charge size can not be strictly equal, but certain common-mode error be present.
In the factors for influenceing common mode charge, the influence of the charge transfer circuit module between sub- level circuit is to closing weight
Will.Realization for high efficiency charge transfer technology, existing technical implementation way typically have patent：US2007/0279507A1
Enhanced charge transfer circuit, its exemplary circuit configuration are as shown in Figure 1.Electric charge transmission MOSFET S grid VGBe connected to by
The output end for the operational amplifier 1 that metal-oxide-semiconductor M1, M2 and M3 are formed.Before the output end computing electric charge transmission of operational amplifier 1, S
State is off, electric charge to be transmitted is stored in C1On.Fig. 2 is the operating voltage waveform diagram of the circuit.The t0 moment,
Ck1 occurs negative rank and more changed, and Ck1n occurs positive exponent and more changed, and causes Ni voltages VNiIt is mutated to a low potential and No voltage
VNoThe change will be responded and drive MOSFET S grids V by being mutated to a high potential, operational amplifier 1GVoltage is high level,
So that S is begun to turn on；Due to the reason of electrical potential difference, electric charge is stored on Ni electronically to be shifted to No, cause VNiOn
Rise and VNoDecline, operational amplifier 1 will can equally respond the change and drive MOSFET S grids VGVoltage gradually reduces；During t1
Carve, work as VNiRise to voltage VrWhen, VGVoltage is gradually lowered to blanking voltage VthWhen, S is turned off again, charge transfer process knot
Beam, wherein VrDetermined by the quiescent point of cascade operational amplifier.
The quantity of electric charge Q that circuit shown in Fig. 1 is transmitted within a clock cycleTC can be used1Upper charge variation amount represents.
In above formula, VCk1(t0)、VCk1(t1)、VNi(t0) fixed amount directly to be controlled by reference voltage；VNi(t0) by
Signal charge quantity to be transmitted determines, and VNi(t1) approached in the electric charge end of transmission to voltage Vr.In whole charge transfer process,
VNiTo VrThe speed and precision approached directly determine the electric charge transmission speed and precision of BCT circuits.If VrIt is precise and stable, then pass
The quantity of electric charge transmitted during defeated is the linear function of signal charge to be transmitted.But due to VrBy cascade operational amplifier
Quiescent point determine, VrFluctuated for PVT (technological fluctuation, supply voltage noise, temperature change) very sensitive.Assuming that by
V is fluctuated in PVTrGenerate Δ V change, corresponding VNi(t1) Δ V voltage variety will be produced.By (1) formula, we can be with
See that Δ V can be directly in QTUpper generation Δ Q=Δs V*C1The error quantity of electric charge.
When the circuit by fully differential in use, the common mode charge amount that can be transmitted is：
As can be seen that VNi(t1) error caused by can not be eliminated when common mode charge transmits, and the error is transferred directly to
Late-class circuit, therefore must be control effectively for the error.
The content of the invention
The purpose of the present invention is the deficiencies in the prior art, there is provided a kind of external signal can Serial regulation PVT it is insensitive
Common mode charge control device, common mode charge problem caused by existing electric charge transmission technology is suppressed.
According to technical scheme provided by the invention, the PVT for charge coupling assembly line analog to digital converter is insensitive
Common mode charge control device includes：Two output common mode tunable charge transmission circuits, common mode detection adjustment circuit, a pass
Power-off pressure duplicate circuit；First output common mode tunable charge transmission circuit and the second output common mode tunable charge transmission circuit
OUT terminal output signal is input to common mode detection adjustment circuit, and common mode detects adjustment circuit according to the first output common mode adjustable electric
The OUT signal of lotus transmission circuit, the OUT signal of the second output common mode tunable charge transmission circuit, control clock and reference voltage
VREFHandled and by output feedback signal Vfb, feedback signal Vfb is connected respectively to two output common mode tunable charge transmission
The output common mode of the P ends regulation OUT terminal of circuit, shut-off voltage duplicate circuit is according to reference voltage VR,1Produce substrate control voltage
The B ends of two output common mode tunable charge transmission circuits of Vbody connections；First output common mode tunable charge transmission circuit and second
Output common mode tunable charge transmission circuit each produces output OUT signal according to the signal at IN ends, B ends and P ends, fully differential
While OUT signal is by common mode detection adjustment circuit detection, next stage common mode charge control circuit is also directly output to；
Described output common mode tunable charge transmission circuit includes：NMOS tube M4 and NMOS tube M1 drain electrode are connected simultaneously
To NMOS tube M2 source electrode, NMOS tube M4 and M1 source electrode are connected to ground simultaneously, and NMOS tube M1 and M4 grid connect respectively
IN ends and P ends, and NMOS tube M1 substrate electric potential is controlled by B ends；NMOS tube M2 drain electrode is connected to electric charge transmission NMOS tube
The drain electrode of Ms grid and PMOS M3, while NMOS tube Men drain electrode is also connected to, NMOS tube M2 grid connects bias voltage
Vbn；；PMOS M3 source electrode is connected to PMOS Mep drain electrode, and PMOS M3 grid meets bias voltage Vbp, PMOS M3
Drain electrode connect NMOS tube Men drain electrode；PMOS Mep source electrode connects supply voltage, and PMOS Mep grid connects work clock
Ck0；NMOS tube Men source ground, NMOS tube Men grid meet work clock Ck0；Electric charge transmission NMOS tube Ms sources, leakage and
Grid end connects the drain electrode at IN ends, OUT terminal and NMOS tube M2 respectively.
Output common mode electric charge of the common mode detection adjustment circuit to first, second output common mode tunable charge transmission circuit
Adjustment be by controlling the P ends of the metal-oxide-semiconductor M4 inside first, second output common mode tunable charge transmission circuit to realize respectively.
Output common mode electric charge of the shut-off voltage duplicate circuit to first, second output common mode tunable charge transmission circuit
Adjustment be underlayer voltage B by controlling the metal-oxide-semiconductor M1 inside first, second output common mode tunable charge transmission circuit respectively
Realize at end.
The common mode detection adjustment circuit includes a common-mode error amplifier module and an error signal processing module,
Common-mode error amplifier module is compared under the control of control clock to difference output charge signal and Vref signal, and will
As a result it is output to error signal processing module；Error signal processing module is handled common-mode error signal to obtain Vfb outputs
Signal, for controlling the P ends of output common mode tunable charge transmission circuit.Error signal processing inside common mode detection adjustment circuit
Module uses programmable trans-conductance amplifier circuit.
It is an advantage of the invention that：Reach the purpose of accurate adjustment common mode charge by 2 kinds of adjustment modes.The first adjustment side
Formula changes the large signal characteristic of common source and common grid amplifier by adjusting the underlayer voltage of common source and common grid amplifier input pipe, so as to
Change whole BBD pass break-point voltage.The second way is put by changing parallel transistor M4 grid voltage to change cascade
The large signal characteristic of big device, so as to change whole BBD pass break-point voltage.Both modes are respectively intended to tackle foregoing two kinds altogether
Mould charge error.
Brief description of the drawings
Fig. 1 is charge transfer circuit schematic diagram in the prior art.
Fig. 2 is electric charge transmitted waveform figure in the prior art.
Fig. 3 is the insensitive common mode charge control device structure charts of PVT of the present invention.
Fig. 4 is the circuit diagram of the output common mode tunable charge transmission circuit (abbreviation BBD) of the present invention.
Fig. 5 is the structural representation of shut-off voltage duplicate circuit.
Fig. 6 is a kind of specific implementation of low-power consumption error amplifier circuit in Fig. 5.
Fig. 7 is the concrete structure block diagram that common mode detects adjustment circuit.
Fig. 8 is a kind of specific implementation of common-mode error amplifier module in Fig. 7.
Fig. 9 is the specific implementation that error signal processing module is may be programmed in Fig. 7.
Embodiment
The present invention is described in more detail with example below in conjunction with the accompanying drawings.
Fig. 3 show the structured flowchart of the insensitive common mode charge control circuits of PVT provided by the invention, it include 2 it is defeated
Go out 33, shut-off voltage duplicate circuits 34 of common mode tunable charge transmission circuit 31 and 32, scale detection adjustment circuits, figure
In 35 be next stage flow line circuit dependent common mode charge control circuit.The annexation of circuit shown in Fig. 3 is as follows：Output
The OUT terminal output signal of common mode tunable charge transmission circuit 31 and 32 is that common mode detection adjustment circuit 33 is detected and controlled
It is compared and treated under the control of clock with Vref voltages, and output feedback signal Vfb is connected to the P controls of circuit 31 and 32
The output common mode of regulation OUT terminal in end processed；Voltage duplicate circuit 34 is turned off according to voltage Vr, 1 produces substrate control voltage Vbody controls
The B ends of circuit 31 and 32 processed；The signal that output common mode tunable charge transmission circuit 31 and 32 provides according to IN, B and P end produces defeated
Go out signal OUT, while the OUT signal of fully differential is detected by common mode detection adjustment circuit 33, be also directly output to next stage (the
N+1 levels) common mode charge control circuit.
For charge coupling assembly line ADC, except BBD close break-point voltage by PVT change and influence common mode charge with
Outside, the change of whole ADC input signal common mode electrical level can also make it that this grade and common mode charge later at different levels generation are larger
Error, so as to influence the normal work of late-class circuit.In order to tackle the two factors, BBD circuits of the invention provide two
Adjustment means are planted to control the error of sub- level circuit output common mode charge.This improved BBD circuits are as indicated at 4.The first is adjusted
Perfect square formula changes the large signal characteristic of common source and common grid amplifier by adjusting the underlayer voltage of common source and common grid amplifier input pipe,
So as to change whole BBD pass break-point voltage.The second way is total to by changing parallel transistor M4 grid voltage to change common source
The large signal characteristic of grid amplifier, so as to change whole BBD pass break-point voltage.Both modes are respectively intended to tackle foregoing two
Kind common mode charge error.
Fig. 4 is the circuit diagram of output common mode tunable charge transmission circuit of the present invention.It is in reinforced electric shown in Fig. 1
3 metal-oxide-semiconductors and 3 control signals are added on the basis of lotus transmission circuit, 3 metal-oxide-semiconductors are respectively：One parallel drive pipe M4
(NMOS), clock-reset Mep (PMOS) and Men pipes (NMOS)；3 control signals are B, P and work clock Ck0.It is electric shown in Fig. 4
The annexation on road is：Draining for NMOS tube M4 and M1 is connected to NMOS tube M2 source electrode simultaneously, and M4 and M1 source electrode are simultaneously
With being connected to, M1 and M4 grid connects IN ends and P input respectively, and M1 substrate electric potential turns to be controlled by B；M2 leakage
Pole is connected to the drain electrode of NMOS tube Ms grid and PMOS M3, while is also connected to Men drain electrode, and M2 grid connects biased electrical
Press Vbn；M3 source electrode is connected to Mep drain electrode, and the drain electrode that M3 grid meets bias voltage Vbp, M3 connects Men drain electrode；Mep's
Source electrode connects supply voltage, and grid meets work clock Ck0；Men source ground, grid meet work clock Ck0；Electric charge transmits NMOS
Pipe Ms sources, leakage and grid end connect IN, OUT and M2 drain electrode respectively.
Fig. 5 show the structure of shut-off voltage duplicate circuit 34.The function of the circuit realiration is to M1 tube linings bottom electricity in Fig. 4
The adjustment and control of B points current potential in the control of pressure, i.e. Fig. 3.Comprising missing in shut-off voltage duplicate circuit 34 its structure shown in Fig. 5
Poor amplifier 51 and grid bootstrapping BBD 52 two circuit function modules of duplicate circuit.
The size crystal corresponding to main BBD circuits in Fig. 4 of each transistor of common-source amplifier in grid bootstrapping BBD duplicate circuits 52
The size of pipe must design in strict accordance with fixed proportion.Usually reduce circuit power consumption, circuit size and main BBD electricity in circuit 52
Corresponding metal-oxide-semiconductor size uses the relational design of scaled down in road.Duplicate circuit is free of electric capacity and CCL, and
The drain terminal and source of transmitting switch add voltage source V respectivelyBWith bias current sources IB.Current source IBIt is very small, only several μ
A, thus can be when the transmission of simulation main BBD circuits electric charge closes to an end very well state, the voltage of its S point is i.e. very close main
The pass break-point voltage V of BBD transmitting switches0.Error amplifier 51 in feedback control circuit is by the voltage of S points and designed ginseng
Examine voltage VRIt is compared, draws error signal, and substrate control signal V is produced after being handledbody, adjust in duplicate circuit
M1Substrate terminal.The negative-feedback can ensure that the voltage of S points is approximately equal to V all the timeR, so as to largely suppress PVT changes pair
The influence of duplicate circuit S point voltages., can be by setting N-bit register to control from resistance string to realize more preferable flexibility
In the size of point current source walked change VR size, so as to realizing the control to switch OFF point voltage in duplicate circuit.
Fig. 6 show a kind of specific implementation of error amplifier 51 in Fig. 5, and its circuit employs the product of Switch capacitor structure
Point device structure, be using switched capacitor technique in order to realize lower power consumption, it is same using traditional continuous time integrator circuit
Sample can realize above-mentioned function.Feedback control signal Vbody is connected to corresponding grid bootstrapping BBD duplicate circuits by error amplifier 51
52 B ends, you can realize the control that voltage is turned off to main BBD.Because simultaneously feedback control signal adjusts main circuit and replicates electricity
The substrate control terminal on road, so main BBD pass break-point voltage will follow the voltage of duplicate circuit S points.Feedback loop stable S points
Voltage, the pass break-point voltage for also allowing for main BBD are approximately equal to V all the timeR。
Fig. 7 show the specific implementation structured flowchart of common mode detection adjustment circuit 33 of the present invention, and it includes one
Common-mode error amplifier module and an error signal processing module.Common-mode error amplifier module is under the control of control clock
Difference output charge signal and Vref signal are compared, and result is output to error signal processing module；Error signal
Processing module is handled common-mode error signal to obtain Vfb output signals, for controlling the P ends of BBD circuits.Shown in Fig. 7
Common mode detects adjustment circuit, inclined between the output common mode level of the sub- level production line of Charged Couple and reference signal by detecting
Difference, a control signal is produced according to the deviation, changes the grid voltage P of parallel transistor in BBD, so as to finely tune BBD shut-off electricity
Pressure carrys out common mode charge error caused by the fluctuation of offset input signal common mode electrical level.
Fig. 8 show a kind of specific implementation of common-mode error amplifier module in Fig. 7.Its structure is that basic switch electric capacity is adopted
Sample retainer, wherein single tube switch are PMOS switch, and complementary switch upper end is that NMOS tube lower end is PMOS.Its course of work can
To be divided into two-phase：Sample mutually and establish phase.In sampling phase, cp1 step-downs, when cp is high, threshold voltage Vp and Vn is total to comparator
Mould biasing Vset is connected to electric capacity sole plate and top plate is sampled；Establishing phase, electric capacity sole plate connect defeated people's signal Vip and
Vin, the difference of so defeated people's signal and threshold signal appear in two input ends of voltage comparator, then voltage comparator
Proceed by amplification.It is as follows that comparison signal establishes process：Electric charge on sampling two electric capacity of phase is C (Vset-Vip) respectively
With C (Vset-Vin)；Phase is being established, due to charge conservation, the voltage of the input end of comparator two will be Vset-Vip+Vp respectively
And Vset-Vin+Vn, contrasted equivalent to by defeated people's voltage and comparative threshold voltage, i.e.,：
(Vset-Vip+Vp)-(Vset-Vin+Vn)=(Vp-Vn)-(Vip-Vin) (3)
Fig. 9 show a kind of specific implementation of error signal processing module described in Fig. 7.To improve design flexibility, adopt
With programmable trans-conductance amplifier circuit.The specific annexation of circuit is：PMOS M3 and M4 form simple PMOS current mirrors
Circuit, PMOS M3 grid are connected to the drain terminal of M3 pipes, and NMOS tube M1 and M2 form input difference pair, and M1 drain electrode is connected to M3
Drain electrode, M2 drain electrode is connected to M4 drain electrode, and NMOS tube M1 and M2 source electrode are connected respectively to resistance R1 and R2 upper end, electricity
Resistance R1 is connected together with R2 lower end and is connected to the drain terminal of M5 pipes, and M5 source electrode is connected to M6 drain electrode, and M6 source electrode connects
Ground is connected to, NMOS tube M5 and M8 form simple NMOS current mirroring circuits, and NMOS tube M6 and M7 form simple NMOS current mirrors
Circuit, NMOS tube M7 and M8 drain electrode meet input bias current source Ib2 and Ib1 respectively, and NMOS tube M6 drain electrode is connected to outside
Adjust the electric current input DAC of code control.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc., it should be included in the scope of the protection.
Claims (5)
1. for the insensitive common mode charge control devices of PVT of charge coupling assembly line analog to digital converter, it is characterized in that, including two
Individual output common mode tunable charge transmission circuit, a common mode detection adjustment circuit（33）, a shut-off voltage duplicate circuit（34）；
First output common mode tunable charge transmission circuit（31）With the second output common mode tunable charge transmission circuit（32）OUT terminal output
Signal is input to common mode detection adjustment circuit（33）, common mode detection adjustment circuit（33）According to the first output common mode tunable charge
Transmission circuit（31）OUT signal, the second output common mode tunable charge transmission circuit OUT signal, control clock and reference electricity
Press VREFHandled and by output feedback signal Vfb, feedback signal Vfb is connected respectively to two output common mode tunable charges and passed
The output common mode of the P ends regulation OUT terminal on transmission of electricity road, turns off voltage duplicate circuit（34）According to reference voltage VR,1Produce substrate control
The B ends of two output common mode tunable charge transmission circuits of voltage Vbody connections processed；First output common mode tunable charge transmission circuit
（31）With the second output common mode tunable charge transmission circuit（32）Output OUT is each produced according to the signal at IN ends, B ends and P ends
Signal, the OUT signal of fully differential detect adjustment circuit by common mode（33）While detection, next stage common mode electricity is also directly output to
Lotus control circuit；
Described output common mode tunable charge transmission circuit includes：NMOS tube M4 and NMOS tube M1 drain electrode are connected to simultaneously
NMOS tube M2 source electrode, NMOS tube M4 and M1 source electrode are connected to ground simultaneously, and NMOS tube M1 and M4 grid connect IN respectively
End and P ends, and NMOS tube M1 substrate electric potential is controlled by B ends；NMOS tube M2 drain electrode is connected to electric charge transmission NMOS tube Ms
Grid and PMOS M3 drain electrode, while be also connected to NMOS tube Men drain electrode, NMOS tube M2 grid connects bias voltage
Vbn；PMOS M3 source electrode is connected to PMOS Mep drain electrode, and PMOS M3 grid meets bias voltage Vbp, PMOS M3
Drain electrode connect NMOS tube Men drain electrode；PMOS Mep source electrode connects supply voltage, and PMOS Mep grid connects work clock
Ck0；NMOS tube Men source ground, NMOS tube Men grid meet work clock Ck0；Electric charge transmission NMOS tube Ms sources, leakage and
Grid end connects the drain electrode at IN ends, OUT terminal and NMOS tube M2 respectively.
2. the insensitive common mode charge control dresses of PVT for charge coupling assembly line analog to digital converter according to claim 1
Put, it is characterized in that, the common mode detects adjustment circuit（33）Output to first, second output common mode tunable charge transmission circuit
The adjustment of common mode charge is the P by controlling the metal-oxide-semiconductor M4 inside first, second output common mode tunable charge transmission circuit respectively
Realize at end.
3. the insensitive common mode charge control dresses of PVT for charge coupling assembly line analog to digital converter according to claim 1
Put, it is characterized in that, the shut-off voltage duplicate circuit（34）Output to first, second output common mode tunable charge transmission circuit
The adjustment of common mode charge is by controlling the metal-oxide-semiconductor M1 inside first, second output common mode tunable charge transmission circuit respectively
Realize at underlayer voltage B ends.
4. the insensitive common mode charge control dresses of PVT for charge coupling assembly line analog to digital converter according to claim 1
Put, it is characterized in that, the common mode detects adjustment circuit（33）Including a common-mode error amplifier module and an error signal
Processing module, common-mode error amplifier module are carried out under the control of control clock to difference output charge signal and Vref signal
Compare, and result is output to error signal processing module；Error signal processing module to common-mode error signal handle
To Vfb output signals, for controlling the P ends of output common mode tunable charge transmission circuit.
5. the insensitive common mode charge control dresses of PVT for charge coupling assembly line analog to digital converter according to claim 4
Put, it is characterized in that, the common mode detects adjustment circuit（33）Internal error signal processing module is amplified using programmable trans-conductance
Device circuit.
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| CN106208982B (en) * | 2016-07-15 | 2019-01-18 | 天津大学 | A kind of trsanscondutance amplifier imbalance elimination structure based on output electric current storage |
| CN106330189B (en) * | 2016-08-24 | 2019-05-21 | 黄山学院 | A kind of charge-domain capacitor digital conversion circuit |
| CN106656183B (en) * | 2016-12-20 | 2020-03-31 | 中国电子科技集团公司第五十八研究所 | Input common-mode error feedforward compensation circuit of pipeline analog-to-digital converter |
| CN107863964B (en) * | 2017-11-10 | 2019-09-24 | 中国电子科技集团公司第五十八研究所 | Accurately control the fully differential charge transfer circuit of common mode charge amount |
| CN107872226B (en) * | 2017-11-10 | 2019-09-03 | 中国电子科技集团公司第五十八研究所 | The charge-domain pipelined ADC calibrated using high-precision numerical model analysis |
| CN107733432B (en) * | 2017-11-10 | 2019-09-03 | 中国电子科技集团公司第五十八研究所 | Charge-domain pipelined ADC common mode charge error calibration system in high precision |
| CN107863962B (en) * | 2017-11-10 | 2019-09-03 | 中国电子科技集团公司第五十八研究所 | The capacitor unbalance calibration system of charge-domain pipelined ADC in high precision |
| CN109150188B (en) * | 2018-08-10 | 2019-07-02 | 上海奥令科电子科技有限公司 | A kind of current mode digital-to-analog converter output-stage circuit of adjustable output common mode level |
| CN111865307B (en) * | 2020-07-09 | 2022-03-01 | 同济大学 | Noise shaping analog-to-digital converter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101454843A (en) * | 2006-05-31 | 2009-06-10 | 肯奈特公司 | Boosted charge transfer pipeline |
| CN101860368A (en) * | 2010-05-10 | 2010-10-13 | 中国电子科技集团公司第五十八研究所 | Negative-voltage effective transmission circuit suitable for standard CMOS process |
| US8222954B1 (en) * | 2009-01-29 | 2012-07-17 | Xilinx, Inc. | Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device |
| CN103036538A (en) * | 2012-12-06 | 2013-04-10 | 国民技术股份有限公司 | Circuit and method for correcting offset voltage of comparator |
-
2014
- 2014-10-13 CN CN201410539911.1A patent/CN104270152B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101454843A (en) * | 2006-05-31 | 2009-06-10 | 肯奈特公司 | Boosted charge transfer pipeline |
| US8222954B1 (en) * | 2009-01-29 | 2012-07-17 | Xilinx, Inc. | Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device |
| CN101860368A (en) * | 2010-05-10 | 2010-10-13 | 中国电子科技集团公司第五十八研究所 | Negative-voltage effective transmission circuit suitable for standard CMOS process |
| CN103036538A (en) * | 2012-12-06 | 2013-04-10 | 国民技术股份有限公司 | Circuit and method for correcting offset voltage of comparator |
Non-Patent Citations (3)
| Title |
|---|
| A 27-mW 10-bit 125-MSPS charge domain pipelined ADC with a PVT insensitive boosted charge transfer circuit;陈珍海，黄嵩人，张鸿，于宗光，季惠才;《Journal of Semiconductors》;20130315;第34卷(第3期);全文 * |
| A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling;陈珍海，钱宏文，黄嵩人，张鸿，于宗光;《Journal of Semiconductors》;20130615;第34卷(第6期);全文 * |
| A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs;Zhanghai Chen,Zongguang Yu,Songren Huang,Hong Zhang,Huicai Ji;《IEICE Electronics Express》;20120325;第9卷(第6期);全文 * |
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