CN104184465B - Phase frequency detector for phaselocked loop - Google Patents
Phase frequency detector for phaselocked loop Download PDFInfo
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- CN104184465B CN104184465B CN201310203013.4A CN201310203013A CN104184465B CN 104184465 B CN104184465 B CN 104184465B CN 201310203013 A CN201310203013 A CN 201310203013A CN 104184465 B CN104184465 B CN 104184465B
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Abstract
The invention discloses a kind of phase frequency detector for phaselocked loop, including：Four edge generation circuits, respectively first and two the rising and falling edges of input signal produce first and two positive negative pulse stuffing signals；First and two MOS transistor cascaded structures, it is in series respectively by PMOS and NMOS tube, the grid of first PMOS connects the first undersuing, the grid of first NMOS tube connects the second positive pulse signal, the grid of second PMOS connects the second undersuing, and the grid of the second NMOS tube connects the first positive pulse signal；First and two nor gates, first and two MOS transistor cascaded structure output end signal connected after the delay of even number of inverters be connected respectively to first and two nor gate two inputs, first and two nor gate output end respectively export decline and rise control signal.The present invention can improve the accurate working frequency for detecting phase difference, improve phase-locked loop performance.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of phase frequency detector for phaselocked loop.
Background technology
Although Phase Lock Technique has pointed out nearly 100 years, be widely used in electronic system, while the requirement to performance is also more next
It is higher.Present PLL chips are towards frequency height, bandwidth, integrated level are big, the direction hair such as low in energy consumption, cheap, powerful
Exhibition, but with working frequency more and more higher, larger " dead band " be present due to phase frequency detector this body structure is without correct
Detect phase difference and decline phase-locked loop performance, so how to design for the phase frequency detector of upper frequency is high property
Energy Design of PLL needs the subject matter solved.
Phaselocked loop is that have nonlinear reponse system.However, by linear analysis can be basic to its operation make
It is approximate well.In such analysis, Laplace conversion is a very useful instrument.The related notion of transfer function, i.e.,
The input of one linear circuit of description and output end are used for open loop and the closed loop characteristic for analyzing PLL in the relation in S domains.Such as
It is the S domains schematic diagram of a simplified phaselocked loop shown in Fig. 1.Module 101 is phase frequency detector (phase-frequency
Detectors, PFD) and charge pump merging module, by configured transmission KPFDRepresent, configured transmission KPFDEqual to ICP/ 2 π, Icp namely
For the Iout in Fig. 1（s）.The impedance for the low pass filter that second-order loop filter is formed is by ZLPF(S)Represent.Module 103 represents
Voltage controlled oscillator（VCO）, its conversion gain KVCORepresent for VT Vcont（s）The susceptibility of frequency.Pre- frequency dividing circuit
104 and low frequency frequency divider 105 be respectively used to divide, pre- frequency dividing circuit 104 and low frequency frequency divider 105 divider ratios are respectively by P and N
Represent, module 103 output frequency signal Fout, the pre- output frequency signal Fout/P of frequency dividing circuit 104, low frequency frequency divider 105 is defeated
Go out frequency signal Fbck.Above-mentioned synthesizer is that the open-loop transmission function of phaselocked loop can be defined as：
Show the limit of an at the origin as caused by VCO.The dynamic characteristic of whole loop is by loop filter
Transfer function determines that it is an impedance function in this example, and charge pump current is converted into VCO VT by it.
ZLPF(s) it is expressed as
Equation（2）Show the limit of first loop filter in ωp1At=0, zero point exists
ωz=1/R1C1（3）
The limit of two at the origins（First due to VCO produce, second is ωp1）It can compensate when phase margin is
Loop is unstable when 0.Add ωzLoop is stabilized, suitable position can provide enough phase margins, to ensure loop
It is stable.In order to obtain one for the significant expression formula of second limit, i.e., and ωzIt is related.By in formula（2）Middle introducing
Variable m=(C1+C2)/C2, obtain：
It shows that the limit of second loop filter exists
By ZLPF(s) abbreviation into
Use formula（6）, open-loop transmission function can be re-written as：
Wherein A is
The amplitude and phase of open-loop transmission function can be drawn in Bode diagram, for check the position of pole and zero with
And the condition of loop stability.As shown in Fig. 2 in zero point ωz, slope drops to 20dB/dec by 40, it is often more important that, make phase
Increase since -180 degree.Amplitude is that the value of phase at 1 or 0-dB is referred to as phase margin（PM）.The crosspoint of frequency is PLL
Loop bandwidth, by ωcRepresent.The calculating of the latter is by making formula（7）HOL(s) amplitude is 1, so as to obtain：
Wherein, φz=tan-1(ωc/ωz), φp2=tan-1(ωc/ωp2).Phase margin is expressed as：
It is desirable that to make phase margin maximum to ensure the stabilization of loop, also to meet to determine pole and zero position certainly
The resistance put and the change of capacitance.Possible maximum phase nargin can be by formula（10）Differentiated and obtained
Arrive：
By ωcSubstitute into formula（10）, obtain maximum phase nargin：
Formula（11）,（12）Show, for best stabilized（Maximum PM）, unit gain crosspoint should be zero point and the
The geometrical mean of two limits, because this is the phase position farthest from 180 degree.Maximum phase nargin is by capacitance ratio
（m）Unique to determine, it is also second limit（ωp2）And zero point（ωz）Ratio.Make It may be noted that sin (φz)=cos (φp2), by formula（9）It is reduced to
Three rank PLL closed loop transmission function is：
Understand that phase frequency detector determines the height of phase-locked loop performance to a certain extent by above theory analysis, so PFD
The speed and sensitivity design of module are most important.As shown in figure 3, it is the circuit for the phase frequency detector for being currently used for phaselocked loop
Figure；Existing PFD is made up of d type flip flop and NAND gate, and its two basic RS filpflops are respectively used to store input input
Input signal fin and fb, the backfeed loop that the rising control signal up and decline control signal dn of output end output are formed can
Form reset function.When phase-locked loop operation is in stable state there is larger " dead band " in existing PFD, can so cause phaselocked loop to exist
In the presence of big shake during lock-out state.Another key factor is traditional PFD using internal feedback detection method, triggering
Signal is to rise control signal up and decline control signal dn just to arrive at target by the delay of six fan doors, and this is just seriously limited
Applications of the existing PFD in High-frequency PLL is made.As shown in figure 4, being the existing phase-locked loop structures shown in Fig. 3 in incoming frequency
1GHz, two inputs differ the simulation result under the conditions of 150ps square waves, ideally, rise control signal up and decline controls
Signal dn includes three states, and it is all low level that first state, which is rising control signal up and declines control signal dn,；Second
Individual state is that first state is that rising control signal up is high level, and it is low level to decline control signal dn；3rd state
It is that first state is that rising control signal up is low level, it is high level to decline control signal dn.And rise control signal up
All it is not present in the ideal situation for the state of high level with control signal dn is declined.And detect as can be seen from Figure 4 defeated
Go out to rise control signal up and decline control signal dn and be all in the presence of substantial amounts of rising control signal up and decline control signal dn
It the state of high level, can not correctly reflect fin, fb phase difference completely, also may result in phaselocked loop and lose its function.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of phase frequency detector for phaselocked loop, can improve accurate inspection
The working frequency of phase difference is measured, improves phase-locked loop performance.
In order to solve the above technical problems, include provided by the present invention for the phase frequency detector of phaselocked loop：
First trailing edge generation circuit, its input connect the first input signal, and output end is in first input signal
Falling edge produce the first undersuing.
First rising edge generation circuit, its input connect the first input signal, and output end is in first input signal
Rising edge at produce the first positive pulse signal.
Second trailing edge generation circuit, its input connect the second input signal, and output end is in second input signal
Falling edge produce the second undersuing.
Second rising edge generation circuit, its input connect the second input signal, and output end is in second input signal
Rising edge at produce the second positive pulse signal.
First MOS transistor cascaded structure, is in series by the first PMOS and the first NMOS tube, first PMOS
Source electrode connect power supply, the source ground of first NMOS tube, the grid of first PMOS connects first negative pulse
Signal, the grid of first NMOS tube connect second positive pulse signal, first PMOS and the first NMOS
The drain electrode of pipe is connected and as the output end of the first MOS transistor cascaded structure.
Second MOS transistor cascaded structure, is in series by the second PMOS and the second NMOS tube, second PMOS
Source electrode connect power supply, the source ground of second NMOS tube, the grid of second PMOS connects second negative pulse
Signal, the grid of second NMOS tube connect first positive pulse signal, second PMOS and the 2nd NMOS
The drain electrode of pipe is connected and as the output end of the second MOS transistor cascaded structure.
First nor gate and the second nor gate, the output end signal of the first MOS transistor cascaded structure is through M first
Connection is connected respectively to the first input end of first nor gate and second nor gate after the delay of phase inverter, and described the
The connection after the delay of M the first phase inverters of the output end signal of two MOS transistor cascaded structures is connected respectively to described first
Second input of nor gate and second nor gate, M are even number.
The output end output of first nor gate declines control signal, and the output end output of second nor gate rises
Control signal.
Further improve is that the first trailing edge generation circuit includes the first NAND gate, first input signal
First inversion signal is formed by one second phase inverter, it is first defeated to be input to first NAND gate for first inversion signal
Enter end, first inversion signal by the delay of N number of second phase inverter and it is anti-phase after be input to the of first NAND gate
Two inputs, N are odd number, and the output end of first NAND gate exports first undersuing.
The first rising edge generation circuit includes the second NAND gate, first input signal be input to described second with
The first input end of NOT gate, first input signal by the delay of N number of second phase inverter and it is anti-phase after be input to described
Second input of two NAND gates, the output end of second NAND gate by one the 3rd phase inverter it is anti-phase after output described the
One positive pulse signal.
The second trailing edge generation circuit includes the 3rd NAND gate, and second input signal passes through one second phase inverter
The second inversion signal is formed, second inversion signal is input to the first input end of the 3rd NAND gate, and described second is anti-
Phase signals by the delay of N number of second phase inverter and it is anti-phase after be input to the second input of the 3rd NAND gate, described the
The output end of three NAND gates exports second undersuing.
The second rising edge generation circuit includes the 4th NAND gate, second input signal be input to the described 4th with
The first input end of NOT gate, second input signal by the delay of N number of second phase inverter and it is anti-phase after be input to described
Second input of four NAND gates, the output end of the 4th NAND gate by one the 3rd phase inverter it is anti-phase after output described the
Two positive pulse signals.
Further improve is M 2, N 3.
The present invention can guarantee that signal passing time is identical using full symmetrical configuration detection phase difference, and the present invention is without internal feedback
Delay can enable phaselocked loop to work in higher frequency, so as to also can guarantee that inspection that can be intact when working frequency is higher
Phase difference is measured, so as to be supplied to the accurate control voltage of voltage controlled oscillator, shake can be reduced, output is accurately tracked
It the change of input, can be provided safeguard to High-Performance Phase-Locked, the design object of High-Performance Phase-Locked can be realized.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the S domains schematic diagram of phaselocked loop；
Fig. 2 is the Bode diagram of phaselocked loop；
Fig. 3 is the circuit diagram for the phase frequency detector for being currently used for phaselocked loop；
Fig. 4 is the simulation result under the high frequency of the existing phase frequency detector shown in Fig. 3；
Fig. 5 is the circuit diagram for the phase frequency detector that the embodiment of the present invention is used for phaselocked loop；
Fig. 6 is the simulation result under the high frequency of the phase frequency detector of the embodiment of the present invention shown in Fig. 5.
Embodiment
As shown in figure 5, it is the circuit diagram for the phase frequency detector that the embodiment of the present invention is used for phaselocked loop.The embodiment of the present invention is used
Include in the phase frequency detector of phaselocked loop：
First trailing edge generation circuit 1, its input connect the first input signal fin, and output end is in the described first input
Signal fin falling edge produces the first undersuing.First input signal fin described in the embodiment of the present invention is the lock
The input frequency signal that phase ring receives.
First rising edge generation circuit 2, its input connect the first input signal fin, and output end is in the described first input
The first positive pulse signal is produced at signal fin rising edge.
Second trailing edge generation circuit 3, its input connect the second input signal fb, and output end is in the described second input letter
Number fb falling edge produces the second undersuing.Second input signal fb described in the embodiment of the present invention is the phaselocked loop
Caused output frequency signal caused feedback signal after frequency dividing.
Second rising edge generation circuit 4, its input connect the second input signal fb, and output end is in the described second input letter
The second positive pulse signal is produced at number fb rising edge.
First MOS transistor cascaded structure 5, it is in series by the first PMOS MP1 and the first NMOS tube MN1, described
One PMOS MP1 source electrode connects power supply, the source ground of the first NMOS tube MN1, and the grid of the first PMOS MP1 connects
Connecing first undersuing, the grid of the first NMOS tube MN1 connects second positive pulse signal, and described first
PMOS MP1 and the first NMOS tube MN1 drain electrode are connected and as the defeated of the first MOS transistor cascaded structure 5
Go out end.
Second MOS transistor cascaded structure 6, it is in series by the second PMOS MP2 and the second NMOS tube MN2, described
Two PMOS MP2 source electrode connects power supply, the source ground of the second NMOS tube MN2, and the grid of the second PMOS MP2 connects
Connecing second undersuing, the grid of the second NMOS tube MN2 connects first positive pulse signal, and described second
PMOS MP2 and the second NMOS tube MN2 drain electrode are connected and as the defeated of the second MOS transistor cascaded structure 6
Go out end.
First nor gate 7 and the second nor gate 8, the output end signal of the first MOS transistor cascaded structure 5 is through M
Connection is connected respectively to the first input of first nor gate 7 and second nor gate 8 after the delay of first phase inverter 13
End, the output end signal of the second MOS transistor cascaded structure 6 connects after the delay of M the first phase inverters 13 to be connected respectively
The second input of first nor gate 7 and second nor gate 8 is connected to, M is even number, and M is 2 in the preferred embodiment.
The output end output of first nor gate 7 declines control signal dn, the output end output of second nor gate 8
Rise control signal up.
The first trailing edge generation circuit 1 includes the first NAND gate 9, and the first input signal fin passes through one second
Phase inverter 14 forms the first inversion signal, and first inversion signal is input to the first input end of first NAND gate 9, institute
State the first inversion signal by the delay of N number of second phase inverter 14 and it is anti-phase after be input to the second defeated of first NAND gate 9
Enter end, N is odd number, and the output end of first NAND gate 9 exports first undersuing.N is in the preferred embodiment
3。
The first rising edge generation circuit 2 includes the second NAND gate 10, and the first input signal fin is input to described
The first input end of second NAND gate 10, the first input signal fin by the delay of N number of second phase inverter 14 and it is anti-phase after
The second input of second NAND gate 10 is input to, the output end of second NAND gate 10 passes through one the 3rd phase inverter 15
It is anti-phase after output first positive pulse signal.
The second trailing edge generation circuit 3 includes the 3rd NAND gate 11, and the second input signal fb passes through one second
Phase inverter 14 forms the second inversion signal, and second inversion signal is input to the first input end of the 3rd NAND gate 11,
Second inversion signal by N number of second phase inverter 14 delay and it is anti-phase after be input to the second of the 3rd NAND gate 11
Input, the output end of the 3rd NAND gate 11 export second undersuing.
The second rising edge generation circuit 4 includes the 4th NAND gate 12, and the second input signal fb is input to described
The first input end of 4th NAND gate 12, the second input signal fb by the delay of N number of second phase inverter 14 and it is anti-phase after
The second input of the 4th NAND gate 12 is input to, the output end of the 4th NAND gate 12 passes through one the 3rd phase inverter 15
It is anti-phase after output second positive pulse signal.
Second phase inverter 14 described in the embodiment of the present invention can use mutually isostructural anti-with the 3rd phase inverter 15
Phase device, also can first phase inverter 13, second phase inverter 14 and the 3rd phase inverter 15 all using mutually isostructural
Phase inverter.So as to which Fig. 5 four edge generation circuits 1,2,3 and 4 that can be seen that the embodiment of the present invention are prolonged using phase inverter
Shi Danyuan and NAND gate complete the detection to input signal edge, because edge sense circuit namely edge generation circuit have phase
Same logical path, change of the edge signal simultaneously to input can be caused to make a response, it is " dead so to avoid input signal
The presence in area ".The decline control signal dn and rising control signal up of the output of the embodiment of the present invention are not fed back to input
End, so detection method of the embodiment of the present invention using non-feedback mechanism, so speed has obtained large increase.The present invention
Embodiment output end using nor gate come the difference of detection signal, so as to correctly reflect the phase difference of input.Such as Fig. 6 institutes
Show, be PFD of the embodiment of the present invention shown in Fig. 5 in incoming frequency be 1GHz, two input differences are the side of 150 psecs for 150ps
Simulation result under the conditions of ripple, it can be clearly seen that output signal reflects the difference of input well, more it is desirable that
It is full width to decline control signal dn, rises the maximum shakes only less than 2mv of control signal up, so to whole phase-locked loop performance
Performance have very great help.So the PFD that can prove the structure through result above has at a relatively high performance in higher frequency band,
Application to High-frequency PLL has great significance.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (2)
1. a kind of phase frequency detector for phaselocked loop, it is characterised in that phase frequency detector includes：
First trailing edge generation circuit, its input connect the first input signal, and output end is under first input signal
Drop produces the first undersuing at；
First rising edge generation circuit, its input connect the first input signal, and output end is upper first input signal
Rise and the first positive pulse signal is produced at；
Second trailing edge generation circuit, its input connect the second input signal, and output end is under second input signal
Drop produces the second undersuing at；
Second rising edge generation circuit, its input connect the second input signal, and output end is upper second input signal
Rise and the second positive pulse signal is produced at；
First MOS transistor cascaded structure, is in series by the first PMOS and the first NMOS tube, the source of first PMOS
Pole connects power supply, the source ground of first NMOS tube, and the grid of first PMOS connects first undersuing,
The grid of first NMOS tube connects second positive pulse signal, the leakage of first PMOS and first NMOS tube
Pole is connected and is used as the output end of the first MOS transistor cascaded structure；
Second MOS transistor cascaded structure, is in series by the second PMOS and the second NMOS tube, the source of second PMOS
Pole connects power supply, the source ground of second NMOS tube, and the grid of second PMOS connects second undersuing,
The grid of second NMOS tube connects first positive pulse signal, the leakage of second PMOS and second NMOS tube
Pole is connected and is used as the output end of the second MOS transistor cascaded structure；
First nor gate and the second nor gate, the output end signal of the first MOS transistor cascaded structure are anti-phase through M individual first
Connection is connected respectively to the first input end of first nor gate and second nor gate after the delay of device, and described second
The connection after the delay of M the first phase inverters of the output end signal of MOS transistor cascaded structure be connected respectively to described first or
Second input of NOT gate and second nor gate, M are even number；
The output end output of first nor gate declines control signal, and the output end output of second nor gate rises control
Signal；
The first trailing edge generation circuit includes the first NAND gate, and first input signal is formed by one second phase inverter
First inversion signal, first inversion signal are input to the first input end of first NAND gate, the first anti-phase letter
Number by the delay of N number of second phase inverter and it is anti-phase after be input to the second input of first NAND gate, N is odd number, institute
The output end for stating the first NAND gate exports first undersuing；
The first rising edge generation circuit includes the second NAND gate, and first input signal is input to second NAND gate
First input end, first input signal by the delay of N number of second phase inverter and it is anti-phase after be input to described second with
Second input of NOT gate, the output end of second NAND gate are exporting described first just afterwards by the anti-phase of one the 3rd phase inverter
Pulse signal；
The second trailing edge generation circuit includes the 3rd NAND gate, and second input signal is formed by one second phase inverter
Second inversion signal, second inversion signal are input to the first input end of the 3rd NAND gate, the second anti-phase letter
Number by the delay of N number of second phase inverter and it is anti-phase after be input to the second input of the 3rd NAND gate, the described 3rd with
The output end of NOT gate exports second undersuing；
The second rising edge generation circuit includes the 4th NAND gate, and second input signal is input to the 4th NAND gate
First input end, second input signal by the delay of N number of second phase inverter and it is anti-phase after be input to the described 4th with
Second input of NOT gate, the output end of the 4th NAND gate are exporting described second just afterwards by the anti-phase of one the 3rd phase inverter
Pulse signal.
2. it is used for the phase frequency detector of phaselocked loop as claimed in claim 1, it is characterised in that：M is 2, N 3.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1494218A (en) * | 2002-12-26 | 2004-05-05 | 北京大学 | Discriminator and lock phase ring using said discriminator |
| CN1633027A (en) * | 2003-12-22 | 2005-06-29 | 上海贝岭股份有限公司 | A frequency and phase discriminator circuit with effective double frequency error-locking suppression |
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2013
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1494218A (en) * | 2002-12-26 | 2004-05-05 | 北京大学 | Discriminator and lock phase ring using said discriminator |
| CN1633027A (en) * | 2003-12-22 | 2005-06-29 | 上海贝岭股份有限公司 | A frequency and phase discriminator circuit with effective double frequency error-locking suppression |
Non-Patent Citations (1)
| Title |
|---|
| 0.25μm CMOS千兆以太网发送器设计;黎飞 等;《电子工程师》;20041231;第30卷(第12期);第26-29页 * |
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