CN104242923A - Voltage-controlled oscillator - Google Patents

Abstract

The invention discloses a voltage-controlled oscillator. The voltage-controlled oscillator comprises a control voltage gain circuit and an annular oscillating circuit. The control voltage gain circuit comprises a first NMOS transistor and a cascode current mirror circuit which are connected with a common source; the source electrode of the first NMOS transistor is grounded through a first resistor and achieves negative feedback. The cascode current mirror circuit outputs control voltage amplification signals. The control voltage amplification signals are input to the control end of the annular oscillating circuit and used for controlling the output frequency of the annular oscillating circuit. The voltage-controlled oscillator can improve the linearity of the circuits, lower the power consumption of the circuits, improve the quality of clock signals and provide a guarantee for system stability.

Description

Voltage controlled oscillator

Technical field

The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of voltage controlled oscillator (VCO).

Background technology

Although VCO and PHASE-LOCKED LOOP PLL TECHNIQUE have proposed nearly 100 years, be widely used in electronic system, simultaneously also more and more higher to the requirement of performance.The future developments such as present PLL chip is high towards frequency, bandwidth, integrated level are large, low in energy consumption, cheap, powerful, wherein the design of core cell VCO is most important, current VCO designs the subject matter faced the restriction of adjustable range: under the change of extreme flow-route and temperature, the centre frequency of some CMOS oscillators may change to twice, and the restriction of adjustable range may make its afunction.Tuning linearity: the non-linear stability of phase-locked loop that makes is degenerated still along with operating frequency is more and more higher.Power consumption is excessive has a strong impact on its scope of application.So ensure when how to design high-performance VCO circuit that system stability needs the subject matter solved.

Phase-locked loop has nonlinear reponse system.But, can the operation basic to it make well approximate by linear analysis.In such analysis, Laplace conversion is a very useful instrument.The related notion of transfer function, namely describes input and the relation of output in S territory of a linear circuit, is used to the Open loop and closed loop characteristic analyzing PLL.As shown in Figure 1, be the S territory schematic diagram of phase-locked loop simplified.Module 101 is that phase frequency detector (phase-frequency detectors, PFD) and charge pump merge module, by transformation parameter K _pFDrepresent, transformation parameter K _pFDequal I _cP/ 2 π, Icp are also the Iout(s in Fig. 1).The impedance of the low pass filter that second-order loop filter is formed is by Z _{lPF (S)}represent.Module 103 represents voltage controlled oscillator (VCO), its conversion gain K _vCOrepresent for tuning voltage Vcont(s) susceptibility of frequency.Pre-frequency dividing circuit 104 and low frequency divider 105 are respectively used to frequency division, pre-frequency dividing circuit 104 and low frequency divider 105 divider ratios are represented by P and N respectively, module 103 output frequency signal Fout, pre-frequency dividing circuit 104 output frequency signal Fout/P, low frequency divider 105 output frequency signal F _bck.The open-loop transmission function of above-mentioned synthesizer and phase-locked loop can be defined as:

$H_{\mathrm{OL}}\left(s\right)=\frac{K_{\mathrm{PFD}}{K}_{\mathrm{VCO}}{Z}_{\mathrm{LPF}}\left(s\right)}{N\·P\·s}---\left(1\right)$

Show a limit at initial point caused by VCO.The dynamic characteristic of whole loop is determined by the transfer function of loop filter, and it is an impedance function in this example, and charge pump current is converted to the tuning voltage of VCO by it.Z _lPFs () is expressed as

$Z_{\mathrm{LPF}}\left(s\right)=\frac{1+s{R}_1{C}_1}{s(s{R}_1{C}_1{C}_2+C_1+C_2)}---\left(2\right)$

Equation (2) shows that the limit of first loop filter is at ω _p1=0 place, zero point exists

ω _z＝1/R ₁C ₁ （3）

(first produces due to VCO, and second is ω for two limits at initial point place _p1) the astable of when phase margin is 0 loop can be compensated.Add ω _zstabilize loop, suitable position can provide enough phase margins, to guarantee loop stability.In order to obtain one for second significant expression formula of limit, namely and ω _zrelevant.By introducing variable m=(C in formula (2) ₁+ C ₂)/C ₂, obtain:

$Z_{\mathrm{LPF}}\left(s\right)=R_1\frac{1+s/{\mathrm{\ω}}_z}{s(1+\frac{\frac{s}{C_1+C_2}}{R_1{C}_1{C}_2})/{\mathrm{\ω}}_z}\frac{m-1}{m}---\left(4\right)$

It shows that the limit of second loop filter exists

${\mathrm{\ω}}_{p2}=\frac{1}{R_1{C}_1}\frac{C_1+C_2}{C_2}=m{\mathrm{\ω}}_z---\left(5\right)$

By Z _lPFs () abbreviation becomes

$Z_{\mathrm{LPF}}\left(s\right)=R_1\frac{1+s/{\mathrm{\ω}}_z}{s(1+\frac{s}{{\mathrm{\ω}}_{P2}})}\frac{m-1}{m}---\left(6\right)$

Use formula (6), open-loop transmission function can be written as again:

$H_{\mathrm{OL}}\left(s\right)=A\frac{1+s/{\mathrm{\ω}}_z}{s^2(1+\frac{s}{{\mathrm{\ω}}_{p2}})/{\mathrm{\ω}}_z}\frac{m-1}{m}---\left(7\right)$

Wherein A is

$A=\frac{K_{\mathrm{PFD}}{K}_{\mathrm{VCO}}{R}_1}{N\·P}---\left(8\right)$

Amplitude and the phase place of open-loop transmission function can be drawn, for the condition of the position and loop stability of checking pole and zero in Bode diagram.As shown in Figure 2, at ω at zero point _z, slope drops to 20dB/dec by 40, the more important thing is, phase place is increased from-180 degree.Amplitude be 1 or the value of 0-dB place phase place be called phase margin (PM).The crosspoint of frequency is the loop bandwidth of PLL, by ω _crepresent.The calculating of the latter is by making formula (7) H _oLs the amplitude of () is 1, thus obtain:

${\mathrm{\ω}}_c=A\frac{m-1}{m}\frac{\cos \left({\mathrm{\φ}}_{p2}\right)}{\sin \left({\mathrm{\φ}}_z\right)}---\left(9\right)$

Wherein, φ _z=tan ^-1(ω _c/ ω _z), φ _p2=tan ^-1(ω _c/ ω _p2).Phase margin is expressed as:

Ideally, phase margin be made maximum to guarantee the stable of loop, certainly also will meet and determine the resistance of pole and zero position and the change of capacitance.Possible maximum phase nargin can be passed through differentiate to formula (10) and obtain:

${\left({\mathrm{\ω}}_c\right)}_{\mathrm{for}\max \mathrm{PM}}=\sqrt{{\mathrm{\ω}}_z{\mathrm{\ω}}_{p2}}=\sqrt{m}{\mathrm{\ω}}_z---\left(11\right)$

By ω _csubstitute into formula (10), obtain maximum phase nargin:

Formula (11), (12) show, for best stabilized (maximum PM), unit gain crosspoint should be the geometrical mean of zero point and the second limit, because this is phase place from 180 degree of positions farthest.Maximum phase nargin is uniquely determined by capacitance ratio (m), and it is also second limit (ω _p2) and zero point (ω _z) ratio.Make sin (φ can be noticed _z)=cos (φ _p2), formula (9) is reduced to

${\mathrm{\ω}}_c=A\frac{m-1}{m}=\frac{K_{\mathrm{PFD}}{K}_{\mathrm{VCO}}{R}_1}{N\·P}\frac{m-1}{m}=\frac{K_{\mathrm{PFD}}{K}_{\mathrm{VCO}}{R}_1}{N\·P}\frac{C_1}{C_1+C_2}---\left(13\right)$

The closed loop transmission function of three rank PLL is:

$H_{\mathrm{CL}}\left(s\right)=\frac{1+s/{\mathrm{\ω}}_z}{1+\frac{s}{{\mathrm{\ω}}_z}+\frac{s^2}{K{\mathrm{\ω}}_z\frac{m-1}{m}}(1+\frac{s}{{\mathrm{\ω}}_{p2}})}---\left(14\right)$

The height of phase-locked loop performance is determined to a certain extent, so the design of VCO module is most important by the known voltage controlled oscillator of above theory analysis.Wherein VCO design important performance characteristic as: adjustable range, tuning linearity, output amplitude, power consumption and noise inhibiting ability reflect the quality of VCO performance intuitively.In addition, USB2.0 interface circuit designs for the general module of various chips, uses extensively; When working in high speed mode, need to use phase-locked loop will provide the clock of 480MHz to USB2.0 interface circuit, so wherein the performance parameter of VCO is if adjustable range, tuning linearity, output amplitude, power consumption, phase noise etc. are all to whole system important, the clock signal therefore VCO being improved to the 480MHz optimized needed for USB2.0 interface circuit is a very important problem.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of voltage controlled oscillator, can improve the linearity of circuit and reduce the power consumption of circuit, can improve the quality of clock signal and provide safeguard for system stability.

For solving the problems of the technologies described above, voltage controlled oscillator provided by the invention comprises control voltage gain circuitry and annular oscillation circuit.

Control voltage gain circuitry comprises:

First NMOS tube, the grid of described first NMOS tube connects the control voltage of input, and the source electrode of described first NMOS tube is by the first grounding through resistance, and the drain electrode of described first NMOS tube connects common-source common-gate current mirror circuit.

Described common-source common-gate current mirror circuit comprises the first PMOS, second PMOS, 3rd PMOS and the 4th PMOS, the drain electrode of described first NMOS tube, the drain electrode of described first PMOS, the grid of described 3rd PMOS and described 4th PMOS links together, the grid of described first PMOS and described second PMOS all connects same bias voltage, the source electrode of described first PMOS is connected with the drain electrode of described 3rd PMOS, the source electrode of described second PMOS is connected with the drain electrode of described 4th PMOS, the source electrode of described 3rd PMOS and described 4th PMOS all connects supply voltage, the drain electrode of described second PMOS exports control voltage amplifying signal.

Described control voltage amplifying signal is input to the control end of described annular oscillation circuit and the output frequency for controlling described annular oscillation circuit.

Further improvement is, described bias voltage is provided by the first biasing circuit, described first biasing circuit comprises: the second NMOS tube, 3rd NMOS tube, 5th PMOS and the 6th PMOS, the source ground of described second NMOS tube, the source electrode of described 3rd NMOS tube connects the drain and gate of described second NMOS tube, the grid of the grid of described 5th PMOS and drain electrode and described 7th PMOS and drain electrode link together and as the output of described bias voltage, the source electrode of described 5th PMOS connects the drain and gate of described 6th PMOS, the source electrode of described 6th PMOS connects supply voltage.

Further improvement is, described annular oscillation circuit is joined end to end by three grades of fully differential inverter delay units and formed.

Described fully differential inverter delay unit at different levels comprises normal phase input end, inverting input, positive output end, reversed-phase output and control end, the normal phase input end of described fully differential inverter delay unit at different levels connects the positive output end of fully differential inverter delay unit described in upper level, the inverting input of described fully differential inverter delay unit at different levels connects the reversed-phase output of fully differential inverter delay unit described in upper level, the positive output end of described fully differential inverter delay unit at different levels is connected to the positive output end of fully differential inverter delay unit described in next stage, the reversed-phase output of described fully differential inverter delay unit at different levels is connected to the reversed-phase output of fully differential inverter delay unit described in next stage.

The control end of described fully differential inverter delay unit at different levels all connects described control voltage amplifying signal.

Further improvement is, described annular oscillation circuit also comprises six inverters, and positive output end and the reversed-phase output of described fully differential inverter delay unit at different levels export a clock signal respectively by an inverter.

Further improvement is, described fully differential inverter delay unit at different levels comprises all respectively:

The first negative circuit be made up of the 4th NMOS tube and the 7th PMOS, the grid of described 4th NMOS tube and described 7th PMOS links together as inverting input, and the drain electrode of described 4th NMOS tube and described 7th PMOS links together as reversed-phase output.

The second negative circuit be made up of the 5th NMOS tube and the 8th PMOS, the grid of described 5th NMOS tube and described 7th PMOS links together as normal phase input end, and the drain electrode of described 5th NMOS tube and described 8th PMOS links together as positive output end.

The source electrode of described 7th PMOS and described 8th PMOS all connects described control voltage amplifying signal, source electrode all ground connection of described 4th NMOS tube and described 5th NMOS tube.

6th NMOS tube and the 7th NMOS tube, the source ground of described 6th NMOS tube and described 7th NMOS tube, the drain electrode of described 6th NMOS tube, the grid of described 7th NMOS tube are all connected with described reversed-phase output, and the drain electrode of described 7th NMOS tube, the grid of described 6th NMOS tube are all connected with described positive output end.

Further improvement is, described fully differential inverter delay unit at different levels also comprises respectively:

8th NMOS tube, the source electrode of described 8th NMOS tube connects the source electrode of described 4th NMOS tube, and the grid of described 8th NMOS tube, drain electrode and source electrode link together.

9th NMOS tube, the source electrode of described 9th NMOS tube connects the source electrode of described 5th NMOS tube, and the grid of described 9th NMOS tube, drain electrode and source electrode link together.

9th PMOS, the source electrode of described 9th PMOS connects the source electrode of described 7th PMOS and described 8th PMOS, and the grid of described 9th PMOS, drain electrode and source electrode link together.

Further improvement is, the clock signal of the output of described voltage controlled oscillator to be input in USB2.0 interface circuit and to provide clock signal for described USB2.0 interface circuit.

Further improvement is, described voltage controlled oscillator provides the frequency of clock signal to be 480MHz for described USB2.0 interface circuit.

The present invention has following beneficial effect:

1, the first resistance of the present invention can realize source negative feedback, common-source common-gate current mirror circuit can improve Power Supply Rejection Ratio, design in conjunction with source negative feedback and common-source common-gate current mirror circuit can improve the linearity of circuit, thus expands the adjustable range of control voltage and can expand the frequency-tuning range of clock signal of circuit.

2, the present invention can realize lower integrated circuit average current, thus can reduce the power consumption of circuit.

3, the present invention can improve the quality of clock signal also for system stability provides safeguard:

Control voltage amplifying signal of the present invention is input in annular oscillation circuit after the 3rd PMOS and the 4th PMOS of common-source common-gate current mirror circuit, because the 3rd PMOS and the 4th PMOS can consume certain voltage, so the amplitude of oscillation of the fully differential inverter delay units at different levels of annular oscillation circuit can be made to be effectively controlled, the speed of clock signal and noise suppressed is made to obtain perfect compromise.

The each clock signal of the present invention exports respectively by an inverter, can realize rail-to-rail output.

The present invention, by arranging the 7th PMOS and the 8th PMOS in fully differential inverter delay unit at different levels, can realize positive feedback, accelerates the output upset of fully differential inverter delay unit at different levels.

The present invention can provide shunt capacitance for fully differential inverter delay unit at different levels by the setting of the 8th NMOS tube, the 9th NMOS tube and the 9th PMOS, thus can suppress VDD-to-VSS noise.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:

Fig. 1 is the S territory schematic diagram of phase-locked loop;

Fig. 2 is the Bode diagram of phase-locked loop;

Fig. 3 is embodiment of the present invention voltage-controlled oscillator circuit figure;

Fig. 4 is the fully differential inverter time-delay unit circuit figure adopted in the embodiment of the present invention;

Fig. 5 is the variation relation figure of clock signal frequency with control voltage of the embodiment of the present invention;

Fig. 6 is embodiment of the present invention circuit power consumption also Output simulation result;

Fig. 7 is embodiment of the present invention current phase noise Simulation result.

Embodiment

As shown in Figure 3, be embodiment of the present invention voltage-controlled oscillator circuit figure; Embodiment of the present invention voltage controlled oscillator comprises control voltage Vcontr gain circuitry and annular oscillation circuit.

Control voltage Vcontr gain circuitry comprises:

The grid of the first NMOS tube MN1, described first NMOS tube MN1 connects the control voltage Vcontr of input, and the source electrode of described first NMOS tube MN1 is by the first resistance R1 ground connection, and the drain electrode of described first NMOS tube MN1 connects common-source common-gate current mirror circuit.

Described common-source common-gate current mirror circuit comprises the first PMOS MP1, second PMOS MP2, 3rd PMOS MP3 and the 4th PMOS MP4, the drain electrode of described first NMOS tube MN1, the drain electrode of described first PMOS MP1, the grid of described 3rd PMOS MP3 and described 4th PMOS MP4 links together, the grid of described first PMOS MP1 and described second PMOS MP2 all connects same bias voltage, the source electrode of described first PMOS MP1 is connected with the drain electrode of described 3rd PMOS MP3, the source electrode of described second PMOS MP2 is connected with the drain electrode of described 4th PMOS MP4, the source electrode of described 3rd PMOS MP3 and described 4th PMOS MP4 all connects supply voltage, the drain electrode of described second PMOS MP2 exports control voltage amplifying signal.As seen from Figure 3, the branch road that the branch road be connected with described 3rd PMOS MP3 by described first PMOS MP1 is connected with described 4th PMOS MP4 with described second PMOS MP2 forms current mirroring circuit, forms cascade amplifying circuit by described second PMOS MP2 and described 4th PMOS MP4.

Described bias voltage is provided by the first biasing circuit, described first biasing circuit comprises: the second NMOS tube MN2, 3rd NMOS tube MN3, 5th PMOS MP5 and the 6th PMOS MP6, the source ground of described second NMOS tube MN2, the source electrode of described 3rd NMOS tube MN3 connects the drain and gate of described second NMOS tube MN2, the grid of the grid of described 5th PMOS MP5 and drain electrode and described 7th PMOS MP7 and drain electrode link together and as the output of described bias voltage, the source electrode of described 5th PMOS MP5 connects the drain and gate of described 6th PMOS MP6, the source electrode of described 6th PMOS MP6 connects supply voltage.

Described control voltage amplifying signal is input to the control end of described annular oscillation circuit and the output frequency for controlling described annular oscillation circuit.

Described annular oscillation circuit is joined end to end by three grades of fully differential inverter delay units 1 and is formed.Described fully differential inverter delay unit 1 at different levels comprises normal phase input end vp, inverting input vn, positive output end vop, reversed-phase output von and control end, the normal phase input end vp of described fully differential inverter delay unit 1 at different levels connects the positive output end vop of fully differential inverter delay unit 1 described in upper level, the inverting input vn of described fully differential inverter delay unit 1 at different levels connects the reversed-phase output von of fully differential inverter delay unit 1 described in upper level, the positive output end vop of described fully differential inverter delay unit 1 at different levels is connected to the positive output end vop of fully differential inverter delay unit 1 described in next stage, the reversed-phase output von of described fully differential inverter delay unit 1 at different levels is connected to the reversed-phase output von of fully differential inverter delay unit 1 described in next stage.The control end of described fully differential inverter delay unit 1 at different levels all connects described control voltage amplifying signal.

Described annular oscillation circuit also comprises six inverters 2, and positive output end vop and the reversed-phase output von of described fully differential inverter delay unit 1 at different levels export a clock signal respectively by an inverter 2.So the embodiment of the present invention can realize the output of the clock signal of six outs of phase.

As shown in Figure 4, be the fully differential inverter time-delay unit circuit figure adopted in the embodiment of the present invention; Described fully differential inverter delay unit 1 at different levels comprises all respectively:

The first negative circuit be made up of the 4th NMOS tube MN4 and the 7th PMOS MP7, the grid of described 4th NMOS tube MN4 and described 7th PMOS MP7 links together as inverting input vn, and the drain electrode of described 4th NMOS tube MN4 and described 7th PMOS MP7 links together as reversed-phase output von.

The second negative circuit be made up of the 5th NMOS tube MN5 and the 8th PMOS MP8, the grid of described 5th NMOS tube MN5 and described 7th PMOS MP7 links together as normal phase input end vp, and the drain electrode of described 5th NMOS tube MN5 and described 8th PMOS MP8 links together as positive output end vop.

The source electrode of described 7th PMOS MP7 and described 8th PMOS MP8 all connects described control voltage amplifying signal, and namely described 7th PMOS MP7 is connected with the drain electrode of described second PMOS MP2 with the source electrode of described 8th PMOS MP8; Source electrode all ground connection of described 4th NMOS tube MN4 and described 5th NMOS tube MN5.

6th NMOS tube MN6 and the 7th NMOS tube MN7, the source ground of described 6th NMOS tube MN6 and described 7th NMOS tube MN7, the drain electrode of described 6th NMOS tube MN6, the grid of described 7th NMOS tube MN7 are all connected with described reversed-phase output von, and the drain electrode of described 7th NMOS tube MN7, the grid of described 6th NMOS tube MN6 are all connected with described positive output end vop.

The source electrode of the 8th NMOS tube MN8, described 8th NMOS tube MN8 connects the source electrode of described 4th NMOS tube MN4, and the grid of described 8th NMOS tube MN8, drain electrode and source electrode link together.The source electrode of the 9th NMOS tube MN9, described 9th NMOS tube MN9 connects the source electrode of described 5th NMOS tube MN5, and the grid of described 9th NMOS tube MN9, drain electrode and source electrode link together.The source electrode of the 9th PMOS MP9, described 9th PMOS MP9 connects the source electrode of described 7th PMOS MP7 and described 8th PMOS MP8, and the grid of described 9th PMOS MP9, drain electrode and source electrode link together.Described 8th NMOS tube MN8, described 9th NMOS tube MN9 and described 9th PMOS MP9 provide shunt capacitance for fully differential inverter delay unit 1 at different levels, thus can suppress VDD-to-VSS noise.

Also comprise reset function parts in the embodiment of the present invention, control the reset of realizing circuit by reset signal Reset.As shown in Figure 3, the drain electrode of the tenth NMOS tube MN10 connects described control voltage Vcontr, source ground, grid meet reset signal Reset.The drain electrode of the 11 NMOS tube MN11 connects described control voltage amplifying signal, source ground, grid meet reset signal Reset.The drain electrode of the tenth PMOS MP10 connects the source electrode of described 6th PMOS MP6, the tenth PMOS MP10 source electrode connects supply voltage, grid meets reset signal Reset.As shown in Figure 4, the drain electrode of the 12 NMOS tube MN12 connects described positive phase input signal vn, source ground, grid meet reset signal Reset.The drain electrode of the 13 NMOS tube MN13 connects described rp input signal vp, source ground, grid meet reset signal Reset.

In the embodiment of the present invention, described control voltage Vcontr is inputted by the grid of the first NMOS tube M1, photovoltaic conversion is become current-mode, in order to improve the linearity of voltage controlled oscillator, add the first resistance R1 at the source electrode of the first NMOS tube M1, form the structure of source negative feedback like this, along with the increase of described control voltage Vcontr, first NMOS tube M1 electric current is also in increase, and the pressure drop equally on the first resistance R1 also can increase.That is, a part of input voltage and described control voltage Vcontr to appear on the first resistance R1 instead of as the driving voltage of the first NMOS tube M1, therefore causes the ER effect of the first NMOS tube M1 to obtain smoothly.First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3 and the 4th PMOS composition common-source common-gate current mirror structure, the grid of the 3rd PMOS MP3 and the 4th PMOS are terminated to the drain terminal of the first NMOS tube M1, a road is provided to be biased in addition the second PMOS MP2, the 3rd PMOS MP3, such one side improves the Power Supply Rejection Ratio ability of circuit, the excursion of control voltage Vctrl is made more extensively, to make the adjustable change frequency of VCO larger further on the other hand.As shown in Figure 5, be the variation relation figure of clock signal frequency with control voltage of the embodiment of the present invention; Can find out that it has the good linearity intuitively, when voltage range change 0.8V ~ 3V, frequency can be changed by 80MHz to 700MHz, and in be concerned about frequency range namely: during 1.5-2.5V, the yield value of voltage controlled oscillator is approximately 270MHz/V.Embodiment of the present invention voltage controlled oscillator can provide frequency to be the clock signal of 480MHz for described USB2.0 interface circuit.

Due to the requirement to subsequent conditioning circuit, six phase overfrequency samplings are adopted, so the present embodiment adopts three grades of fully differential delay unit structures to clock data recovery circuit.Because the 3rd PMOS MP3 and the 4th PMOS MP4 consumes certain voltage, so every grade of fully differential inverter delay unit 1 amplitude of oscillation obtains certain restriction, speed and noise suppressed is made to obtain good compromise; 8th NMOS tube MN8 described in fully differential inverter delay unit 1, described 9th NMOS tube MN9 and described 9th PMOS MP9 are bypass transfiguration, can suppress the noise on power supply and ground.7th PMOS MP7 and the 8th PMOS MP8 adopts positive feedback structure, can accelerate the upset of output, improves reversal rate.The output of every grade all connects an inverter, makes to export as the full amplitude of oscillation.As shown in Figure 6, be embodiment of the present invention circuit power consumption also Output simulation result; Can find out that output voltage swing is the full amplitude of oscillation, duty ratio is close to 50%.And the average current of integrated circuit only has 0.33mA, that is the power consumption of whole circuit only has less than 1mW.

As shown in Figure 7, be embodiment of the present invention current phase noise Simulation result, the phase noise approximately-99dB at 1MHz place can be found out, reach 119.6dB at the phase noise at 10MHz place, so embodiment of the present invention VCO has good phase noise reduction ability.

Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (8)

1. a voltage controlled oscillator, is characterized in that: voltage controlled oscillator comprises control voltage gain circuitry and annular oscillation circuit;

Control voltage gain circuitry comprises:

First NMOS tube, the grid of described first NMOS tube connects the control voltage of input, and the source electrode of described first NMOS tube is by the first grounding through resistance, and the drain electrode of described first NMOS tube connects common-source common-gate current mirror circuit;

Described common-source common-gate current mirror circuit comprises the first PMOS, second PMOS, 3rd PMOS and the 4th PMOS, the drain electrode of described first NMOS tube, the drain electrode of described first PMOS, the grid of described 3rd PMOS and described 4th PMOS links together, the grid of described first PMOS and described second PMOS all connects same bias voltage, the source electrode of described first PMOS is connected with the drain electrode of described 3rd PMOS, the source electrode of described second PMOS is connected with the drain electrode of described 4th PMOS, the source electrode of described 3rd PMOS and described 4th PMOS all connects supply voltage, the drain electrode of described second PMOS exports control voltage amplifying signal,

Described control voltage amplifying signal is input to the control end of described annular oscillation circuit and the output frequency for controlling described annular oscillation circuit.

2. voltage controlled oscillator as claimed in claim 1, it is characterized in that: described bias voltage is provided by the first biasing circuit, described first biasing circuit comprises: the second NMOS tube, 3rd NMOS tube, 5th PMOS and the 6th PMOS, the source ground of described second NMOS tube, the source electrode of described 3rd NMOS tube connects the drain and gate of described second NMOS tube, the grid of the grid of described 5th PMOS and drain electrode and described 7th PMOS and drain electrode link together and as the output of described bias voltage, the source electrode of described 5th PMOS connects the drain and gate of described 6th PMOS, the source electrode of described 6th PMOS connects supply voltage.

3. voltage controlled oscillator as claimed in claim 1, is characterized in that: described annular oscillation circuit is joined end to end by three grades of fully differential inverter delay units and formed;

Described fully differential inverter delay unit at different levels comprises normal phase input end, inverting input, positive output end, reversed-phase output and control end, the normal phase input end of described fully differential inverter delay unit at different levels connects the positive output end of fully differential inverter delay unit described in upper level, the inverting input of described fully differential inverter delay unit at different levels connects the reversed-phase output of fully differential inverter delay unit described in upper level, the positive output end of described fully differential inverter delay unit at different levels is connected to the positive output end of fully differential inverter delay unit described in next stage, the reversed-phase output of described fully differential inverter delay unit at different levels is connected to the reversed-phase output of fully differential inverter delay unit described in next stage,

The control end of described fully differential inverter delay unit at different levels all connects described control voltage amplifying signal.

4. voltage controlled oscillator as claimed in claim 3, it is characterized in that: described annular oscillation circuit also comprises six inverters, positive output end and the reversed-phase output of described fully differential inverter delay unit at different levels export a clock signal respectively by an inverter.

5. the voltage controlled oscillator as described in claim 3 or 4, is characterized in that: described fully differential inverter delay unit at different levels comprises all respectively:

The first negative circuit be made up of the 4th NMOS tube and the 7th PMOS, the grid of described 4th NMOS tube and described 7th PMOS links together as inverting input, and the drain electrode of described 4th NMOS tube and described 7th PMOS links together as reversed-phase output;

The second negative circuit be made up of the 5th NMOS tube and the 8th PMOS, the grid of described 5th NMOS tube and described 7th PMOS links together as normal phase input end, and the drain electrode of described 5th NMOS tube and described 8th PMOS links together as positive output end;

The source electrode of described 7th PMOS and described 8th PMOS all connects described control voltage amplifying signal, source electrode all ground connection of described 4th NMOS tube and described 5th NMOS tube;

6th NMOS tube and the 7th NMOS tube, the source ground of described 6th NMOS tube and described 7th NMOS tube, the drain electrode of described 6th NMOS tube, the grid of described 7th NMOS tube are all connected with described reversed-phase output, and the drain electrode of described 7th NMOS tube, the grid of described 6th NMOS tube are all connected with described positive output end.

6. voltage controlled oscillator as claimed in claim 5, is characterized in that: described fully differential inverter delay unit at different levels also comprises respectively:

8th NMOS tube, the source electrode of described 8th NMOS tube connects the source electrode of described 4th NMOS tube, and the grid of described 8th NMOS tube, drain electrode and source electrode link together;

9th NMOS tube, the source electrode of described 9th NMOS tube connects the source electrode of described 5th NMOS tube, and the grid of described 9th NMOS tube, drain electrode and source electrode link together;

9th PMOS, the source electrode of described 9th PMOS connects the source electrode of described 7th PMOS and described 8th PMOS, and the grid of described 9th PMOS, drain electrode and source electrode link together.

7. voltage controlled oscillator as claimed in claim 1, is characterized in that: the clock signal of the output of described voltage controlled oscillator to be input in USB2.0 interface circuit and to provide clock signal for described USB2.0 interface circuit.

8. voltage controlled oscillator as claimed in claim 7, is characterized in that: described voltage controlled oscillator provides the frequency of clock signal to be 480MHz for described USB2.0 interface circuit.