CN104133705B - A kind of serial ports loads the system and method for PowerPC System guides files - Google Patents
A kind of serial ports loads the system and method for PowerPC System guides files Download PDFInfo
- Publication number
- CN104133705B CN104133705B CN201410374815.6A CN201410374815A CN104133705B CN 104133705 B CN104133705 B CN 104133705B CN 201410374815 A CN201410374815 A CN 201410374815A CN 104133705 B CN104133705 B CN 104133705B
- Authority
- CN
- China
- Prior art keywords
- data
- norflash
- read
- serial ports
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Stored Programmes (AREA)
Abstract
The present invention discloses the system and method that a kind of serial ports loading PowerPC guides file, including the design for the loading software for realizing the board design of loading scheme, CPLD logic realization and PC ends, after the requirement of these three modules is completed, file is sent to by serial ports by CPLD by the loading software at PC ends, file is programmed into the loading for the guiding file that system is completed in Norflash by the logic in CPLD.The present invention realizes a kind of succinct system loads method, by realizing the logic of Norflash programmings on CPLD rather than realizing programmed algorithm on the software of PC ends, so that the speed of programming is guaranteed, the program make it that the exploitation of PC ends software is also comparatively simple simultaneously, it is only necessary to reads the file for needing to load and then is transmitted according to the frame format packing data frame defined by serial ports.In addition, the present invention instead of special emulator and programmed environment, the loading flow of System guides file is simplified, the debugging efficiency of early stage is improved.
Description
Technical field
The present invention relates to PowerPC（The enhanced reduced instruction set computer central processing unit of performance optimization) guiding file loading side
Method, more particularly to a kind of serial ports loads the system and method for PowerPC System guides files.
Background technology
PowerPC is often the main CPU as system（Central processing unit）Use, system start first stage be
Into the guiding of cpu system, the startup bin of conventional PowerPC systems（Binary system）The loading of file is provided by manufacturer
Dedicated emulated device, it is not only expensive using downloader, and need that corresponding debugging software is installed on PC, complete debugging
Also need to that the relevant parameter of debugging enironment is configured and adjusted according to the design of hardware after software installation, and due to
Emulator is not allow hot plug operations, therefore higher to environmental requirement.
That typically used due to interface mode is all JTAG（Joint test working group）Interface, it is therefore desirable to set in circuit board
The circuit design of JTAG parts is specially done in timing.For the machine system of vanning, such interface mode is substantially to be inconvenient to make
, due to needing special emulator, as long as therefore System guides damage be accomplished by taking apart cabinet veneer is split out plug it is imitative
True device guides reloading for code, and this operating process is not only bothered but also inefficiency.
The content of the invention
The problem of existing for background technology, what the present invention provided a kind of serial ports loading PowerPC System guides files is
System and method.The realization of the present invention includes circuit design, the CPLD of the loading scheme（CPLD）Logic
Realize and PC（Personal computer）The loading Software for Design at end.
Present invention aims at guiding file quickly loading and the upgrading for realizing PowerPC systems, saving is largely manually taken
Build ambient time.
It is characteristic of the invention that carrying out CPU guiding file loadings using general serial line interface, due to general front panel all
CPU debugging serial ports is had, therefore is multiplexed the interface, completing CPU guiding files using the interface before system starts adds
Carry, the interface is used as CPU debugging serial ports after system start-up.
Extra debugging enironment need not be built using the mode of serial line interface, it is only necessary to plugged Serial Port Line connection PC and be
The CPU debugging serial ports of system.The loading that file completes system is guided by the related CPU of the upper computer software loading at PC ends,
It is simple to operate, and the damage of any time System guides, it is only necessary to the software for re-using PC ends is loaded once, greatly
Improve efficiency greatly.
Solving the technical scheme that the technical problem used is：
The system that a kind of serial ports loads PowerPC System guides files, including the computer equipped with processing software and
Integrated central processing unit PowerPC, complex programmable logic device (CPLD), non-volatile flash memory on circuit boards
Norflash, electrical level transferring chip, panel interface；PowerPC local bus is connected on CPLD, and Norflash passes through local
Bus is connected on CPLD；The serial ports of computer is connected by Serial Port Line with panel interface, the serial ports letter accessed from panel interface
Number it is connected to after electrical level transferring chip is changed on CPLD, CPLD is connected with PowerPC by serial ports.
A kind of method that serial ports based on said system loads PowerPC System guides files, comprises the following steps,
Step 1：System electrification；
Step 2：Download and the read-write of serial ports and Norflash erasing and read-write behaviour are realized in CPLD programs, CPLD programs
Make logic；
Step 3：Open the processing software Sflash at PC ends；
Step 4：Sflash is operated, serial ports is selected, serial ports parameter is configured；
Step 5：Norflash or programming Norflash is read in selection；If reading Norflash, the base read is selected
Address and read length, click on and read flash, at this moment can pop-up dialogue box selection storing path and import file name, it is determined that after
Start reading process；If programming Norflash, the file to be downloaded is selected, starts to compile while inputting base address and then clicking on
Journey；During reading and programming Norflash, indicate to carry out Norflash on circuit boards by LED flicker
Read either programming operation；
Step 6：File reads either programming and completed, and the system that resets completes system and started.
The process that the processing software Sflash is programmed Norflash comprises the following steps,
Step 1：Configure " serial ports parameter ", click on " opening serial ports " button；The step realizes the configuration of PC ends serial ports；
Step 2：" browsing file " button is clicked on, the binary file of programming is selected；The step realizes the choosing of programming file
Select；
Step 3：Programming Norflash initial address is inputted at " address " place, " size " place input frame content can be according to institute
The file of selection is filled automatically, is clicked on " starting programming "；The step realizes that programming operation starts；
Step 4：Sflash softwares receive the content read after " starting programming " instruction in selected programming file and carried out
Data frame format as defined in being packaged into simultaneously is sent data by serial ports；
Step 5：CPLD carries out unpacking analysis after the data frame that PC serial ports is sended over by receiving to data frame, carries
Take the command information and data message in data frame；
Step 6：The data frame that CPLD is extracted according to step 5 starts the write operation to Norflash；
Step 7：Repeat step 4 is to step 6 until data are all sent, and Sflash interface displays program progress,
Pop-up dialogue box prompting completes programming flash after the completion of data write toward Norflash.
The process that the processing software Sflash is read out Norflash comprises the following steps,
Step 1：Configure " serial ports parameter ", click on " opening serial ports " button；The step realizes the configuration of PC ends serial ports；
Step 2：The initial address for reading Norflash is inputted at " address " place, " size " place file to be read of input is big
It is small；Click on and " check flash " buttons, file save location choice box is read in ejection, define filename and choose storing path；Should
Step realizes Data Position and the determination of size and the storing path determination for the Norflash to be read；
Step 3：Ejection determines dialog box after step 2 is completed, click on " it is determined that ", realize that read operation starts；
Step 4：Sflash softwares can send the data frame of reading instruction after receiving read operation instruction by serial ports；
Step 5：CPLD carries out unpacking analysis after the data frame that PC serial ports is sended over by receiving to data frame, carries
Take the command information and data message in data frame；
Step 6：The data frame that CPLD is extracted according to step 5 starts the read operation to Norflash；
Step 7：The data read are sent to Sflash by serial ports；
Step 8：The data that Sflash receives serial ports are write in the text preserved；
Step 9：To step 8, until data, all reading finishes and writes text repeat step 6.
The CPLD programs realize the read-write of serial ports and Norflash erasing and read-write, and detailed process includes,
By logic realization serial data transmission-receiving function module in CPLD, after serial ports receives data, according to the number of definition
It is read operation, write operation or erasing operation to parse the frame data according to frame format；
If read operation, then following steps are performed：
Step 1：Parse the initial address that Norflash is read in data frame and read size；
Step 2：Initial address is write to Norflash address bus, it is 0 that data amount check has been read in setting；
Step 3：The logic of Norflash read operations is performed, data are read；
Step 4：The data read are cached；
Step 5：The data of caching are filled into the transmission buffering area of serial ports；
Step 6：Start serial ports and send data；
Step 7：Address plus 1, data amount check has been read and plus 1, judges to have read whether data amount check is equal to the reading parsed
Data amount check, if not then represent not run through also, it is necessary to repeat step 3 arrive step 6；If it is represent that digital independent is complete
Into；
If write operation, then following steps are performed：
Step 1：Parse initial address in data frame, write-in data amount check and data；
Step 2：Initial address is write to Norflash address bus, first data is write to Norflash data
Bus, it is 0 that data amount check has been write in setting；
Step 3：Norflash write operation logics are performed, data are write；
Step 4：Plus 1 by address writes Norflash address bus, while next data are write into data/address bus, will
Written data number adds 1；
Step 5：Judge whether written data number is equal to the write-in data amount check parsed, if not then expression also
Do not write, it is necessary to which repeat step 3 arrives step 4, if it is expression has been written into completion；
If erasing operation, then following steps are performed：
Step 1：Parsing erasing initial address and the sector number to be wiped；
Step 2：Initial address is write to Norflash address bus；
Step 3：Norflash sector erasing operation logic is performed, sector is wiped；
Step 4：The address of erasing is added to the size of single sector, the starting point of the next sector to be wiped is obtained
Location；
Step 5：According to the sector number being resolved to, whether what judgement was wiped at present is last sector, if not
Then represent to also have sector not to be wiped free of, it is necessary to which repeat step 3 if it is represents that all sectors have been wiped free of to step 4
Into.
The present invention compared with the existing technology has the advantage that, feature or good effect：
The present invention realizes a kind of succinct system loads method, by realized on CPLD Norflash programming logic and
It is not to realize programmed algorithm on the software of PC ends so that the speed of programming is guaranteed, while the program causes PC ends software
Exploitation it is also comparatively simple, it is only necessary to read need load file then passed through according to the frame format packing data frame defined
Serial ports is transmitted.In addition, the present invention instead of special emulator and programmed environment, System guides file is simplified
Flow is loaded, the debugging efficiency of early stage is improved.
The present invention will guide file to be loaded into startup Norflash by simple serial line interface（Non-volatile flash memory）In,
As long as PowerPC hardware system is errorless, it can start after loading is completed, this greatly simplifies System startup files loading
Process, accelerates the debugging progress of system.
Brief description of the drawings
Fig. 1 is the structured flowchart of present system.
The method flow that Fig. 2 is programming Norflash in the present invention.
Fig. 3 reads the method flow of Norflash data for the present invention.
Fig. 4 is that CPLD programs of the present invention realize the read-write of serial ports and Norflash erasing and read-write flow.
Fig. 5 is PC ends software Sflash of the present invention（PC ends dbase）Interface sectional drawing.
Embodiment
Idea of the invention is that the guiding file load mode for simplifying existing PowerPC systems passes through there is provided one kind
The method that serial ports loads PowerPC System guides files, present invention aim to address rely on dedicated emulated device and debugging software
Limitation there is provided a kind of succinct system loads method.By the load mode, the startup of PowerPC System guides can be shortened
Debug time, realize and emulator download identical effect, greatly simplify System guides file loading process.
The system that a kind of serial ports loads PowerPC System guides files, including computer and collection equipped with processing software
Into central processing unit PowerPC on circuit boards, complex programmable logic device (CPLD), non-volatile flash memory Norflash,
Electrical level transferring chip, panel interface；PowerPC local bus is connected on CPLD, and Norflash is connected by local bus
Onto CPLD；The serial ports of computer is connected by Serial Port Line with panel interface, and the rs 232 serial interface signal accessed from panel interface passes through electricity
It is connected to after flat conversion chip conversion on CPLD, CPLD is connected with PowerPC by serial ports.
A kind of method that serial ports based on said system loads PowerPC System guides files, concrete operation step is：
Step 1：It is electric on circuit board；
Step 2：Download and the read-write of serial ports and Norflash erasing and read-write behaviour are realized in CPLD programs, CPLD programs
Make logic；
Step 3：PC and circuit board serial ports are connected by Serial Port Line；
Step 4：Open PC end software Sflash；
Step 5：Sflash is operated, serial ports is selected, serial ports parameter is configured；
Step 6：If to read Norflash, base address and the reading length read is selected, clicks on and " reads
Flash ", at this moment can pop-up dialogue box selection storing path and import file name, it is determined that after start reading process.If programmed
Norflash, please select the file to be downloaded, while inputting base address（File size can automatically be filled out according to the file size of selection
Fill）, then click on and start programming beginning programming process.During reading and programming Norflash, pass through on circuit boards
LED（Light emitting diode）Lamp flicker indicates to be read out Norflash either programming operation.
Step 7：File reads either programming and completed, and the system that resets completes system and started.
To achieve the above object, the loading of the invention that complete PowerPC System guides files needs to complete 3 modules,
Circuit design requirements including PowerPC systems, PowerPC guiding CPLD load-on module are realized, the reality of PC ends loading software
It is existing.
PowerPC can be guided by many introduces a collections, including Norflash, SD（Security Digital (SD)）Card, I2C
（The twin wire universal serial bus of PHILIPS Co.'s exploitation）、SPI（Serial Peripheral Interface (SPI)）Etc..The invention is drawn for Norflash
Lead and do scheme realization, therefore PowerPC systems need to select Norflash guiding source when configuring start-up mode.
The invention is realized, PowerPC localbus is should be noted on circuit design（Local bus）Bus is not
It can be connected directly on Norflash, it is necessary to arrive Norflash again after CPLD.In addition, PowerPC debugging serial ports can not
It is directly over being pulled out to panel interface after electrical level transferring chip, it is necessary to pull out again after CPLD.Circuit design such as Fig. 1.Fig. 1
Middle central processing unit refers to PowerPC, and CPLD refers to CPLD, and non-volatile flash memory refers to Norflash.Will
PowerPC local bus is connected on CPLD, and Norflash is connected on CPLD by local bus, from panel interface access
Rs 232 serial interface signal be connected to after electrical level transferring chip is changed on CPLD, the part is that the circuit realized in hardware circuit board connects
Connect.In addition, to realize the loading of guiding file, it is necessary to which the serial ports of hardware circuit board panel interface and personal computer is passed through into string
Mouth line is connected.
The invention is realized, needs the logic realized mainly to include in CPLD：Serial data transmitting-receiving, Norflash erasing
With read-write operation etc..Data write Norflash operating processes：The packed data frame in PC ends, PC is sent out data by serial ports end
CPLD is given, CPLD will complete Norflash write operation according to Norflash instruction format.Data are read from Norflash
Operating process：PC ends, which are sent, reads instruction, and CPLD completes Norflash read operation according to Norflash instruction format,
Data are sent to PC ends by CPLD by serial ports.Operating process such as Fig. 2 and Fig. 3.
The invention is realized, the loading software at PC ends needs the transmitting-receiving that the major function realized is serial data, specifically
Data frame format needs to coordinate CPLD logics, packed per frame data according to custom instruction format standard.PC ends software interface
Mainly include the functional modules such as serial ports configuration, Norflash are read, Norflash is programmed.PC ends software is realized such as Fig. 4, Fig. 5 institute
Show：
By logic realization serial data transmission-receiving function module in CPLD, after serial ports receives data, according to the number of definition
It is read operation, write operation or erasing operation to parse the frame data according to frame format；
If read operation, then following steps are performed：
Step 1：Parse the initial address that Norflash is read in data frame and read size；
Step 2：Initial address is write to Norflash address bus, it is 0 that data amount check has been read in setting；
Step 3：The logic of Norflash read operations is performed, data are read；
Step 4：The data read are cached；
Step 5：The data of caching are filled into the transmission buffering area of serial ports；
Step 6：Start serial ports and send data；
Step 7：Address plus 1, data amount check has been read and plus 1, judges to have read whether data amount check is equal to the reading parsed
Data amount check, if not then represent not run through also, it is necessary to repeat step 3 arrive step 6；If it is represent that digital independent is complete
Into；
If write operation, then following steps are performed：
Step 1：Parse initial address in data frame, write-in data amount check and data；
Step 2：Initial address is write to Norflash address bus, first data is write to Norflash data
Bus, it is 0 that data amount check has been write in setting；
Step 3：Norflash write operation logics are performed, data are write；
Step 4：Plus 1 by address writes Norflash address bus, while next data are write into data/address bus, will
Written data number adds 1；
Step 5：Judge whether written data number is equal to the write-in data amount check parsed, if not then expression also
Do not write, it is necessary to which repeat step 3 arrives step 4, if it is expression has been written into completion；
If erasing operation, then following steps are performed：
Step 1：Parsing erasing initial address and the sector number to be wiped；
Step 2：Initial address is write to Norflash address bus；
Step 3：Norflash sector erasing operation logic is performed, sector is wiped；
Step 4：The address of erasing is added to the size of single sector, the starting point of the next sector to be wiped is obtained
Location；
Step 5：According to the sector number being resolved to, whether what judgement was wiped at present is last sector, if not
Then represent to also have sector not to be wiped free of, it is necessary to which repeat step 3 if it is represents that all sectors have been wiped free of to step 4
Into.
The logic realization and PC ends software that the present invention is combined in CPLD are realized, are designed, led to by the data frame format of science
The correct loading that serial ports completes guiding file is crossed, the guiding file of PowerPC systems is in turn simplify on the premise of guaranteed rate
Load mode, process orderliness is clear, practical simple and convenient, efficiency high.
Claims (2)
1. the system that a kind of serial ports loads PowerPC System guides files, it is characterised in that：Including the calculating equipped with processing software
Machine and integrated central processing unit PowerPC, complex programmable logic device (CPLD), non-volatile flash memory on circuit boards
Norflash, electrical level transferring chip, panel interface；PowerPC local bus is connected on CPLD, and Norflash passes through local
Bus is connected on CPLD；The serial ports of computer is connected by Serial Port Line with panel interface, the serial ports letter accessed from panel interface
Number it is connected to after electrical level transferring chip is changed on CPLD, CPLD is connected with PowerPC by serial ports；
The method of specific loading PowerPC System guides files comprises the following steps,
Step 1：System electrification；
Step 2：Download in CPLD programs, CPLD programs and realize that the read-write of serial ports and Norflash erasing and read-write operation are patrolled
Volume；
Step 3：Open the processing software Sflash at PC ends；
Step 4：Sflash is operated, serial ports is selected, serial ports parameter is configured；
Step 5：Norflash or programming Norflash is read in selection；If reading Norflash, the base address read is selected
With read length, click on and read flash, at this moment can pop-up dialogue box selection storing path and import file name, it is determined that after start
Reading process；If programming Norflash, the file to be downloaded is selected, programming is started while inputting base address and then clicking on；
During reading and programming Norflash, indicate to be read out Norflash by LED flicker on circuit boards
Or programming operation；
Step 6：File reads either programming and completed, and the system that resets completes system and started；
The process that the processing software Sflash is programmed Norflash comprises the following steps,
Step 1：Configure " serial ports parameter ", click on " opening serial ports " button；The step realizes the configuration of PC ends serial ports；
Step 2：" browsing file " button is clicked on, the binary file of programming is selected；The step realizes the selection of programming file；
Step 3：Programming Norflash initial address is inputted at " address " place, " size " place input frame content can be according to selected
File be filled automatically, click on " start programming "；The step realizes that programming operation starts；
Step 4：Sflash softwares receive the content read after " starting programming " instruction in selected programming file and packed
Data are sent into defined data frame format and by serial ports；
Step 5：CPLD carries out unpacking analysis after the data frame that PC serial ports is sended over by receiving to data frame, extracts number
According to the command information and data message in frame；
Step 6：The data frame that CPLD is extracted according to step 5 starts the write operation to Norflash；
Step 7：Repeat step 4 is to step 6 until data are all sent, and Sflash interface displays program progress, data
Pop-up dialogue box prompting completes programming flash after the completion of toward Norflash write-ins；
The process that the processing software Sflash is read out Norflash comprises the following steps,
Step 1：Configure " serial ports parameter ", click on " opening serial ports " button；The step realizes the configuration of PC ends serial ports；
Step 2：The initial address for reading Norflash, the file size to be read of " size " place input are inputted at " address " place；Point
Hit and " check flash " buttons, file save location choice box is read in ejection, define filename and choose storing path；The step
Realize Data Position and the determination of size and the storing path determination for the Norflash to be read；
Step 3：Ejection determines dialog box after step 2 is completed, click on " it is determined that ", realize that read operation starts；
Step 4：Sflash softwares can send the data frame of reading instruction after receiving read operation instruction by serial ports；
Step 5：CPLD carries out unpacking analysis after the data frame that PC serial ports is sended over by receiving to data frame, extracts number
According to the command information and data message in frame；
Step 6：The data frame that CPLD is extracted according to step 5 starts the read operation to Norflash；
Step 7：The data read are sent to Sflash by serial ports；
Step 8：The data that Sflash receives serial ports are write in the text preserved；
Step 9：To step 8, until data, all reading finishes and writes text repeat step 6.
2. the system that a kind of serial ports according to claim 1 loads PowerPC System guides files, it is characterised in that：Institute
State CPLD programs and realize the read-write of serial ports and Norflash erasing and read-write, detailed process includes,
By logic realization serial data transmission-receiving function module in CPLD, after serial ports receives data, according to the data frame of definition
The format analysis frame data are read operation, write operation or erasing operation；
If read operation, then following steps are performed：
Step 1：Parse the initial address that Norflash is read in data frame and read size；
Step 2：Initial address is write to Norflash address bus, it is 0 that data amount check has been read in setting；
Step 3：The logic of Norflash read operations is performed, data are read；
Step 4：The data read are cached；
Step 5：The data of caching are filled into the transmission buffering area of serial ports；
Step 6：Start serial ports and send data；
Step 7：Address plus 1, data amount check has been read and plus 1, judges to have read whether data amount check is equal to the reading data parsed
Number, if not then represent not run through also, it is necessary to repeat step 3 arrive step 6；If it is represent that digital independent is completed；
If write operation, then following steps are performed：
Step 1：Parse initial address in data frame, write-in data amount check and data；
Step 2：Initial address is write to Norflash address bus, the data that first data is write into Norflash are total
Line, it is 0 that data amount check has been write in setting；
Step 3：Norflash write operation logics are performed, data are write；
Step 4：Plus 1 by address writes Norflash address bus, while next data are write into data/address bus, will write
Enter data amount check and plus 1；
Step 5：Judge whether written data number is equal to the write-in data amount check that parses, if not then representing not having also
Write, it is necessary to which repeat step 3 arrives step 4, if it is expression has been written into completion；
If erasing operation, then following steps are performed：
Step 1：Parsing erasing initial address and the sector number to be wiped；
Step 2：Initial address is write to Norflash address bus；
Step 3：Norflash sector erasing operation logic is performed, sector is wiped；
Step 4：The address of erasing is added to the size of single sector, the initial address of the next sector to be wiped is obtained；
Step 5：According to the sector number being resolved to, whether what judgement was wiped at present is last sector, if not then table
Show that also sector is not wiped free of, it is necessary to which repeat step 3 if it is represents that all sectors have been wiped free of completion to step 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410374815.6A CN104133705B (en) | 2014-07-31 | 2014-07-31 | A kind of serial ports loads the system and method for PowerPC System guides files |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410374815.6A CN104133705B (en) | 2014-07-31 | 2014-07-31 | A kind of serial ports loads the system and method for PowerPC System guides files |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104133705A CN104133705A (en) | 2014-11-05 |
| CN104133705B true CN104133705B (en) | 2017-10-03 |
Family
ID=51806391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410374815.6A Active CN104133705B (en) | 2014-07-31 | 2014-07-31 | A kind of serial ports loads the system and method for PowerPC System guides files |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104133705B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105045624A (en) * | 2015-07-17 | 2015-11-11 | 天津市英贝特航天科技有限公司 | PowerPC mainboard and program writing method |
| CN107193751B (en) * | 2017-05-19 | 2020-12-08 | 浪潮集团有限公司 | Method for storing file information of Nandflash array |
| CN107255975B (en) * | 2017-07-21 | 2020-03-27 | 中国电子科技集团公司第二十九研究所 | Device and method for realizing rapid loading of FPGA (field programmable Gate array) program by utilizing high-speed bus |
| CN107505932B (en) * | 2017-08-17 | 2020-05-01 | 中国科学院光电技术研究所 | DSP remote debugging device and method based on serial communication |
| CN107885523B (en) * | 2017-11-10 | 2021-08-31 | 航宇救生装备有限公司 | Rapid and stable serial port software upgrading method |
| CN109783454A (en) * | 2019-01-23 | 2019-05-21 | 成都易海通科技有限公司 | A kind of super large text file comparison method |
| CN111045734B (en) * | 2019-11-19 | 2023-09-01 | 中国航空工业集团公司西安航空计算技术研究所 | IMA platform-based software and hardware program one-key curing system and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201689685U (en) * | 2010-04-28 | 2010-12-29 | 长城信息产业股份有限公司 | Flash memory starting device |
| CN102736938A (en) * | 2012-06-18 | 2012-10-17 | 中国电子科技集团公司第十研究所 | Burning method of FPGA (Field Programmable Gate Array) configuration program |
| CN103136028A (en) * | 2013-03-11 | 2013-06-05 | 西北工业大学 | FLASH memorizer long-distance on-line upgrade method based on field programmable gate array (FPGA) |
| CN103389669A (en) * | 2013-07-26 | 2013-11-13 | 中国船舶重工集团公司第七一五研究所 | Remote dynamic loading system and method for processor program on basis of FPGA (Field Programmable Gate Array) or CPLD (complex programmable logic device) controller |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9348783B2 (en) * | 2012-04-19 | 2016-05-24 | Lockheed Martin Corporation | Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory |
-
2014
- 2014-07-31 CN CN201410374815.6A patent/CN104133705B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201689685U (en) * | 2010-04-28 | 2010-12-29 | 长城信息产业股份有限公司 | Flash memory starting device |
| CN102736938A (en) * | 2012-06-18 | 2012-10-17 | 中国电子科技集团公司第十研究所 | Burning method of FPGA (Field Programmable Gate Array) configuration program |
| CN103136028A (en) * | 2013-03-11 | 2013-06-05 | 西北工业大学 | FLASH memorizer long-distance on-line upgrade method based on field programmable gate array (FPGA) |
| CN103389669A (en) * | 2013-07-26 | 2013-11-13 | 中国船舶重工集团公司第七一五研究所 | Remote dynamic loading system and method for processor program on basis of FPGA (Field Programmable Gate Array) or CPLD (complex programmable logic device) controller |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的静态可重构***平台设计;梁宏;《中国优秀硕士学位论文全文数据库信息科技辑》;20140615(第06期);第25-45页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104133705A (en) | 2014-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104133705B (en) | A kind of serial ports loads the system and method for PowerPC System guides files | |
| CN100461105C (en) | Update and repair method of intellectualized equipment and system thereof | |
| CN110209419A (en) | A kind of CAN bus based DSP embedded device updating method and device | |
| CN104407878B (en) | C6000 digital signal processor online upgrading methods | |
| US20070220499A1 (en) | USB tool stick with multiple processors | |
| CN103544122B (en) | The cooperative system and its Synergistic method of a kind of interface adaptive matching | |
| CN108037938B (en) | Card opening method of eMMC | |
| CN109542478A (en) | A kind of system and method updating FPGA program in SPI Flash | |
| CN105760191A (en) | Embedded system equipment programming mass production method | |
| CN102917242A (en) | Testing system and testing method of multi-format video decoder | |
| CN110851163B (en) | Software updating method compatible with multi-equipment platform based on CAN communication | |
| CN111459744A (en) | Firmware burning method and firmware debugging method of video processing chip | |
| CN103677885A (en) | ARM FLASH simple program programming method | |
| CN110413298A (en) | The method that single-chip microcontroller serially upgrades and debugs is carried out based on Labwindows platform | |
| CN103678194A (en) | Device used for ISP (internet service provider) downloading of STM (scanning tunneling microscope) 32 program | |
| CN102750243A (en) | Easily-debugged embedded system of complex SD (secure digital) interface | |
| CN105653330A (en) | SD card based NorFlash programming system and method | |
| CN116541032B (en) | Data burning method, device, equipment and computer storage medium | |
| CN101950265B (en) | Method for CPU board card program downloading and hardware online detection and plug-in connector | |
| CN106776399A (en) | BIOS flash memory data read-write system and method based on baseboard management controller | |
| CN110366038B (en) | Method for multi-version software equipment to be compatible with multiple technical states | |
| CN109426511A (en) | Soft core update method and system | |
| CN103366812B (en) | The device of Flash online programming and implementation method on circuit board | |
| CN106066822B (en) | A kind of emulator and method for supporting coverage rate statistical function | |
| CN100359468C (en) | Single board software downloading method and apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 430074, No. 88, postal academy road, Hongshan District, Hubei, Wuhan Patentee after: Wuhan post and Telecommunications Science Research Institute Co., Ltd. Address before: 430074, No. 88, postal academy road, Hongshan District, Hubei, Wuhan Patentee before: Wuhan Inst. of Post & Telecom Science |