CN104064475A - 高迁移率功率金属氧化物半导体场效应晶体管 - Google Patents

高迁移率功率金属氧化物半导体场效应晶体管 Download PDF

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CN104064475A
CN104064475A CN201410340007.8A CN201410340007A CN104064475A CN 104064475 A CN104064475 A CN 104064475A CN 201410340007 A CN201410340007 A CN 201410340007A CN 104064475 A CN104064475 A CN 104064475A
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德瓦.帕塔纳亚克
K-I.陈
T-T.朝
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Abstract

本申请涉及沟槽MOSFET和形成沟槽MOSFET的方法。高迁移率的P-沟道功率金属氧化物半导体场效应晶体管。根据本发明的一种实施例,功率MOSFET被制作成使空穴在沿着(110)晶面或其等价面的反转/累积沟道中流动,当相对于源极施加负电压到栅极时,电流沿[110]方向或其等价方向。增强的空穴沟道迁移率导致导通电阻的沟道部分减小,因此,有利地减少了装置的全“导通”电阻。

Description

高迁移率功率金属氧化物半导体场效应晶体管
本申请是申请日为2006年12月22日、申请号为200680052188.8、发明名称为“高迁移率功率金属氧化物半导体场效应晶体管”的专利申请的分案申请。
技术领域
本发明的实施例涉及半导体的设计和制作。更具体地,本发明的实施例涉及高迁移率功率金属氧化物半导体场效应晶体管的***和方法。
背景技术
MOSFET(金属氧化物半导体场效应晶体管)装置的导通状态(或“导通”)电阻是重要的性能指数,尤其是对于功率装置。例如,当这样的装置导通或导电时,***功率的一部分由于装置里的电阻热而损耗。这将导致效率有害地降低。这种电阻热也会导致热损耗问题,进而可导致***过热和/或可靠度降低。因此,特别需要低导通电阻的装置。
MOSFET(金属氧化物半导体场效应晶体管)装置的导通电阻主要包括沟道电阻、漂移层(drift layer)电阻和衬底部件电阻。对于低压MOSFET,沟道电阻分量提供主要作用。沟道电阻与沟道中的载流子的迁移率成反比。在硅里,沟道中的载流子迁移率依赖于晶面和电流方向,对于不同类型的载流子,例如电子相对于空穴,这种依赖性不同。
MOSFET可以用晶体硅来制作。与晶格有关的几何结构通常根据密勒指数(Miller index)来描述,密勒指数依据晶体的晶轴,例如,a,b和c。当晶体是周期性的,存在等效方向和等效平面族。在这里,平面,例如从晶体锭切开的晶片的表面,用被圆括号括到里面的例如(abc)来描述。这种表示方法描述了(abc)平面和等效平面。相对于晶格的方向用被方括号括到里面的例如[abc]来描述。这种表示方法描述了[abc]方向和等效方向。
已知,在硅中电子的迁移率在(100)晶面达到最大,同时对电流的方向的依赖性小。相反,晶面的方向和电流的方向对空穴的迁移率都有很强的作用。空穴的迁移率在(110)晶面和[110]方向达到最大。
很久以前就知道,(110)晶面里的空穴的迁移率依赖于电流方向,在[110]方向达到最大(D.Colman等,Journal of Applied Physics(应用物理杂志),pp.1923-1931,1968)。他们的实验结果显示在图1的曲线图里(传统技术)。从图1的曲线图里,比起常规的(100)方向,很明显取决于栅极偏压,在(110)晶面里的空穴的迁移率增加到多于两倍。
Plummer等(1980IEDM,pp.104-106)也已经报道了制作在沟槽侧壁平行于(110)晶面的晶片上的沟槽功率MOSFET比沟槽壁平行于(110)平面但是其电流方向也在[100]方向的相应沟槽MOSFET在较高栅极电压展示了较高的空穴迁移率。
更近地,多名作者已经重申空穴迁移率在(110)平面里和[110]方向上是最高的(H.Irie等,IEDM,pp.225-228,2004和其参考文献)。沟槽侧向装置的专利已经被授予Wendell P.Noble等(2003年6月17日公布的美国专利号6,580,154)。
然而,传统的P-沟道沟槽MOSFET装置被制作成使得空穴在沿着(100)晶面的反转沟道中运动,且电流方向在[100]方向。
因此,存在对导通电阻降低的功率MOSFET装置的需求。另外地存在对用于空穴被限制在(110)平面以及在[110]方向运动的P-沟槽功率MOSFET的***和方法的需求。进一步存在对用于与半导体设计和制造的现有***和方法兼容互补的功率MOSFET的***和方法的需求。本发明的实施例提供了这些优点。
发明内容
公开了高迁移率P-沟道功率金属氧化物半导体场效应晶体管。根据本发明的实施例,功率MOSFET被制作成使空穴在反转/累积沟道中流动,该反转/累积沟道沿着(110)晶面,当相对于源极施加负电压到栅极时,电流沿[110]方向。增强的空穴沟道迁移率导致导通状态电阻的沟道部分减小,因此,有利地减少了装置的全“导通”电阻。
根据本发明的另一实施例,功率MOSFET结构包括栅极和源极。功率MOSFET还包括反转/累积沟道,其中空穴在所述反转/累积沟道中流动。沟槽沿(110)晶面对齐,当相对于源极施加负电压到所述栅极时电流沿[110]方向。
附图说明
结合于此形成本说明书的一部分的附图示出了本发明的实施例,并且与描述一起用来解释本发明的原理。除非另有说明,附图未按照比例绘制。
图1示出了基于晶面方向的空穴迁移率的实验测量结果。
图2示出了用于制作传统的P沟道沟槽功率MOSFET的传统晶片。
图3、4、5、6和7示出了在多种不同的沟槽旋转(trench rotation)的沟槽的结构。
图8A、8B、8C、8D示出了根据本发明实施例的带有各种平坦部(flat)的(110)晶片。
图9示出了根据本发明实施例的垂直于晶片平坦部的蚀刻沟槽。
图10示出了根据本发明实施例的平行和垂直于晶片平坦部的蚀刻沟槽。
图11示出了根据本发明实施例的沟槽MOSFET结构的示意图。
图12示出了根据本发明实施例的平面耗尽模MOSFET(DMOSFET)P-沟道结构的示意图。
图13示出了根据本发明实施例的高迁移率的P-沟道沟槽MOSFET装置的示意图。
具体实施方式
现在将详细参照本发明的各种实施例,在附带的图纸里示出了本发明的各种实施例的实例。尽管结合这些实施例描述本发明,应理解这不是为了将本发明局限于这些实施例。而是相反,本发明旨在覆盖由附属附带权利要求限定的包括在本发明的实质和范围内的可选、更改和等价形式。另外,在本发明下面详细的描述中,大量特殊细节被阐述以提供对本发明的全面理解。但是,本领域普通技术人员应理解,可以实践本发明而不需要这些特定细节。另一方面,众所周知的方法,程序,部件,流程(电路)没有详细描述,以免不必要地混淆本发明的各个方面。
图2示出了用于制作传统的P-沟道沟槽功率MOSFET的传统晶片200。晶片200被描述为带(001)平坦部的(001)晶片。晶片200也被描述为在<010>方向有平坦部。晶片200的顶面是(100)平面。应理解沟槽MOSFET中的电流方向,其中电流是从例如晶片200等的晶片的顶面到底面,将一直沿[100]方向,例如,如图2所示,进入图纸平面。
图3、4、5、6和7示出了在多种不同的沟槽旋转中沟槽的结构。图3示出了封闭单元沟槽结构300。竖直沟槽310和水平沟槽320沟槽都在(100)等价面上。
图4示出了旋转45°形成的封闭单元沟槽结构400。旋转的沟槽410和420都在(110)等价面上。
图5示出了条带单元沟槽结构500。竖直沟槽510在(100)等价面上。
图6示出了旋转45°形成的条带单元沟槽结构600。旋转的沟槽610在(110)等价面上。
图7示出了旋转-45°形成的条带单元沟槽结构700。旋转的沟槽710在(110)等价面上。
包括图5的条带单元沟槽结构500的芯片(die)和包括图6的旋转45°形成的芯片的沟槽结构600的实验实例已经被制作出来。初步分析显示例如当电流在(110)平面时,旋转45°形成的旋转沟槽结构600的全电阻比沟槽在(100)平面的传统技术装置低。
但是,应该理解,尽管电流可以和晶片200的(110)平面对准,但是沟槽电流在[100]方向,如前所述。
图8A、8B、8C和8D示出了根据发明实施例的带多种平坦部的(110)晶片。应理解其它的平坦部很好地适用于本发明实施例。图8A的晶片800被描述为带(110)平坦部的(110)晶片。示出了各种晶向,包括[001]、[111]和[110]。例如,如图8A所示,晶片800顶面是(110)平面。
图8B中晶片810被描述为带(111)平坦部的(110)晶片。示出了(111)晶向。例如,如图8B所示,晶片810顶面是(110)平面。图8C中晶片820被描述为带(001)平坦部的(110)晶片。示出了[001]和[110]晶向。例如,如图8C所示,晶片820顶面是(110)平面。
图8D中晶片830被描述为带(112)平坦部的(110)晶片。示出了[112]晶向。例如,如图8D所示,晶片830顶面是(110)平面。
根据本发明的实施例,在晶片800(图8A)里形成的沟槽MOSFET在(110)平面和[110]方向可有空穴电流。例如,从顶面到底面的电流可在[110]方向,例如,图纸平面向里,如图8A所示。
根据本发明的其它实施例,在晶片810(图8B)里形成的沟槽MOSFET可在(110)平面和[111]方向有空穴电流。
根据本发明的可选实施例,在晶片820(图8C)里形成的沟槽MOSFET可在(110)平面和[001]方向有空穴电流。
根据本发明的其它实施例,在晶片830(图8D)里形成的沟槽MOSFET可在(110)平面和[112]方向有空穴电流。
图9示出了根据本发明实施例的垂直于晶片800(图8A)的平坦部的蚀刻沟槽900。应该理解沟槽900在(110)或其等价面里。由于晶面是(110)平面,因此空穴电流方向也在[110]方向。应该理解本发明的实施例很好地适用于垂直于其它平坦部方向形成的沟槽,例如,如图8B,8C,和/或8D所示。
图10示出了根据本发明实施例的平行和垂直于晶片800(图8A)的平坦部的蚀刻沟槽1000。应理解沟槽1000在(110)或其等价面里。由于晶面是(110)平面,因此空穴电流方向也在[110]方向。应理解本发明的实施例很适合相对于其它平坦部方向形成的沟槽,例如,如图8B,8C,和/或8D所示。
图11示出了根据本发明实施例的沟槽MOSFET结构1100的示意图。沟槽MOSFET结构1100包括P+源极1110、N本体(body)1130和P+漏极1120。沟槽MOSFET结构1100可以形成在晶片800(图8A)中和晶片800上,用来提供对于电子和空穴运动电流均适合的方向。沟槽MOSFET结构1100的晶面方向在图11中已示出。应理解沟槽MOSFET结构1100的源极1110和漏极1120之间的电流在[110](或等价)方向。应理解本发明的实施例很适合垂直于其它平坦部方向形成的沟槽,例如,如图8B,8C,和/或8D所示。
图12示出了根据本发明实施例的平面耗尽模MOSFET(DMOSFET)P沟道结构1200示意图。平面耗尽模MOSFET P沟道结构1200包括P+源极1210、N本体1230和P+漏极1220。平面耗尽模MOSFET P沟道结构1200可形成在晶片800(图纸8)中或晶片800上,用来提供对于电子和空穴运动电流均适合的方向。平面耗尽模MOSFET P沟道结构1200的晶面方向在图12中已示出。应理解,平面耗尽模MOSFET P沟道结构1200的源极1210和漏极1220之间的电流在[110](或等价)方向。应理解本发明的实施例很适合垂直于其它平坦部方向的沟槽排列,例如,如图8B,8C,和/或8D所示。
应理解在不同的晶面里氧化物生长速度不同。例如,氧化物一般在[110]方向比在[100]方向增长的更快。在(110)平面的表面电荷是在(100)平面的大约2倍。当设计高迁移率MOSFET的临界电压时,需要考虑这些特性。
图13示出了根据本发明实施例的高迁移率P沟道累积沟槽MOSFET1300的示意图。沟槽MOSFET1300包括源极金属1310,绝缘体1320,P+源极区1330和N本体1340。沟槽MOSFET1300还包括多晶硅栅极1350,栅极氧化物1390和P-漂移区1360。沟槽MOSFET1300另外还包括衬底1370和漏极镀金属1380。
如图13所示,应理解沟槽MOSFET1300是沿[110]方向制作。根据本发明实施例,沟槽MOSFET1300可以垂直于(110)平坦部形成。应理解本发明的实施例很适合垂直于其它平坦部方向形成的沟槽,例如,如图8B,8C,和/或8D所示。
在电流传导中,沟槽MOSFET1300使沟道(N本体1340)反转并且在轻微掺杂(slightly doped)累积区(P-漂移区1360)累积电荷,在栅极1350附近形成P+累积层。因此,电流在N本体1340里的反转层和紧接栅极1350形成的累积层之中流动。
击穿电压在延伸到漂移区中的P N结处被承受。但是,不像传统的沟槽MOSFET,漂移电阻由两个平行部分组成:一个是累积区电阻,且另一个是漂移区电阻。累积区电阻部分小于流动区电阻部分。根据本发明实施例,由于电流在(110)平面和[110]方向流动,漂移区全电阻将比传统的累积型功率MOSFET装置的相应值大大减少。
在这个新颖的MOSFET设计中,通过将MOSFET的累积层平面制作为(110),将累积层方向制作为[110],累积层电阻将被大大减小,例如减小到大约1/2。
根据本发明的实施例提供了低导通电阻的功率MOSFET的***和方法。根据本发明的实施例也提供了P-沟道沟槽功率MOSFET的***和方法,其中空穴被限制在(110)平面并在[110]方向流动。另外,根据本发明的实施例提供了用于功率MOSFET的***和方法,该功率MOSFET与现有半导体设计和制造的***和方法兼容互补。
描述了本发明的各种实施例,高迁移率P-沟道功率金属氧化物半导体场效应晶体管。尽管本发明在特定实施例中描述,应理解本发明不应解释为限于这样的实施例,而是按照下面的权利要求解释。

Claims (7)

1.一种形成沟槽MOSFET的方法,包括:
得到具有沿选自包括[110]、[111]、[112]和[001]的组的方向的表面方向的硅晶片;
在所述晶片的(110)平面中蚀刻矩形沟槽;
邻近并平行于所述矩形沟槽的第一侧壁形成第一源极区;
邻近并平行于所述矩形沟槽的第二侧壁形成第二源极区,其中所述第一侧壁和所述第二侧壁在所述矩形沟槽的相对侧;并且
在所述第一和第二源极区之间形成栅极结构。
2.如权利要求1所述的方法,其中所述沟槽MOSFET被配置成用于反转沟道中的电流,当用与相对于其源极施加到所述MOSFET装置的栅极的负电压操作时,其位于(110)平面并且在[110]方向上。
3.一种沟槽MOSFET,包括:
硅晶片,包括沿选自包括[110]、[111]、[112]和[001]的组的方向的表面方向;
在所述晶片在(110)平面中形成的矩形沟槽;
邻近并平行于所述矩形沟槽的第一侧壁的第一源极区;
邻近并平行于所述矩形沟槽的第二侧壁的第二源极区,其中所述第一侧壁和所述第二侧壁在所述矩形沟槽的相对侧上;以及
在所述第一和第二源极区之间的栅极结构。
4.一种形成平面耗尽模MOSFET的方法,包括:
得到具有沿选自包括[110]、[111]、[112]和[001]的组的方向的表面方向的硅晶片;
在所述晶片的表面形成矩形平面栅极;
邻近并平行于所述矩形平面栅极的第一侧形成第一本体区;
邻近并平行于所述矩形平面栅极的第二侧形成第二本体区,其中所述第一侧和所述第二侧在所述矩形平面栅极的相对侧;
在所述第一本体区内形成第一源极区;
在所述第二本体区内形成第二源极区;并且
在所述晶片的所述表面相对的区域形成漏极区,
其中所述栅极、所述本体和所述源极区约束电流在所述源极区和所述漏极区之间在[110]方向中流动。
5.如权利要求4所述的方法,其中所述形成矩形平面栅极包括形成(110)平面限定的多个垂直平面栅极。
6.如权利要求5所述的方法,其中所述多个垂直栅极形成封闭单元。
7.如权利要求5所述的方法,其中所述多个垂直平面栅极形成条带单元。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7635637B2 (en) * 2005-07-25 2009-12-22 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
US8409954B2 (en) 2006-03-21 2013-04-02 Vishay-Silconix Ultra-low drain-source resistance power MOSFET
US20090292149A1 (en) * 2006-07-31 2009-11-26 Japan Gas Synthesize, Ltd. Catalyst for liquefied petroleum gas production and method for producing liquefied petroleum gas using the catalyst
US20090035911A1 (en) * 2007-07-30 2009-02-05 Willy Rachmady Method for forming a semiconductor device having abrupt ultra shallow epi-tip regions
US20090072277A1 (en) * 2007-09-17 2009-03-19 Dsm Solutions, Inc. System and Method for Enabling Higher Hole Mobility in a JFET
US8101500B2 (en) * 2007-09-27 2012-01-24 Fairchild Semiconductor Corporation Semiconductor device with (110)-oriented silicon
US8039877B2 (en) * 2008-09-09 2011-10-18 Fairchild Semiconductor Corporation (110)-oriented p-channel trench MOSFET having high-K gate dielectric
US10026835B2 (en) 2009-10-28 2018-07-17 Vishay-Siliconix Field boosted metal-oxide-semiconductor field effect transistor
CN102130005A (zh) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 沟槽侧壁为(110)面的沟槽pmos的制备方法
US8513798B2 (en) 2010-09-09 2013-08-20 Infineon Technologies Ag Power semiconductor chip package
US8461645B2 (en) 2011-03-16 2013-06-11 Infineon Technologies Austria Ag Power semiconductor device
US8816429B2 (en) 2011-07-07 2014-08-26 Fairchild Semiconductor Corporation Charge balance semiconductor devices with increased mobility structures
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
KR102098996B1 (ko) 2014-08-19 2020-04-08 비쉐이-실리코닉스 초접합 금속 산화물 반도체 전계 효과 트랜지스터

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495883B2 (en) * 2001-02-06 2002-12-17 Denso Corporation Trench gate type semiconductor device and method of manufacturing
CN1127148C (zh) * 1998-03-25 2003-11-05 日本电气株式会社 绝缘栅型半导体器件及其制造方法
JP2004146626A (ja) * 2002-10-25 2004-05-20 Toshiba Corp 半導体装置
JP2004356114A (ja) * 2003-05-26 2004-12-16 Tadahiro Omi Pチャネルパワーmis電界効果トランジスタおよびスイッチング回路

Family Cites Families (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US615389A (en) * 1898-12-06 Wristlet
US671040A (en) * 1900-07-25 1901-04-02 John Thomas Wright Combined cultivator and planter.
US691961A (en) * 1900-10-31 1902-01-28 August G Nelson Alarm-bell.
US4131524A (en) * 1969-11-24 1978-12-26 U.S. Philips Corporation Manufacture of semiconductor devices
JPS58100441A (ja) 1981-12-10 1983-06-15 Toshiba Corp 半導体装置の製造方法
JPS58168258A (ja) 1982-03-30 1983-10-04 Nippon Telegr & Teleph Corp <Ntt> 半導体集積回路装置およびその製造方法
JPS58197839A (ja) 1982-05-14 1983-11-17 Toshiba Corp 半導体装置の製造方法
JPS5935445A (ja) 1982-08-24 1984-02-27 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
US4605919A (en) * 1982-10-04 1986-08-12 Becton, Dickinson And Company Piezoresistive transducer
JPS6122630A (ja) 1984-07-10 1986-01-31 Sony Corp 半導体装置の製造方法
US4835585A (en) 1984-11-26 1989-05-30 American Telephone And Telegraph Company, At&T Bell Laboratories Trench gate structures
JPS61256739A (ja) 1985-05-10 1986-11-14 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6292361A (ja) * 1985-10-17 1987-04-27 Toshiba Corp 相補型半導体装置
US4767722A (en) 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
JPS62298130A (ja) 1986-06-18 1987-12-25 Matsushita Electric Ind Co Ltd 素子分離方法
JPS63228710A (ja) * 1987-03-18 1988-09-22 Toshiba Corp 半導体装置
US4799990A (en) 1987-04-30 1989-01-24 Ibm Corporation Method of self-aligning a trench isolation structure to an implanted well region
JPH0810757B2 (ja) 1987-05-25 1996-01-31 松下電子工業株式会社 半導体装置の製造方法
JPS6476755A (en) 1987-09-18 1989-03-22 Hitachi Ltd Semiconductor device
US4758531A (en) 1987-10-23 1988-07-19 International Business Machines Corporation Method of making defect free silicon islands using SEG
JPH0235736A (ja) 1988-07-26 1990-02-06 Matsushita Electric Ind Co Ltd 半導体装置
EP0354449A3 (en) * 1988-08-08 1991-01-02 Seiko Epson Corporation Semiconductor single crystal substrate
JPH0258248A (ja) 1988-08-23 1990-02-27 Seiko Epson Corp 半導体装置の製造方法
US4939557A (en) * 1989-02-15 1990-07-03 Varian Associates, Inc. (110) GaAs microwave FET
JPH0344067A (ja) 1989-07-11 1991-02-25 Nec Corp 半導体基板の積層方法
US5182233A (en) * 1989-08-02 1993-01-26 Kabushiki Kaisha Toshiba Compound semiconductor pellet, and method for dicing compound semiconductor wafer
FR2668465B1 (fr) 1990-10-30 1993-04-16 Inst Francais Du Petrole Procede d'elimination de mercure ou d'arsenic dans un fluide en presence d'une masse de captation de mercure et/ou d'arsenic.
JP3131239B2 (ja) * 1991-04-25 2001-01-31 キヤノン株式会社 半導体回路装置用配線および半導体回路装置
US5087586A (en) 1991-07-03 1992-02-11 Micron Technology, Inc. Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer
US5366914A (en) * 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
JPH07176745A (ja) * 1993-12-17 1995-07-14 Semiconductor Energy Lab Co Ltd 半導体素子
US5814858A (en) 1996-03-15 1998-09-29 Siliconix Incorporated Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer
JPH09283440A (ja) 1996-04-12 1997-10-31 Toshiba Corp 選択エピタキシャル膜の形成方法
JP3545590B2 (ja) * 1997-03-14 2004-07-21 株式会社東芝 半導体装置
US6180966B1 (en) * 1997-03-25 2001-01-30 Hitachi, Ltd. Trench gate type semiconductor device with current sensing cell
JP3755228B2 (ja) * 1997-04-14 2006-03-15 株式会社ニコン 荷電粒子線露光装置
US6373100B1 (en) 1998-03-04 2002-04-16 Semiconductor Components Industries Llc Semiconductor device and method for fabricating the same
EP0996160A1 (en) 1998-10-12 2000-04-26 STMicroelectronics S.r.l. Contact structure for a semiconductor device
US7578923B2 (en) 1998-12-01 2009-08-25 Novellus Systems, Inc. Electropolishing system and process
US6413822B2 (en) 1999-04-22 2002-07-02 Advanced Analogic Technologies, Inc. Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer
GB9917099D0 (en) 1999-07-22 1999-09-22 Koninkl Philips Electronics Nv Cellular trench-gate field-effect transistors
US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6245615B1 (en) * 1999-08-31 2001-06-12 Micron Technology, Inc. Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
US6475864B1 (en) * 1999-10-21 2002-11-05 Fuji Electric Co., Ltd. Method of manufacturing a super-junction semiconductor device with an conductivity type layer
JP4528460B2 (ja) * 2000-06-30 2010-08-18 株式会社東芝 半導体素子
US6605843B1 (en) 2000-08-11 2003-08-12 Advanced Micro Devices, Inc. Fully depleted SOI device with tungsten damascene contacts and method of forming same
JP4764987B2 (ja) * 2000-09-05 2011-09-07 富士電機株式会社 超接合半導体素子
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
JP2002231945A (ja) 2001-02-06 2002-08-16 Denso Corp 半導体装置の製造方法
JP3534084B2 (ja) 2001-04-18 2004-06-07 株式会社デンソー 半導体装置およびその製造方法
EP1267415A3 (en) * 2001-06-11 2009-04-15 Kabushiki Kaisha Toshiba Power semiconductor device having resurf layer
US6436791B1 (en) 2001-06-14 2002-08-20 Taiwan Semiconductor Manufacturing Company Method of manufacturing a very deep STI (shallow trench isolation)
US6764906B2 (en) 2001-07-03 2004-07-20 Siliconix Incorporated Method for making trench mosfet having implanted drain-drift region
JP2003115587A (ja) * 2001-10-03 2003-04-18 Tadahiro Omi <110>方位のシリコン表面上に形成された半導体装置およびその製造方法
EP1302982A1 (de) 2001-10-12 2003-04-16 Infineon Technologies AG Verfahren zum Ausbilden einer vertikalen Feldeffekttransistoreinrichtung
US6753250B1 (en) 2002-06-12 2004-06-22 Novellus Systems, Inc. Method of fabricating low dielectric constant dielectric films
JP4055504B2 (ja) 2002-07-23 2008-03-05 トヨタ自動車株式会社 半導体装置
AU2003269926A1 (en) 2002-07-30 2004-02-16 The Regents Of The University Of California Superlattice nanopatterning of wires and complex patterns
JP4158453B2 (ja) * 2002-08-22 2008-10-01 株式会社デンソー 半導体装置及びその製造方法
KR100475025B1 (ko) 2002-10-25 2005-03-10 주식회사 하이닉스반도체 반도체소자의 소자분리절연막 형성방법
JP4695824B2 (ja) * 2003-03-07 2011-06-08 富士電機ホールディングス株式会社 半導体ウエハの製造方法
US6844238B2 (en) 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
WO2004095567A1 (de) 2003-04-17 2004-11-04 X-Fab Semiconductor Foundries Ag Kontrolle des dickenabtrags von einem scheibenverbund und teststruktur zur abtragskontrolle
US6987305B2 (en) 2003-08-04 2006-01-17 International Rectifier Corporation Integrated FET and schottky device
US7022578B2 (en) 2003-10-09 2006-04-04 Chartered Semiconductor Manufacturing Ltd. Heterojunction bipolar transistor using reverse emitter window
US6967112B2 (en) * 2003-12-23 2005-11-22 Sharp Laboratories Of America, Inc. Three-dimensional quantum dot structure for infrared photodetection
US7115920B2 (en) * 2004-04-12 2006-10-03 International Business Machines Corporation FinFET transistor and circuit
US7122412B2 (en) 2004-04-30 2006-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a necked FINFET device
EP1605498A1 (en) 2004-06-11 2005-12-14 S.O.I. Tec Silicon on Insulator Technologies S.A. A method of manufacturing a semiconductor wafer
US7329576B2 (en) 2004-09-02 2008-02-12 Micron Technology, Inc. Double-sided container capacitors using a sacrificial layer
JP2006120789A (ja) * 2004-10-20 2006-05-11 Toshiba Corp 半導体装置
US7371641B2 (en) 2004-10-29 2008-05-13 International Rectifier Corporation Method of making a trench MOSFET with deposited oxide
JP4841829B2 (ja) * 2004-11-17 2011-12-21 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US20060108635A1 (en) * 2004-11-23 2006-05-25 Alpha Omega Semiconductor Limited Trenched MOSFETS with part of the device formed on a (110) crystal plane
US20100032857A1 (en) 2005-02-28 2010-02-11 Saint-Gobain Ceramics & Plastics, Inc. Ceramic components, coated structures and methods for making same
US9685524B2 (en) 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
US7868394B2 (en) 2005-08-09 2011-01-11 United Microelectronics Corp. Metal-oxide-semiconductor transistor and method of manufacturing the same
US8409954B2 (en) 2006-03-21 2013-04-02 Vishay-Silconix Ultra-low drain-source resistance power MOSFET

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1127148C (zh) * 1998-03-25 2003-11-05 日本电气株式会社 绝缘栅型半导体器件及其制造方法
US6495883B2 (en) * 2001-02-06 2002-12-17 Denso Corporation Trench gate type semiconductor device and method of manufacturing
JP2004146626A (ja) * 2002-10-25 2004-05-20 Toshiba Corp 半導体装置
JP2004356114A (ja) * 2003-05-26 2004-12-16 Tadahiro Omi Pチャネルパワーmis電界効果トランジスタおよびスイッチング回路

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