CN104051397B - 包括非整数引线间距的封装器件及其制造方法 - Google Patents

包括非整数引线间距的封装器件及其制造方法 Download PDF

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CN104051397B
CN104051397B CN201410089178.8A CN201410089178A CN104051397B CN 104051397 B CN104051397 B CN 104051397B CN 201410089178 A CN201410089178 A CN 201410089178A CN 104051397 B CN104051397 B CN 104051397B
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chip
lead
encapsulation
spacing
carrier
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CN104051397A (zh
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J.赫格劳尔
M-A.库特沙克
李德森
G.洛曼
R.奥特伦巴
W.佩因霍普夫
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本发明涉及包括非整数引线间距的封装器件及其制造方法。公开了包括非整数引线间距的封装芯片、***和用于制造封装芯片的方法。在一个实施例中，一种封装器件包括第一芯片、包装第一芯片的封装以及从封装突出的多个引线，其中所述多个引线包括不同的非整数倍引线间距。

Description

包括非整数引线间距的封装器件及其制造方法
技术领域
本发明总体涉及半导体封装并且具体涉及封装引线的配置。
背景技术
封装和组装构成半导体器件制作的最后阶段。封装提供芯片和芯片载体之间的必要互连以及抵抗化学、机械或辐射引起的损坏的保护外壳。连续的技术改进处于进行中，以便满足对具有更小的尺寸、增强的性能、更多样的功能和改进的可靠性的器件的需求。
发明内容
根据实施例，一种封装器件包括第一芯片、包装第一芯片的封装以及从封装突出的多个引线，其中多个引线包括不同的非整数倍引线间距。
根据实施例，一种用于制造封装芯片的方法包括：把第一芯片安装到芯片载体组件上，其中芯片载体组件包括不同的非整数倍引线间距；把第一芯片连接到芯片载体组件的引线；用包装物包装第一芯片；以及把第一包装芯片分离成个体封装芯片。
根据实施例，***包括：第一芯片；包装第一芯片的封装；从封装突出的第一引线；从封装突出的第二引线，第一引线和第二引线以第一引线间距布置；从封装突出的第三引线，第二引线和第三引线以第二引线间距布置；以及从封装突出的第四引线，第三引线和第四引线以第三引线间距布置，其中第一引线间距是与第二引线间距和第三引线间距不同的非整数倍，并且其中第二引线间距是与第三引线间距不同的非整数倍。
附图说明
为了更全面理解本发明及其优点，现在参考结合附图做出的后面的描述，在附图中：
图1图示了通过透孔互连技术连接到部件载体的封装芯片的三维图；
图2图示了通过表面安装技术（SMD）连接到部件载体的封装芯片的三维图；
图3A图示了包括具有各种宽度和各种引线间距的引线的封装芯片的实施例的顶视图；
图3B图示了针对PC板导体的电压间隔要求；
图3C图示了包括具有各种宽度和各种引线间距的引线的封装芯片的另一实施例的顶视图；
图4图示了根据本发明的实施例的用于制造封装芯片的方法的流程图；以及
图5图示了根据本发明的实施例的芯片载体组件的部分的顶视图，该部分与单个多间距芯片封装相关。
具体实施方式
下面详细地讨论目前优选的实施例的制作和使用。然而，应当意识到的是，本发明提供了许多适用的发明构思，这些发明构思可以体现在广泛的各种具体上下文中。所讨论的具体实施例仅说明制作和使用本发明的具体方式，并不限制本发明的范围。
封装不仅可以提供芯片到芯片载体的机械附着，而且还可以提供芯片和引线、焊盘或管脚之间的电连接。封装芯片可以被分类成多个类别。例如，封装芯片可以是如图1中示出的透孔封装（THP）或如图2中示出的表面安装器件（SMD）。
图1的***100包括封装芯片110、设置在封装芯片110底侧上的散热器（散热块）120、以及把封装芯片110电连接到部件载体140的引线或管脚130。
封装芯片110可以包括设置在封装内的芯片载体，诸如引线框。引线框包括多个引线130。芯片设置在引线框的管芯附着物或管芯焊板（die paddle）上。
在一些实施例中，封装或包装物包括第一部分80A和第二部分80B。第一部分80A直接设置在芯片上方。第二部分80B可以被设置成横向邻近芯片。第二部分80B与多个引线130的方向相反，使得芯片设置在多个引线130和第二部分80B之间。第一部分80A比第二部分80B厚。开口150可以设置在包装物内。开口150被配置成实现散热器120的安装。例如，可以使用穿过开口150安装的螺钉（出于简单性原因，螺钉未示出）把散热器120附着到封装芯片110。
在各个实施例中，芯片可以是功率芯片，其例如汲取大电流（例如大于30安培）。例如，芯片可以被配置成操作在大约20V到大约1000V处。可替代地，芯片可以被配置成操作在大约20V到大约100V处。在其它实施例中，芯片可以被配置成操作在大约100V到大约500V处。在一个实施例中，芯片可以被配置成操作在大约5V到大约20V处。
在各个实施例中，芯片可以是功率半导体器件，在一个实施例中，该功率半导体器件可以是分立的器件。在一个实施例中，芯片是三端子器件，诸如功率金属绝缘体半导体场效应晶体管（MISFET）、结型场效应晶体管（JFET）、双极结型晶体管（BJT）、绝缘栅双极晶体管（IGBT）或晶闸管。可替代地，芯片包括集成电路（IC）。
在一个实施例中，芯片是n沟道MISFET。在另一实施例中，芯片是p沟道MISFET。在一个或多个实施例中，芯片可以包括多个器件，诸如垂直MISFET和二极管，或可替代地，由隔离区分离的两个MISFET器件。
图2的***200表示附着到部件载体240的SMD的示例。组件200包括封装芯片210，封装芯片210沿其主表面之一附着到部件载体240。机械附着到封装芯片210的一侧且与部件载体240直接机械接触的可以是散热器220。到封装芯片210的内部功能元件的电连接经由将封装***处的接触焊盘和部件载体处的接触焊盘相连接的一组引线230而实现。这些引线可以例如是J形或鸥翼形的。可替代地，表面安装技术（SMT）还可以通过在位于封装210的面对载体240的底侧处的球栅阵列上利用焊接接点而实行。
芯片可以是与关于图1描述的芯片相同的芯片，并且操作电流和电位可以与关于图1描述的相同。
由于表面安装技术关于组装密度的优点，表面安装技术已广泛代替透孔技术（THT），提供了显著的经济上的优点。另一方面，透孔技术仍然供应了出众的互连可靠性，并因此仍然对于特定（例如军事）应用来说是有利的。此外，基于THT的组件提供关于从器件内部到外部的散热的效率的附加优点。对于SMD，热传输必须经由散射器220所附着至的部件载体240发生。
本发明的各个实施例提供了针对封装芯片的柔性引线设计。例如，每个引线可以出于其预期的目的而被优化，与标准印刷电路板配置无关。本发明的各个实施例提供了不由标准印刷电路板限定的引线配置。例如，引线可以基于电流密度、爬电距离（例如两个电位之间的隔离距离）、电容量和电感率而被优化。在各个实施例中，这导致引线具有不同的宽度、间距和/或长度。例如，引线可以具有不同的非整数倍引线间距（包括1的倍数）。
对于经由THT附着到载体的封装芯片，部件载体（例如PCB）表面处的两个引线之间的爬电距离可以是关键参数。间隙距离（例如，空气中邻近引线之间的距离）可以是较不关键的，这是因为空气提供了足够的绝缘，达大约每毫米距离1kV电压。来自环境的湿气和其它导电杂质可能随时间在部件载体的表面上累积并最终在邻近的引线之间创建不可接受地高的泄漏电流。如果施加更高的操作电压，则这个问题可能变得更重要。
本发明的各个实施例针对经受高电压和/或高电流操作的封装芯片提供了电性能中的改进。
图3A示出了封装芯片300的实施例。封装芯片300包括设置在封装（包装）310内的芯片载体上的芯片（或多个芯片）。封装芯片300包括从封装310平行突出的四个引线320、322、324、326。
在各个实施例中，封装芯片300可以包括如关于图1和2描述的芯片、电流和/或电压应用。芯片可以包括垂直结构，具有设置在芯片的第一主表面上的漏极电极以及设置在芯片的第二主表面上的源极和栅极电极。可替代地，漏极和栅极电极设置在芯片的第一主表面上，并且漏极电极设置在芯片的另一主要表面上。此外，封装芯片300可以包括控制芯片、传感器芯片、逻辑芯片或其它性质的芯片（例如MEMS器件）。在一些实施例中，（一个或多个）另外的芯片可以设置在功率芯片上。在其它实施例中，（一个或多个）另外的芯片可以被设置成邻近功率芯片的侧表面。在另外其它实施例中，功率芯片可以是规则分立芯片或集成电路。
被包围在封装芯片300中的半导体芯片可以由半导体材料或化合物半导体材料（诸如Si、SiGe、SiC或GaAs）制造。半导体芯片可以进一步包括无机和有机材料，诸如氧化硅、氮化硅、绝缘塑料或金属。封装或包装物310可以包括模制化合物（诸如热固性或热塑性材料）或层压件。
引线320-326可以是由诸如铜、铜合金、铝、铝合金或黄铜之类的材料构成的金属引线框的部分。可替代地，引线320-326可以包括导电材料，诸如焊接附着到封装310***处的接触焊盘的预制金属部分或导线。
在一些实施例中，封装芯片300可以包括引线，该引线包括不同的非整数引线间距（包括非整数倍引线间距）。第一间距P1（引线320和322的中心之间的距离）大于第二间距P2，并且第三间距P3大于第二间距P2，但是P1不等于P3。在具体示例中，第一间距P1是3.54mm，第二间距P2是1.94mm，并且第三间距P3是2.14mm。间距P1和间距P3是间距P2的非整数倍并且反之亦然。
在可替代实施例中，引线320-324（322-326）可以包括倍数整数间距，并且引线324-326（320-322）包括非整数倍间距。可替代地，引线320-322和324-326包括整数间距，并且引线322-324包括非整数倍间距。
封装芯片300的引线间距中的可变性可以在其被视为避免爬电电流问题所必需的情况下提供更宽的引线间距。对于低电压引线，可以将引线间距保持为显著地更小，以最小化对在封装芯片300被配置成安装到其上的部件载体的表面处消耗的占地面积的影响。
在各个实施例中，封装芯片300可以进一步包括具有各种引线（或非均匀）厚度的引线320-326。引线320和322包括第一宽度（第一直径）W1，并且引线324和326包括第二宽度（第二直径）W2。第一宽度W1可以大于第二宽度W2。例如，第一宽度W1可以在0.5mm和5mm之间或在0.5和1.5mm之间。可替代地，第一宽度W1可以是大约1mm。第二宽度W2可以在0.25mm和2.5mm之间或在0.25和0.75mm之间。可替代地，第二宽度W2可以是大约0.5mm。
引线320和322可以用于高电压/高电流应用，并且引线324和326可以用于低电压或逻辑应用。引线320和322可以电连接功率芯片的负载电极，并因此是经受高电压和/或高电流的功率芯片的负载路径的部分。引线324和326可以电连接到控制功率芯片的传感器芯片或逻辑芯片。
高电流流动10A-100A可以要求横截面为大约1mm2或直径在0.5mm-1mm的范围内。0.2mm2-0.3mm2的引线横截面对于用于到逻辑芯片的信号传送或连接的、具有保持在1A-10A范围内的电流的导电路径来说可以是足够的。
在可替代实施例中，第一引线320的宽度不同于第二引线322的宽度，并且第三引线324的宽度不同于第四引线326的宽度。可替代地，每个引线的宽度不同于其它引线中的每一个的宽度。引线间距以及引线宽度中的可变性可以允许针对变化的电流流动和电压电位的优化。
在本发明的又一实施例中，封装芯片包括倍数引线间距以及恒定的引线到引线距离。这个组合可以仅在引线宽度非均匀的情况下是可能的。这个具体的引线设计提供了引线间距和宽度可变性以适应高功率/电流器件的需要。
在进一步实施例中，封装芯片300包括对于所有引线来说不同的引线间距和不同的引线到引线距离。
在另外其它实施例中，封装芯片300可以包括各种引线长度，以实现到部件载体（诸如印刷电路板（PCB））的不同层中的导电部分的适当连接。
图3B示出了针对功率转换器件的引线之间的隔离（例如爬电）距离（引线的边到边，诸如D2、D3和/或D4，非间距）的曲线图。y轴涉及引线之间的隔离距离，并且x轴涉及器件的电压峰值。例如，如能够从图3B看出的那样，针对100kV电压峰值的引线距离是1.1mm，并且针对200kV电压峰值的引线距离是1.6mm。
图3C示出了封装芯片350的另一实施例。封装芯片350包括设置在封装（或包装）360内的芯片载体上的芯片（或多个芯片）。封装芯片300包括从封装360平行突出的10个引线（5个在封装360的第一侧上，并且5个在封装360的第二侧上）370-379。引线具有处于第一侧上的不同的非整数倍间距、处于第二侧上的不同的非整数倍间距、以及处于两侧上的不同的非整数倍间距。P1是与P2不同的非整数倍，P1和P2是与P3不同的非整数倍，并且P1、P2、P3是与P4不同的非整数倍。在一些实施例中，封装芯片350对于除了一个引线间距外的所有引线可以具有相同的引线间距（或其整数倍）。该一个引线间距是非整数倍引线间距。
在可替代实施例中，非整数倍引线间距可以设置在封装芯片350的所有四个侧上。
图4示出了根据本发明实施例的用于制造封装芯片的方法的流程图400。封装芯片可以安装在部件载体（诸如PCB板）上。
在第一步骤410中，提供包括多个引线框单元的芯片载体组件，每个引线框单元对应于封装芯片。在高容量封装制造中，不是个体地处理器件，而是将多个芯片附着到芯片载体组件（例如引线框组件）。芯片载体组件经受进一步的处理步骤并最终被分离成个体封装芯片。
例如，引线框组件可以包括8或16个引线框单元。在图5中示出了示例性引线框单元500。根据本发明的先前描述的实施例的基于倍间距引线设计的引线框组件可以是通过对金属板进行打孔来制造的，该金属板包括如关于较早实施例描述的导电金属材料。
引线框单元500包括针对一个或多个芯片的附着而预留的“管芯焊板”区530（芯片附着区）。散热器520可以被设置成邻近管芯焊板530。散热器520可以包括处于散热器520中心的孔525以便容易地把外部散热器（未描绘）附着到完成的封装芯片。
引线框单元500进一步包括引线。可以用封装材料（诸如模制材料）包围引线部分550、552、554、561，而部分560、562、564、566可以不用封装材料包围并从封装芯片突出。封装或包装545在图5中被示作边界线。引线框部分550/560、552/562以及556/566可以分别连接到功率芯片（例如MOSFET功率芯片）的集电极/漏极、发射极/源极以及栅极电极，而部分554/564例如可以提供到设置在MOSFET功率芯片上的传感器或逻辑芯片的连接。
在制造中的这个阶段处，个体引线框单元（例如500）以及焊板530和每个引线框单元（例如500）的内部引线部分550-556和外部引线部分560-566仍然由辅助引线框部分（被称为系杆或挡板570、575）保持在一起。这些辅助元件在处理期间提供机械稳定性直到引线框单元最终分离为止。
在步骤420中，在引线框单元500的芯片焊板530上安装一个或多个芯片。通过采用焊接技术或通过采用导电或非导电的膏/箔，将（一个或多个）芯片附着到引线框结构。
可以通过使用诸如边沿屏蔽、喷射/喷洒或模版印刷之类的技术来执行选择性的焊接沉积。焊接接点的形成可以在200oC-400oC范围内（通常在焊接材料的熔点之上20oC-50oC）的温度处发生。所施加的焊接层可以具有100nm到1μm的厚度，但是较低或较高的厚度值也是可行的。可以采用扩散焊接或软焊接材料。扩散焊接材料（诸如AuSn、CuSn、AgSn、AuSi、AuIn、CuIn或AgIn）扩散到材料的配合端面中以被接合，并在界面处形成金属间的相。在软焊接过程完成之后，软焊接材料（通常为变化成分的SnPb合金）保持在接合界面处。
可以使用拾取和放置工具来拾取要安装的芯片，在它们的指派位置上方准确地对准它们并且然后把它们按压到预热的引线框单元500上，以便发起焊接接合的形成。例如，在减少气体大气（N2中少量百分比的H2）时，在360oC的温度和3.3N/mm2的接合力处，75%Au25%Sn焊接可以包括1200nm的焊接厚度。
在可替代实施例中，芯片到引线框的附着可以通过施加作为膏或箔而沉积的导电或非导电、有机或非有机粘附层而实现。有机粘附层可以包括与交联组分混合的环氧、丙烯酸盐、氰酸酯或聚酰亚胺化合物。导电粘附材料可以另外包括Au、Ag、Cu或者镀Ag或镀Au的Ni的纳米粒子（多达70体积%-85体积%）。通常在120oC-200oC之间的温度处频繁地与压强(1PSI-5PSI)的施加组合来执行采用粘附材料的附着过程。在附着过程完成之后，在烤炉中或通过热空气的流动使粘附层变干和固化。
当施加焊接材料或导电膏/箔时，生成芯片和引线框之间的机械以及电连接。例如，包括集电极/漏极电极的功率MOSFET芯片的第一主表面附着到引线框单元500的焊板530。焊板530连接到第一引线560。
在步骤430中，将引线框的引线连接到功率MOSFET芯片和/或逻辑芯片/传感器芯片。例如，设置在功率MOSFET芯片的上主表面上的源极电极连接到第二引线，并且，也设置在功率MOSFET芯片的上主表面上的栅极电极连接到逻辑芯片。逻辑芯片可以连接到第三引线和到第四引线。可替代地，源极电极连接到第二引线，并且栅极电极连接到另一引线。逻辑芯片继而连接到第四和第五引线。连接可以经由导线接合、球接合或夹接合而进行。导线或夹的材料可以是Au、Al、Ag或Cu。导线接合的厚度可以在16和500μm之间变化。
三种不同的技术可能可用于导线接合：超声、热压缩和热超声接合。在室温处，超声接合可以采用超声能量（20kHz到60kHz），其中接合时间大约为20ms。热压缩可以利用压强和热（具有300oC-500oC范围内的温度）的组合。热超声接合基于超声能量、热（具有125oC-150oC的温度）以及压强的组合效果。在热超声接合中施加的压强可以大约是比热压缩接合所需的量级低的量级。
在下一个步骤440中，用包装物（诸如模制化合物）包装芯片、接合（例如导线接合）和引线550、552、554、556的部分。模制化合物可以是热固性材料或热塑性材料。可以施加若干种模制技术，诸如传递和注入模制。对于传递模制，在压力下将热固性模制材料传递到模制室中以填充模具的腔。后固化步骤可以跟随。对于注入模制，通过若干个加热区来传输塑料粒。在最后的和最热的加热区，模制材料达到熔化状态。从那里，模制材料被注入到发生凝固的模制室中。不管所施加的模制方法如何，所产生的封装随后都经受去残胶（de-flash）步骤以便去除过量的树脂。采用研磨颗粒与高压空气或高压水浆组合的混合物来执行去残胶。
在步骤450中，通过沿预定切割线580（如图5中所指示）切割穿过系杆/挡板570/575和包装物，将所包装的芯片组件分离成个体芯片封装。
最后，在步骤460中，通过应用透孔技术或表面安装技术将包括多间距引线（例如非整数间距引线）的芯片封装之一与部件载体互连。部件载体可以是印刷电路板或预浸料层压件。可替代地，部件载体可以是包括电隔离材料（例如陶瓷、玻璃、聚合物）的主体的衬底，其包括导电迹线（例如铜或铝）。
通过把封装引线560、562、564、566***到部件载体的对应孔中来把芯片封装连接到部件载体。引线可以包括Sn、Sn合金或Au的薄涂层，以促进高质量焊接接点的形成。部件载体中的孔也可以用类似的材料和/或有机化合物加以涂覆以便改进焊接可润湿性。可替代地，芯片封装的引线设置在部件载体接触焊盘上。
引线被焊接到部件载体。可以利用泡沫流来喷射芯片封装和部件载体以清洗载体孔/部件载体接触焊盘和引线的表面。然后，组件经过焊料的湍流和层流。湍流促进焊料穿透到狭窄裂缝中。层流提供均匀的焊料分布并促进流除气。所施加的温度和停留时间依赖于组件的几何结构以及所使用的焊接材料。对于SnPb焊料，焊接温度通常在230oC-260oC的范围内。在焊接接点形成后，组件经过热空气刀以吹掉过量的焊料。在组件的冷却之前，可选的溶剂或水清洗步骤可以跟随。
虽然已详细描述了本发明及其优点，但是应当理解的是，在不脱离如所附权利要求限定的本发明的精神和范围的情况下，在本文中可以进行各种改变、替代和变更。
此外，本申请的范围不意图限制于说明书中描述的过程、机器、制造、物质组成、装置、方法和步骤的具体实施例。如本领域普通技术人员将从本发明的公开内容容易地意识到的那样，根据本发明，可以利用与本文中描述的对应实施例执行基本相同功能或达到基本相同结果的、目前存在的或后续开发的过程、机器、制造、物质组成、装置、方法或步骤。相应地，所附权利要求意图在其范围内包括这样的过程、机器、制造、物质组成、装置、方法或步骤。

Claims (19)

1.一种封装器件，包括：
第一芯片；
包装第一芯片的封装；以及
从所述封装突出的多个引线，其中所述多个引线中的相邻引线之间的引线间距对于所有引线而言是不同的，不同的引线间距不是彼此的整数倍。
2.根据权利要求1所述的封装器件，其中所述多个引线包括不同的引线宽度。
3.根据权利要求1所述的封装器件，其中所述多个引线包括不同的引线长度。
4.根据权利要求1所述的封装器件，其中所述多个引线包括不同的引线宽度和不同的引线长度。
5.根据权利要求1所述的封装器件，进一步包括芯片载体，其中芯片设置在所述芯片载体的第一侧上。
6.根据权利要求5所述的封装器件，进一步包括散热器，所述散热器设置在所述芯片载体的第二侧上。
7.根据权利要求1所述的封装器件，进一步包括第二芯片，所述第二芯片由所述封装包装。
8.一种制造封装芯片的方法，所述方法包括：
把第一芯片安装到芯片载体组件上，其中所述芯片载体组件包括多个引线，其中所述多个引线中的相邻引线之间的引线间距对于所有引线而言是不同的，不同的引线间距不是彼此的整数倍；
把第一芯片连接到所述芯片载体组件的引线；
用包装物包装第一芯片；以及
把第一包装芯片分离成个体封装芯片。
9.根据权利要求8所述的方法，其中所述多个引线包括具有不同引线宽度的引线。
10.根据权利要求8所述的方法，其中所述多个引线包括具有不同引线长度的引线。
11.根据权利要求8所述的方法，进一步把第二芯片安装到所述芯片载体组件上并且用所述包装物包装第二芯片。
12.根据权利要求11所述的方法，其中第二芯片安装在第一芯片上并电连接到第一芯片。
13.根据权利要求8所述的方法，进一步包括：在把包装的第一芯片分离成个体封装芯片之后，把封装芯片接合到部件载体。
14.根据权利要求13所述的方法，其中把封装芯片接合到部件载体包括把封装芯片透孔接合到部件载体。
15.一种半导体封装***，包括：
第一芯片；
包装第一芯片的封装；
从所述封装突出的第一引线；
从所述封装突出的第二引线，第一引线和第二引线以第一引线间距布置；
从所述封装突出的第三引线，第二引线和第三引线以第二引线间距布置；以及
从所述封装突出的第四引线，第三引线和第四引线以第三引线间距布置，其中第一引线间距是与第二引线间距和第三引线间距不同的非整数倍，并且其中第二引线间距是与第三引线间距不同的非整数倍。
16.根据权利要求15所述的半导体封装***，进一步包括第二芯片，其中所述封装包装第二芯片。
17.根据权利要求16所述的半导体封装***，其中第一芯片是功率芯片，其中第二芯片是逻辑芯片，其中第一芯片的第一电极连接到第一引线，其中第一芯片的第二电极连接到第二引线，其中第一芯片的第三电极连接到第二芯片的第一端子，其中第二芯片的第二端子连接到第三引线，并且其中第二芯片的第二端子连接到第四引线。
18.根据权利要求17所述的半导体封装***，进一步包括芯片载体和散热器，第一芯片设置在所述芯片载体的第一侧上，并且所述散热器设置在所述芯片载体的第二侧上。
19.根据权利要求17所述的半导体封装***，进一步包括部件载体，其中第一到第四引线连接到所述部件载体。
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