CN104037228B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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Abstract
提供了半导体器件及其制造方法。所述半导体器件包括:设置在衬底内的沟槽,所述沟槽包括宽度比下沟槽部宽的上沟槽部;设置在沟槽中的栅极;设置在沟槽中的栅极上方的层间绝缘层图案;设置在衬底内并且与上沟槽部的侧壁接触的源极区;设置在衬底中的源极区下方的本体区;以及设置在本体区上方并且填充有导电材料的接触沟槽。
Description
技术领域
以下描述涉及半导体器件,并且涉及例如具有上宽度比下宽度宽的沟槽的半导体器件,以及所述半导体器件的制造方法。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)是半导体行业中公知的一种半导体器件。
一种MOSFET是垂直导电沟槽MOSFET。
图1是示出MOSFET的截面图的示意图。
参见图1,MOSFET10包括沟槽17。每个沟槽17均包括通过栅极绝缘层19与本体区15绝缘的多晶硅栅极21。
源极区23接触每个沟槽17的侧表面。栅极绝缘层19将栅极21与金属层30绝缘。半导体衬底11形成MOSFET10的漏极。
仍参见图1,附图标记A表示沟槽宽度,B表示接触开口,以及C表示沟槽与接触开口之间的间隙。当MOSFET10在导通状态下偏置时,电流在源极区23与半导体衬底11之间垂直流动。在导通状态下,MOSFET10的电流能力和漏极与源极之间的导通电阻Rdson成反比。因此,为了提高MOSFET10的电流能力,必须降低导通电阻Rdson。
降低MOSFET10的导通电阻的方法之一是增加沟槽17的密度,也就是说,需要增加每单位面积的沟槽数目。这可以通过减少单元间距(cell pitch)来实现。
然而,MOSFET的单元间距可以被减少的程度受限于MOSFET单元的某些特征以及用于制造MOSFET的过程。
在MOSFET中,源极区通常形成在与沟槽成水平方向的半导体衬底上,以降低导通电阻。这限制了每单位面积的MOSFET单元的密度。
为了降低MOSFET的导通电阻,期望增加每单位面积的沟槽数目。然而,需要在沟槽与半导体衬底的表面上的接触开口之间设置间隙的过程,以在与沟槽成水平方向的半导体衬底上形成源极区。因此,存在对沟槽间隙可以被减小的程度的限制,这进一步限制了MOSFET的导通电阻可以被降低的程度。
发明内容
在一个一般方面中,提供了一种半导体器件,包括:设置在衬底的外延层内的沟槽,所述沟槽具有宽度比下沟槽部宽的上沟槽部;设置在沟槽的内表面上的栅极绝缘层;设置在沟槽内的栅极;设置在包括栅极的沟槽内的在栅极绝缘层上的层间绝缘层图案;设置在衬底内并且与沟槽的上沟槽部的侧壁接触的源极区;设置在衬底的外延层内的本体区;填充有金属的接触沟槽,所述接触沟槽使得源极区和本体区彼此接触;以及形成在接触沟槽之下的杂质区,所述杂质区具有与本体区相同类型的杂质并且具有比本体区高的杂质浓度。
源极区的下表面可以形成为比接触沟槽的下表面低。
栅极的上表面可以与接触沟槽的下表面齐平或者高于接触沟槽的下表面。
从衬底的上表面到接触沟槽的下表面的深度可以为从衬底的上表面到下沟槽部的下表面的深度的一半。
栅极的上表面可以与接触沟槽的下表面齐平或者低于接触沟槽的下表面。
层间绝缘层图案可以包括BPSG(硼磷硅酸盐玻璃)膜、HLD(树脂性氯丁胶)氧化物或其组合。
在另一一般方面中,提供了一种半导体器件,包括:设置在衬底内的沟槽,所述沟槽包括宽度比下沟槽部宽的上沟槽部;设置在沟槽中的栅极;设置在沟槽中的栅极上方的层间绝缘层图案;设置在衬底内并且与上沟槽部的侧壁接触的源极区;设置在衬底中的源极区下方的本体区;以及设置在本体区上方并且填充有导电材料的接触沟槽。
半导体器件的一般方面还可以包括:形成在接触沟槽与本体区之间的杂质区,所述杂质区具有与本体区相同类型的杂质并且具有比本体区高的杂质浓度。
可以在栅极的上表面上方设置源极区的一部分。
在另一一般方面中,提供了一种用于制造半导体器件的方法,包括:在衬底上形成焊垫氧化物层图案和焊垫氮化物层图案;使用焊垫氮化物层图案作为蚀刻掩模来对衬底进行选择性蚀刻,以在衬底内形成上沟槽部;在包括上沟槽部的表面的焊垫氮化物层图案和焊垫氧化物层图案上形成氮化物层;对氮化物层的整个表面进行蚀刻,以在上沟槽部的侧壁和焊垫氮化物层图案与焊垫氧化物层图案的侧壁上形成氮化物层图案;使用焊垫氮化物层图案和氮化物层图案作为蚀刻掩模来对上沟槽部之下的衬底进行蚀刻,以形成下沟槽部;对位于上沟槽部的侧壁上的氮化物层图案、焊垫氮化物层图案和焊垫氧化物层图案进行蚀刻,以形成具有下沟槽部和上沟槽部的沟槽,所述上沟槽部的宽度比下沟槽部宽;在沟槽的表面上形成栅极绝缘层;在下沟槽部和上沟槽部内的栅极绝缘层上沉积多晶硅;在衬底的外延层内形成本体区;对多晶硅进行蚀刻,以在下沟槽部内形成栅极;在上沟槽部的侧表面上形成源极区;在上沟槽部内的栅极绝缘层上形成层间绝缘层图案;形成接触沟槽,以使得源极区和本体区能够彼此接触;在接触沟槽之下形成杂质区,所述杂质区具有与本体区相同类型的杂质并且具有比本体区高的杂质浓度;以及使用金属层来填充接触沟槽。
可以使用自对准接触蚀刻法来形成接触沟槽。
层间绝缘层图案可以包括BPSG膜、HLD氧化物或其组合。
可以通过对多晶硅进行回蚀刻来形成栅极。
所述方法的一般方面还可以包括:在形成所述氮化物层之前在上沟槽部的表面上形成氧化物层之后,对所述氮化物层和所述氧化物层的整个表面进行蚀刻,以在上沟槽部的侧壁和焊垫氧化物层图案与焊垫氮化物层图案的侧壁上形成氧化物层图案和氮化物层图案。
可以使用自对准接触蚀刻法来形成接触沟槽。
层间绝缘层图案可以包括BPSG膜、HLD氧化物或其组合。
可以通过对多晶硅进行回蚀刻来形成栅极。
在另一一般方面中,提供了一种用于制造包括具有上沟槽部和下沟槽部的沟槽的半导体器件的方法,所述方法包括:通过使用硬掩模材料层来在衬底中形成第一沟槽;沿第一沟槽的露出表面形成氧化物层;沿硬掩模材料层的露出表面形成氮化物层;沿第一沟槽的底表面对氧化物层进行蚀刻以露出底表面,同时保留氧化物层的沿第一沟槽的侧表面的至少一部分;对第一沟槽的露出的底表面之下的衬底进行蚀刻,以形成沟槽的下沟槽部;以及沿第一沟槽的侧表面移除氧化物层,以形成沟槽的上沟槽部,所述上沟槽部的宽度比下沟槽部宽。
所述方法的一般方面还包括:沿上沟槽部的侧表面形成源极区;在下沟槽部内形成栅极;在上沟槽部内形成层间绝缘层图案;形成接触沟槽以接触源极区;在接触沟槽之下形成杂质区;以及使用导电材料填充接触沟槽。
其它特征和方面可以根据下面的详细描述、附图和权利要求而变得明显。
附图说明
图1为示出使用沟槽的MOSEFT的截面图的示意图。
图2为示出根据本公开内容的半导体器件的一个实例的截面视图的示意图。
图3A至图3K为半导体器件的一个实例在其制造期间的截面视图,用于依次示出用于制造这样的半导体器件的方法的一个实例的视图。
图4为响应于根据本公开内容的半导体器件的一个实例的单元间距的电阻值变化的曲线图。
在附图和详细描述中,除非另有说明,相同的附图标记将被理解为表示相同的元件、特征和结构。为了清楚、说明和方便起见,这些元件的相对尺寸和描绘可能被放大。
具体实施方式
提供下面的详细描述以帮助读者获得本文所述的方法、装置、和/或***的全面了解。因此,本领域技术人员会想到本文所述的***、装置和/或方法的各种改变、修改和等同方案。此外,为了更加清楚和简明起见,可以省略公知功能和结构的描述。
图2示出根据本公开内容的半导体器件的一个实例的截面图。
参见图2,半导体器件100可以包括:形成在具有外延层101a的半导体衬底101内的沟槽109(参见图3H),所述沟槽具有下沟槽部109b和上沟槽部109a,所述上沟槽部的宽度W1比下沟槽部109b的宽度W2宽;形成在沟槽109的内表面上的栅极绝缘层115;形成在沟槽109内的栅极绝缘层115上的栅极117;形成在半导体衬底101的外延层101a内并且与沟槽109的上侧壁接触的源极区119;形成在包括栅极117的沟槽109内的栅极绝缘层115上的层间绝缘层图案121;形成在半导体衬底101的外延层101a内的本体区101b;形成在本体区101b的表面内的高掺杂P型区125;以及形成为与本体区101b和源极区119彼此接触的金属层127。
栅极绝缘层115可以实施为氧化硅层,并且可以具有约至 的厚度。
栅极117可以由多晶硅制成并且形成在下沟槽部109b内。栅极117可以为约至厚。多晶硅可以掺杂有杂质。
源极区119可以形成在半导体衬底101内,并且可以接触上沟槽部109a。可以通过沿半导体衬底的与上沟槽部109a接触的区域注入N型杂质如砷或磷来形成源极区119。也就是说,源极区119可以形成在与上沟槽部109a相对应的半导体衬底101内。在该实例中,半导体衬底101可以用作漏极区。
此外,层间绝缘层121可以由绝缘材料如BPSG膜、HLD氧化物或者其组合制成,并且可以具有约至的厚度。
同时,P型本体区101b可以形成在半导体衬底101的沟槽109外部的外延层101a内。例如,可以通过将P型杂质如硼注入接触沟槽的表面中来在半导体衬底101的相邻沟槽109之间的外延层内形成P型本体区101b。
高掺杂P型区125可以使得金属层127与本体区101b之间能够进行欧姆接触。
如上文所述,根据本公开内容的半导体器件100,上沟槽部109a的宽度W1可以比下沟槽部109b的宽度W2宽。该结构布置可以增加每单位面积可以形成的沟槽数目,从而降低半导体器件的沟槽电阻。
例如,在上沟槽部的宽度W1比下沟槽部的宽度W2宽的情况下,半导体器件可以确保源极区119在接触上沟槽部的半导体衬底内。这可以最小化单元间距(沟槽-沟槽宽度),以增加单元密度。因此,可以降低作为使用沟槽的半导体器件的主要特征之一的导通电阻值Rdson。
在下文中,参见图3A至图3I,将描述用于制造具有所述构造的半导体器件的方法。
图3A至图3I示出半导体器件在其制造期间的截面视图,以依次示出用于制造这样的半导体器件的方法的一个实例。
如图3A所示,可以在高掺杂N型半导体衬底101上设置轻掺杂N型外延层101a。也就是说,高掺杂N型半导体衬底101中的杂质浓度可以比轻掺杂N型外延层101a中的杂质浓度高。
可以在由无源层区和有源区限定的半导体衬底101上依次沉积焊垫氧化物层103和焊垫氮化硅层105。在该实例中,可以将焊垫氧化物层103和焊垫氮化硅层105一起用作硬掩模材料层。此外,硬掩模材料层的厚度可以比深沟槽的深度更薄。使用该布置,可以减少或防止光敏层的缺陷涂覆。
参见图3B,可以在焊垫氮化硅层105上涂覆第一光敏层107。
接着,参见图3C,可以通过使用曝光掩模(未示出)的光刻工艺来对光敏层107进行曝光和显影,并且可以移除所显影的部分,从而形成第一光敏层图案107a。
可以将第一光敏层图案107a用作掩模来对构成硬掩模的焊垫氮化硅层105和焊垫氧化物层103进行蚀刻,以形成焊垫氮化硅图案105a和焊垫氧化物层图案103a。然后可以移除第一光敏层图案107a。在该实例中,通过执行蚀刻以穿透形成硬掩模的焊垫氮化硅层105和焊垫氧化物层103,能够防止或抑制出现在用于形成浅沟槽的蚀刻过程期间可能引起的光敏层的缺陷涂覆,所述浅沟槽形成沟槽的上沟槽部。也就是说,通过硬掩模蚀刻工艺,在硬掩模中的层的布置可以便于限定作为上沟槽部形成区的浅沟槽形成区的过程。然后,可以通过使用形成硬掩模的焊垫氮化硅图案105a来形成浅沟槽。
参见图3D,可以移除第一光敏层图案107a。随后,可以将构成硬掩模的焊垫氮化硅层图案105a和焊垫氧化物层图案103a用作蚀刻掩模来对半导体衬底101的位于这些图案下方的露出部分进行蚀刻,从而形成对应于浅沟槽的上沟槽部109a。
参见图3E,可以氧化半导体衬底的位于上沟槽部109a内的表面,以形成侧壁氧化物层111。例如,可以以热氧化的方式来生长侧壁氧化物层111。此外,可以省略形成侧壁氧化物层111的过程。
随后,仍参见图3E,可以在半导体衬底的包括侧壁氧化物层111和焊垫氮化硅层图案105a的整个表面上沉积氮化物层113。在该实例中,即使在省略侧壁氧化物层111的形成的情况下,也可以通过控制形成在半导体衬底的整个表面上的氮化物层113的厚度来调节上沟槽部109a的宽度。
参见图3F,可以对氮化物层113进行回蚀刻以在焊垫氮化物层图案105a的侧壁上形成氮化物层图案113a。在该实例中,在对氮化物层113进行回蚀刻的同时,还可以移除位于侧壁氧化物层111上的氮化物层113和位于上沟槽部109a上的侧壁氧化物层111。因此,可以露出半导体衬底101的在上沟槽部109a下方的外延层101a。
参见图3G,可以通过将构成硬掩模的焊垫氮化物层图案105a和氮化物层图案113a用作蚀刻掩模来对外延层101a所露出部分进行选择性蚀刻,从而形成作为深沟槽的下沟槽部109b。
参见图3H,可以移除焊垫氮化物层图案105a、焊垫氧化物层图案103a和侧壁氧化物层图案111a,从而形成具有上沟槽部109a和下沟槽部109b的沟槽109。如图所示,上沟槽部109a的宽度W1可以比下沟槽部109b的宽度W2宽。由于移除了位于上沟槽部109a的内侧壁上的侧壁氧化物层图案111a,所以通过所移除的侧壁氧化物层图案111a可以使下沟槽部109b的内宽度W2变宽。
参见图3I,可以在具有上沟槽部109a和下沟槽部109b的沟槽109的内表面上沉积栅极绝缘层115。例如,栅极绝缘层115可以被实施为氧化硅层,并且可以具有约至的厚度。
然后,可以在沟槽109内的栅极绝缘层115上沉积具有足以填充沟槽109的厚度的多晶硅层(未示出)。
然后,通过将P型杂质例如硼离子注入半导体衬底101的沟槽109外部的外延层101a中,可以在半导体衬底101的相邻沟槽109之间的外延层101a内形成P型本体区101b。例如,在没有单独掩模的情况下,可以将P型杂质离子注入半导体衬底101的外延层101a中。
然后可以对多晶硅层(未示出)进行回蚀刻。仅留下填充下沟槽部109b的部分,从而形成栅极117。多晶硅层可以掺杂有杂质。
接着,沿着形成上沟槽部109a的内壁的区域,可以将N型杂质如砷或磷注入进半导体衬底101的外延层101a的表面,从而在沿与上沟槽部109a接触的区域的半导体衬底101内形成源极区119。例如,可以在对应于上沟槽部109a的半导体衬底101内形成源极区119。半导体衬底101可以用作为漏极区。
参见图3J,当在半导体衬底101的包括栅极117和栅极绝缘层115的整个表面上沉积层间绝缘层之后,可以通过平坦化来选择性移除层间绝缘层,从而在沟槽109内形成层间绝缘层图案121。这里,层间绝缘层可以由绝缘材料如BPSG膜、HLD氧化物或其组合制成。
参见图3K,随后,为了使得半导体衬底101的本体区101b和源极区119能够彼此接触,可以使用自对准接触(SAC)蚀刻工艺来形成接触沟槽。然后可以通过将离子注入进接触沟槽的下表面来形成高掺杂P型区125。
接着,可以使用金属来填充接触沟槽以形成金属层127。因此,可以完成根据本公开内容的半导体器件100的制造过程。在该实例中,高掺杂P型区125可以使得金属层127与本体区101b之间能够进行欧姆接触。此外,可以通过沿每个沟槽的上表面延伸的层间绝缘层图案121使金属层127与栅极117绝缘。
图4为示出响应于根据本公开内容的半导体器件的单元间距的导通电阻值的变化的曲线图。
如图4所示,曲线图包括对应于4.5V的栅极-源极偏置电压的曲线。
可以注意到,在根据本公开内容的半导体器件中,单元间距减小至1.0μm。
因此,在根据本公开内容的半导体器件的单元间距中,根据栅极-源极偏置电压的导通电阻Rdson可以减少约20%至30%。
如上所述,根据本公开内容的半导体器件可以具有其宽度比下沟槽部的宽度宽的上沟槽部。这可以增加每单位面积形成的沟槽数目,从而导致减小半导体器件的沟槽电阻。
由于根据本公开内容的半导体器件具有宽度比下沟槽部的宽度宽的上沟槽部,所以可以确保源极区在与上沟槽部接触的半导体器件内。这可以最小化单元间距(沟槽-沟槽宽度)并且相应地增加单元密度。因此,可以降低作为使用沟槽的半导体器件的主要特征之一的导通电阻值。
上述为半导体器件及其制造方法的各种实例。尽管该实例可以改善相关技术中的一个或更多个缺点,但这不是必需的。详细描述的方面提供了具有减小的单元间距和降低的导通电阻的通过如下步骤形成的半导体器件及其制造方法:当形成沟槽时同时形成具有宽宽度的上沟槽;在具有宽宽度的上沟槽内形成层间绝缘层;并且随后使用层间绝缘层作为掩模来形成接触沟槽。
还提供了一种半导体器件,所述半导体器件包括:具有外延层的半导体衬底;形成在半导体衬底的外延层内的沟槽,所述沟槽具有宽度比下沟槽部宽的上沟槽部;形成在沟槽的内表面上的栅极绝缘层;形成在沟槽内的栅极绝缘层上的栅极;形成在包括栅极的沟槽内的栅极绝缘层上的层间绝缘层图案;形成在与沟槽的上沟槽部的侧壁接触的半导体衬底内的源极区;形成在半导体衬底外延层内的本体区;填充金属的接触沟槽,所述接触沟槽使得源极区和本体区能够彼此接触;以及形成在接触沟槽之下的高掺杂杂质区,所述高掺杂杂质区具有与本体区相同类型的杂质。
此外,提供了一种用于制造半导体器件的方法。所述方法可以包括:在具有外延层的半导体衬底上形成焊垫氧化物层图案和焊垫氮化物层图案;使用焊垫氮化物层图案作为蚀刻掩模来对半导体衬底进行选择性蚀刻,以在半导体衬底内形成上沟槽部;在包括上沟槽部的表面的焊垫氮化物层图案和焊垫氧化物层图案上形成氮化物层;对氮化物层的整个表面进行蚀刻,以在上沟槽部的侧壁和焊垫氮化物层图案与焊垫氧化物层图案的侧壁上形成氮化物层图案;使用焊垫氮化物层图案和氮化物层图案作为蚀刻掩模来对上沟槽部之下的半导体衬底进行蚀刻,以形成下沟槽部;对位于上沟槽部的侧壁上的氮化物层图案、焊垫氮化物层图案和焊垫氧化物层图案进行蚀刻,以形成具有下沟槽部和上沟槽部的沟槽,所述上沟槽部的宽度比下沟槽部宽;在沟槽的表面上形成栅极绝缘层;在下沟槽部和上沟槽部内的栅极绝缘层上沉积多晶硅,以填充沟槽;在半导体衬底的外延层内形成本体区;对多晶硅进行蚀刻,以在下沟槽部内形成栅极;通过离子注入在上沟槽部的侧表面上形成源极区;在上沟槽部内的栅极绝缘层上形成层间绝缘层图案;形成接触沟槽,以使得源极区和本体区能够彼此接触;在接触沟槽之下形成高掺杂杂质区,所述高掺杂杂质区具有与本体区相同类型的杂质;以及使用金属层来填充接触沟槽。
根据本公开内容的半导体器件及其制造方法,由于通过在形成沟槽时同时形成具有宽的上宽度的沟槽部来预先确保源极形成区,所以可以不需要单独的沟槽接触间隙。这可以最小化单元间距并且相应地增加相同面积内形成的沟槽数目。
此外,根据本发明内容的半导体器件及其制造方法,在构成沟槽的上沟槽部的宽度比下沟槽部宽的情况下,可以确保源极区在与上沟槽部接触的半导体衬底内。因此,可以减小沟槽接触间隙。这可以最小化单元间距(沟槽-沟槽宽度)并且相应地增加单元密度,从而导致作为使用沟槽的半导体器件的主要特征之一的导通电阻(Rdson)降低。
应当理解的是,本公开内容的特征可以以不同形式来实施并且不应当被解释为受限于本文所阐述的实例。相反,提供实施例是为了使得本公开内容将是全面和完整的,并且将向本领域技术人员传达本公开内容的全部范围。附图不一定按比例绘制,并且在某些情况下,为了清楚示出实例的特征,比例可能被放大。当第一层被表示为在第二层“上”或在衬底“上”时,它不仅可以表示第一层直接形成在第二层上或衬底上的情况,也可以表示第一层与第二层或衬底之间存在第三层的情况。另外,虽然表述例如“第一”或“第二”可以用来表示各种元件,但是所述元件不受限于该表述。表述仅用于将一个元件与其它元件区分的目的。除非另有说明,单数形式的表述包括复数含义。在整个说明书中,表述“包括”或“具有”仅用于指示存在本文所述的特性、数目、步骤、操作、元件、部件或其组合,但不排除其它特性、数目、步骤、操作、元件、部件或其组合中的一个或更多个或者增加物存在的可能性。
空间相关的表述例如“下方”、“之下”、“下”、“上方”、“上”等可以用于方便地描述一个器件或元件与其它器件或在元件中的关系。空间相关的表述应当被理解为包括附图中所示的方向,应当添加器件在使用或操作中的其它方向。此外,器件可以被定位为其它方向,并且相应地,基于该定位来解释空间相关的表述。
此外,本文所用的表述例如“第一导电类型”和“第二导电类型”可以表示彼此相反的导电类型例如N型或P型,并且本文所说明和举例的实例包括其补充实例。
上面已经描述了多个实例。然而,应当理解,可以进行各种修改。例如,在以不同顺序执行所述技术的情况下,并且/或者在以不同方式来合并和/或由其它部件或其等同物来替代或补充所述***、构造、器件或电路中的部件的情况下,可以实现适当的结果。因此,其它实施方式也在所附权利要求的范围内。
Claims (19)
1.一种半导体器件,包括:
设置在衬底的外延层内的沟槽,所述沟槽具有宽度比下沟槽部宽的上沟槽部;
设置在所述沟槽的所述下沟槽部的内表面上的栅极绝缘层;
设置在所述沟槽的所述下沟槽部内的栅极;
设置在位于包括所述栅极的所述沟槽内的所述栅极绝缘层上的层间绝缘层图案;
设置在所述衬底内并且接触所述沟槽的所述上沟槽部的侧壁的源极区;
设置在所述衬底的所述外延层内的本体区;
填充有金属的接触沟槽,所述接触沟槽使所述源极区和所述本体区彼此接触;以及
形成在所述接触沟槽之下的杂质区,所述杂质区具有与所述本体区相同类型的杂质并且具有比所述本体区高的杂质浓度。
2.根据权利要求1所述的器件,其中所述源极区的下表面形成为低于所述接触沟槽的下表面。
3.根据权利要求1所述的器件,其中所述栅极的上表面与所述接触沟槽的下表面齐平或者高于所述接触沟槽的下表面。
4.根据权利要求1所述的器件,其中从所述衬底的上表面至所述接触沟槽的下表面的深度为从所述衬底的所述上表面至所述下沟槽部的下表面的深度的一半。
5.根据权利要求1所述的器件,其中所述栅极的上表面与所述接触沟槽的下表面齐平或者低于所述接触沟槽的下表面。
6.根据权利要求1所述的器件,其中所述层间绝缘层图案包括BPSG膜、HLD氧化物或其组合。
7.一种半导体器件,包括:
设置在衬底内的沟槽,所述沟槽包括宽度比下沟槽部宽的上沟槽部;
设置在所述沟槽中的栅极;
设置在所述沟槽中的所述栅极上方的层间绝缘层图案;
设置在所述衬底内并且接触所述上沟槽部的侧壁和所述下沟槽部的侧壁的源极区;
设置在所述衬底中的所述源极区下方的本体区;以及
设置在本体区上方并且填充有导电材料的接触沟槽。
8.根据权利要求7所述的半导体器件,还包括:
形成在所述接触沟槽与所述本体区之间的杂质区,所述杂质区具有与所述本体区相同类型的杂质并且具有比所述本体区高的杂质浓度。
9.根据权利要求7所述的半导体器件,其中所述源极区的一部分设置在所述栅极的上表面上方。
10.一种用于制造半导体器件的方法,包括:
在衬底上形成焊垫氧化物层图案和焊垫氮化物层图案;
使用所述焊垫氮化物层图案作为蚀刻掩模来对所述衬底进行选择性蚀刻,以在所述衬底内形成上沟槽部;
在包括所述上沟槽部的表面的所述焊垫氮化物层图案和所述焊垫氧化物层图案上形成氮化物层;
对所述氮化物层的整个表面进行蚀刻,以在所述上沟槽部的侧壁以及所述焊垫氮化物层图案和所述焊垫氧化物层图案的侧壁上形成氮化物层图案;
使用所述焊垫氮化物层图案和所述氮化物层图案作为蚀刻掩模来对所述上沟槽部之下的衬底进行蚀刻,以形成下沟槽部;
对位于所述上沟槽部的所述侧壁上的所述氮化物层图案、所述焊垫氮化物层图案和所述焊垫氧化物层进行蚀刻,以形成具有所述下沟槽部和所述上沟槽部的沟槽,所述上沟槽部的宽度比所述下沟槽部宽;
在所述沟槽的表面上形成栅极绝缘层;
在所述下沟槽部和所述上沟槽部内的所述栅极绝缘层上沉积多晶硅;
在所述衬底的外延层内形成本体区;
对所述多晶硅进行蚀刻,以在所述下沟槽部内形成栅极;
在所述上沟槽部的侧表面上形成源极区;
在所述上沟槽部内的所述栅极绝缘层上形成层间绝缘层图案;
形成接触沟槽,使得所述源极区和所述本体区彼此接触;
在所述接触沟槽之下形成杂质区,所述杂质区具有与所述本体区相同类型的杂质并且具有比所述本体区高的杂质浓度;以及
使用金属层来填充所述接触沟槽。
11.根据权利要求10所述的方法,其中使用自对准接触蚀刻法来形成所述接触沟槽。
12.根据权利要求10所述的方法,其中所述层间绝缘层图案包括BPSG膜、HLD氧化物或其组合。
13.根据权利要求10所述的方法,其中通过对所述多晶硅进行回蚀刻来形成所述栅极。
14.根据权利要求10所述的方法,还包括:
在于所述上沟槽部的所述表面上形成氧化物层以及形成所述氮化物层之后,对所述氮化物层和所述氧化物层的整个表面进行蚀刻,以在所述上沟槽部的所述侧壁和所述焊垫氧化物层图案与所述焊垫氮化物层图案的所述侧壁上形成所述氧化物层图案和所述氮化物层图案。
15.根据权利要求14所述的方法,其中使用自对准接触蚀刻法来形成所述接触沟槽。
16.根据权利要求14所述的方法,其中所述层间绝缘层图案包括BPSG膜、HLD氧化物或其组合。
17.根据权利要求14所述的方法,其中通过对所述多晶硅进行回蚀刻来形成所述栅极。
18.一种用于制造包括具有上沟槽部和下沟槽部的沟槽的半导体器件的方法,所述方法包括:
通过使用硬掩模材料层在衬底中形成第一沟槽;
沿所述第一沟槽的露出表面形成氧化物层;
沿所述硬掩模材料层的露出表面形成氮化物层;
沿所述第一沟槽的底表面对所述氧化物层进行蚀刻以露出所述底表面,同时保留所述氧化物层的沿所述第一沟槽的侧表面的至少一部分;
对所述第一沟槽的露出的底表面之下的衬底进行蚀刻以形成所述沟槽的所述下沟槽部;以及
沿所述第一沟槽的所述侧表面移除所述氧化物层以形成所述沟槽的所述上沟槽部,所述上沟槽部的宽度比所述下沟槽部宽。
19.根据权利要求18所述的方法,还包括:
沿所述上沟槽部的侧表面形成源极区;
在所述下沟槽部内形成栅极;
在所述上沟槽部内形成层间绝缘层图案;
形成接触沟槽,以接触所述源极区;
在所述接触沟槽之下形成杂质区;以及
使用导电材料填充所述接触沟槽。
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