CN106201945A - Bit width conversion device - Google Patents
Bit width conversion device Download PDFInfo
- Publication number
- CN106201945A CN106201945A CN201610485689.0A CN201610485689A CN106201945A CN 106201945 A CN106201945 A CN 106201945A CN 201610485689 A CN201610485689 A CN 201610485689A CN 106201945 A CN106201945 A CN 106201945A
- Authority
- CN
- China
- Prior art keywords
- bit width
- output
- width conversion
- control unit
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The present invention provides a kind of bit width conversion device, is applied between the first module and the second module that data bit width differs.Described device includes: bit width conversion sends sub-device and bit width conversion receives sub-device.Wherein, described bit width conversion sends sub-device by the bit wide that the bit width conversion of described first module is described second module, and described bit width conversion receives sub-device by bit wide that the bit width conversion of described second module is described first module.Said apparatus is possible not only to realize the bit width conversion between different bit wide module, can also be verified by the data that described bit width conversion device is changed by pseudo-random sequence checker, above-mentioned bit width conversion device can find the mistake in bit width conversion design in time, and send interrupt signal when mistake occurs, bring great convenience to the emulation of chip, test, improve the reliability of system.
Description
Technical field
The present invention relates to chip design field, be specifically that in a kind of solution actual chips design, intermodule needs interface
The device of bit width conversion.
Background technology
In actual chip design engineering, the bit wide of modules A and module B data interface is probably unmatched, in order to
Enabling modules A and module B to be mutually butted, this is to be accomplished by the device that a kind of interface bit wide mutually changes to realize different bit wide
Under data conversion.
Such as, in exchanger chip designs, the 64B/66B coding that 10G network interface (10G Base-R) uses, module exports
Data bit width be 66 bits, and coupled deserializer (Serdes) is owing to using intellectual property
(Intellectual Property is called for short IP) core, generally has its fixing bit wide (such as 32 bits).Therefore at exchanger core
Need a bit width conversion device to carry out the conversion between different pieces of information bit wide when sheet is arranged.The design of bit width conversion device is
The problem being frequently encountered by exchanger chip design.
In actual engineering, owing to the bit wide of data is converted, this will make the original certain sense of data
Can disappear.So the emulation of chip, test can be brought certain difficulty, it is impossible to enough discovery in time is deposited in bit width conversion design
Design mistake.
Summary of the invention
In view of this, the purpose of the embodiment of the present invention is to provide a kind of bit wide can changed different bit wide data
Conversion equipment, with the conversion solved between different bit wide Data Data with find design mistake present in bit width conversion design in time
Technical problem by mistake.
To achieve these goals, the technical scheme that the embodiment of the present invention uses is as follows:
The embodiment of the present invention provides a kind of a kind of bit width conversion device, be applied to the first module that data bit width differs with
Between second module.Described device includes: bit width conversion sends sub-device and bit width conversion receives sub-device.Wherein, institute's rheme
Wide conversion sends the bit wide that the bit width conversion of described first module is described second module by sub-device, and described bit width conversion receives
Sub-device is by bit wide that the bit width conversion of described second module is described first module.
Described bit width conversion send sub-device include pseudo-random sequence generator, selector, the first stacked control unit, the
One asynchronous input into/output from cache, first pop control unit, the first enumerator and send control unit.Described pseudo-random sequence is sent out
The outfan of raw device and the data output end of described first module input with described selector respectively is connected.Described selector
Control end input select signal for input data are selected, the outfan of described selector is first asynchronous defeated with described
The stacked data terminal entering output caching connects.Described first stacked control unit enters with described first asynchronous input into/output from cache
Stack signal controls end and connects.The data terminal of popping of described first asynchronous input into/output from cache is connected with sending control unit.Described
First signal of popping popping control unit and described first asynchronous input into/output from cache controls end and is connected.Described first enumerator
It is connected to described first pop between control unit and described transmission control unit.Writing of described first asynchronous input into/output from cache
Clock frequency is identical with the clock frequency of described first module.The reading clock frequency of described first asynchronous input into/output from cache and institute
The clock frequency stating the second module is identical.
Described bit width conversion receive sub-device include pseudo-random sequence checker, second pop control unit, receive control
Unit, the second timer, the second stacked control unit and the second asynchronous input into/output from cache.The input of described reception control unit
End is connected with the data output end of described second module, and the outfan of described reception control unit is defeated with described second asynchronous input
The stacked data terminal going out caching connects.Described second stacked control unit and the stacked letter of described second asynchronous input into/output from cache
Number control end connect.Described second timer is connected between described second stacked control unit and described reception control unit.
Described second signal of popping popping control unit and described second asynchronous input into/output from cache controls end and is connected.Described second different
The data output end of popping of step input into/output from cache is connected with the data input pin of described first module, described second asynchronous input
The data output end of popping of output caching is also connected with described pseudo-random sequence checker.Described pseudo-random sequence checker is to institute
The data of the output stating the data output end of popping of the second asynchronous input into/output from cache verify.Described second asynchronous input is defeated
The reading clock frequency going out caching is identical with the clock frequency of described first module.When writing of described first asynchronous input into/output from cache
Clock frequency rate is identical with the clock frequency of described second module.
Further, described in described bit width conversion device, the bit wide of the first module is 66 bits, described second module
Bit wide is 32 bits.
Further, the first enumerator described in described bit width conversion device and described second enumerator carry out 0 to 32
Cycle count.
Further, the clock frequency of writing of the first asynchronous input into/output from cache described in described bit width conversion device is
156.25MHz, the reading clock frequency of described first asynchronous input into/output from cache is 322.265625MHz；Described second asynchronous defeated
The clock frequency of writing entering output caching is 322.265625MHz, and the reading clock frequency of described first asynchronous input into/output from cache is
156.25MHz。
Further, the first module described in described bit width conversion device is equal with the data bandwidth of described second module.
Further, send control unit described in described bit width conversion device to include: the first remaining bits depositor, institute
State the first remaining bits depositor remaining Bit data during depositing bit width conversion.
Further, pseudo-random sequence checker described in described bit width conversion device, when checking appearance mistake, exports
Interrupt signal.
Further, described in described bit width conversion device, the first control unit of popping includes the first obstructive root canal list
Unit, described first obstructive root canal subelement is for stoping the Pop operations of data in the first asynchronous input into/output from cache.
Further, described in described bit width conversion device, the second control unit of popping includes the second obstructive root canal list
Unit, described second obstructive root canal subelement is for stoping the Pop operations of data in the second asynchronous input into/output from cache.
Further, pseudo-random sequence generator described in described bit width conversion device, when selection signal is 1, sends institute
State pseudo-random sequence to test to described pseudo-random sequence checker.
Relative to prior art, the bit width conversion device that the present invention provides is possible not only to realize between different bit wide module
Bit width conversion, it is also possible to the data changed described bit width conversion device by pseudo-random sequence checker are verified, above-mentioned
Bit width conversion device can find the mistake in bit width conversion design in time, and sends interrupt signal, to core when there is mistake
The emulation of sheet, test bring great convenience, and improve the reliability of system.
For making the above-mentioned purpose of the present invention, feature and advantage to become apparent, preferred embodiment cited below particularly, and coordinate
Appended accompanying drawing, is described in detail below.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below by embodiment required use attached
Figure is briefly described, it will be appreciated that the following drawings illustrate only certain embodiments of the present invention, and it is right to be therefore not construed as
Restriction, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to attached according to these
Figure obtains the accompanying drawing that other are relevant.
Fig. 1 is the electrical block diagram that the embodiment of the present invention provides bit width conversion device.
Fig. 2 is the fundamental diagram of pseudo-random sequence generator in Fig. 1.
The fundamental diagram of pseudo-random sequence detector in Fig. 1 during Fig. 3.
Main element symbol description
| Bit width conversion device | 100 |
| Bit width conversion sends sub-device | 110 |
| Pseudo-random sequence generator | 111 |
| Selector | 112 |
| First stacked control unit | 113 |
| First asynchronous input into/output from cache | 114 |
| First pops control unit | 115 |
| First obstructive root canal subelement | 1151 |
| First enumerator | 116 |
| Send control unit | 117 |
| First data select subelement | 1171 |
| First remaining bits depositor | 1172 |
| Bit width conversion receives sub-device | 120 |
| Pseudo-random sequence checker | 121 |
| Second pops control unit | 122 |
| Second obstructive root canal subelement | 1221 |
| Second asynchronous input into/output from cache | 123 |
| Second stacked control unit | 124 |
| Second enumerator | 125 |
| Reception control unit | 126 |
| Second data select subelement | 1261 |
| Second remaining bits depositor | 1262 |
Detailed description of the invention
Below in conjunction with accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground describes, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Generally exist
Can arrange and design with various different configurations with the assembly of the embodiment of the present invention that illustrates described in accompanying drawing herein.Cause
This, be not intended to limit claimed invention to the detailed description of the embodiments of the invention provided in the accompanying drawings below
, but it is merely representative of the selected embodiment of the present invention.Based on embodiments of the invention, those skilled in the art are not making
The every other embodiment obtained on the premise of creative work, broadly falls into the scope of protection of the invention.
Refer to Fig. 1, be the electrical block diagram of the bit width conversion device 100 that the embodiment of the present invention provides, institute's rheme
Wide conversion equipment 100 is connected between the first module and the second module, the data bit width of described first module and described second mould
The data bit width of block differs, and described bit width conversion device 100 can realize between described first module and described second module
The conversion of bit wide data.
In the present embodiment, described bit width conversion device 100 includes that bit width conversion sends sub-device 110 and bit width conversion connects
Receive sub-device 120.Wherein, described bit width conversion sends sub-device 110 is described second by the bit width conversion of described first module
The bit wide of module.It is described first module by the bit width conversion of described second module that described bit width conversion receives sub-device 120
Bit wide.
Described bit width conversion sends pseudo-random sequence generator 111, the choosing that sub-device 110 includes being electrically connected with each other
Select device 112, first stacked control unit the 113, first asynchronous input into/output from cache 114, first pop control unit 115, first
Enumerator 116 and transmission control unit 117.
The outfan of described pseudo-random sequence generator 111 and the data output end of described first module respectively with described choosing
The input selecting device 112 connects, the control end input select signal of described selector 112.When described selection signal is 1, institute
State selector 112 export pseudo-random binary sequence to described bit width conversion receive sub-device 120 carry out middle inspection；In described choosing
Selecting signal when being 0, described selector 112 exports the input data of described first module.
The outfan of described selector 112 is connected with the stacked data terminal of described first asynchronous input into/output from cache 114, institute
State the first stacked control unit 123 to be connected with the stacked signal control end of described first asynchronous input into/output from cache 114.Described
The data terminal of popping of one asynchronous input into/output from cache 114 is connected with described transmission control unit 117.Described pop control unit with
The signal of popping of described first asynchronous input into/output from cache 114 controls end and connects.Described first enumerator 116 goes out described in being connected to
Between stack control unit and described transmission control unit 117.Described first asynchronous input into/output from cache 114 write clock frequency with
The clock frequency of described first module is identical, the reading clock frequency and described second of described first asynchronous input into/output from cache 114
The clock frequency of module is identical.
Described bit width conversion receive pseudo-random sequence checker 121 that sub-device 120 includes being electrically connected with each other, the
Two pop control unit the 122, second timer 125, reception control unit the 126, second stacked control units 124 and second are asynchronous
Input into/output from cache 123.
The input of described reception control unit 126 is connected with the data output end of described second module, and described reception is controlled
The outfan of unit 126 processed is connected with the stacked data terminal of described second asynchronous input into/output from cache 123.Described second stacked control
Unit 124 processed controls end with the stacked signal of described second asynchronous input into/output from cache 123 and is connected.Described second timer connects
Between described second stacked control unit 124 and described reception control unit 126.Described second pop control unit 122 with
The signal of popping of described second asynchronous input into/output from cache 123 controls end and connects.
The data output end data input pin with described first module of popping of described second asynchronous input into/output from cache 123
Connecting, the data output end of popping of described second asynchronous input into/output from cache 123 also connects with described pseudo-random sequence checker 121
Connect, the output to the data output end of popping of described second asynchronous input into/output from cache 123 of the described pseudo-random sequence checker 121
Data verify.The reading clock frequency of described second asynchronous input into/output from cache 123 and the time clock frequency of described first module
Rate is identical, described first asynchronous input into/output from cache 114 to write clock frequency identical with the clock frequency of described second module.
Further, in the present embodiment, described transmission control unit 117 includes: the first remaining bits depositor 1172,
Described first remaining bits depositor 1172 be used for depositing bit width conversion during remaining Bit data.
Further, in the present embodiment, the described first control unit 115 of popping includes the first obstructive root canal subelement
1151, described first obstructive root canal subelement 1151 is for stoping the behaviour that pops of data in the first asynchronous input into/output from cache 114
Make.Described second control unit 122 of popping includes that the second obstructive root canal subelement, described second obstructive root canal subelement are used for hindering
The only Pop operations of data in the second asynchronous input into/output from cache 123.
Specifically, being 66 bits with the data bit width of the first module below, the bit wide of described second module is that 32 bits are
The operation principle of the wide conversion equipment of example place of matchmakers rheme 100.In the case, described in described bit width conversion device 100 first
Asynchronous input into/output from cache 114 write clock frequency 156.25MHz, the reading clock of described first asynchronous input into/output from cache 114
Frequency 322.265625MHz；Described second asynchronous input into/output from cache 123 write clock frequency 322.265625MHz, described
Reading clock frequency 156.25MHz of one asynchronous input into/output from cache 114.
Specific works principle is as follows
Bit width conversion sends sub-device 110 end: it is 66 bits that bit width conversion sends the data bit width of sub-device 110 input,
Clock frequency is 156.25MHz (clock66b)；The data bit width of the output that bit width conversion sends sub-device 110 is 32 bits,
Clock frequency is 322.265625MHz (clock32b).Wherein, the bandwidth of the data of the data of input and output is
10.3125Gbps。
The puppet that 66 Bit datas (dataIn) and the pseudo-random sequence generator 111 of input are produced by described selector 112
Random binary sequence (Pseudo-Random Binary Sequence is called for short PRBS) selects.Selection signal is
testEn.If testEn is 1, then sends PRBS data stream, otherwise send 66 Bit datas.Wherein pseudo-random sequence generator
111 use PRBS31 algorithm, and as shown in Equation 1, pseudo-random sequence generator 111 fundamental diagram is as shown in Figure 2 for its multinomial.
When testEn is 1, send PRBS Sequence, receive sub-device 120 end to bit width conversion and test.
1+x28+x31
In formula, x is the data of input, x28Represent the 28th of data, x31Represent the 31st of data ,+represent XOR
Operation.
66 Bit datas are write in described first asynchronous input into/output from cache 114 and carries out cross clock domain operation, each
Clock66b clock pushes on once at described first asynchronous input into/output from cache 114.System brings into operation when, to first
The input of asynchronous input into/output from cache 114 carries out keeping operation, is waiting after 16 clock32b clock cycle, and now first
Just having the data of 8 degree of depth in asynchronous input into/output from cache 114, start the first enumerator 116, the first enumerator 116 starts 0
To the cycle count of 32.Carry out Pop operations simultaneously, the logic of control unit of popping be the first enumerator 116 for odd number time, just
Carry out a Pop operations.Input the data of 66 bits every time at described first asynchronous input into/output from cache 114, need 2
The clock32b clock cycle could send the data of 64 bits, the most also can be stored in the first remaining bits by remaining 2 Bit datas
In depositor 1172.Described transmission control unit 117 can also include: the first data select subelement 1171, through 32
The clock32b clock cycle, now the data in the first remaining bits depositor 1172 reach 32 bits, described first data choosing
Select subelement 1171 to be sent out by 32 Bit datas of the first remaining bits depositor 1172 when the 33rd clock32b clock cycle
Go out, just complete the 1 data conversion taking turns 66 bits to 32 bits.
Data at the first asynchronous input into/output from cache 114 are popped end, and the first obstructive root canal (Hold Control) is single
The function of unit 1151 is system brings into operation when, stops the Pop operations of the first asynchronous input into/output from cache 114, allows the
One asynchronous input into/output from cache 114 accumulates a certain amount of data, to prevent the first asynchronous input into/output from cache 114 from occurring to underflow
Go out (Underrun).
In the present embodiment, described first enumerator 116, control signal of popping (pop), data of popping (pop data), the
The relation of one remaining bits depositor 1172 and output 32 Bit datas is as shown in table 1 below.
Table 1
Bit width conversion sub-device 120 end of reception:
The data bit width of input is 32 bits, and clock frequency is 322.265625MHz (clock32b)；The data bit of output
A width of 66 bits, clock frequency is 156.25MHz (clock66b).
At the stacked data segment end of the second asynchronous input into/output from cache 123, start the second enumerator 125, described second meter
Number device 125 is the cycle count of 0 to 32.For 32 Bit datas of input, after being combined into 66 Bit datas, just can carry out once
The Pop operations of the second asynchronous input into/output from cache 123.When after first three 32 Bit data input, it is combined into 66 Bit datas, enters
Pop operations of row, three 32 Bit datas now inputted there remains the data of 30 bits.This is stored in reception and controls single
The second remaining bits depositor 1262 under unit 126.Described reception control unit 126 can also include that the second data select son single
Unit 1261, hereafter the data in described second asynchronous input into/output from cache 123 are just carried out by each two clock32b clock cycle
Once pop.Until the second data select subelement 1261 by the second remaining bits depositor under reception control unit 126
In 1262, remaining data distribute.The logic of the signal of control unit of popping is that the second enumerator 125 is even number and is not 0
Time, carry out a Pop operations.Through 33 clock32b clock cycle, one can be completed and take turns 32 bits data to 66 bits
Conversion.System brings into operation when, carry out maintaining operation to the data terminal of popping of the second asynchronous input into/output from cache 123,
After waiting 8 clock66b clock cycle, the second asynchronous input into/output from cache 123 now has the data of 8 degree of depth, carries out
Pop operations.The logic of the signal of control unit of popping is once to pop each clock66b clock cycle, and will pop
The data output obtained.When being 1 when checking signal testEn, the data that described pseudo-random sequence checker 121 obtains popping
Carry out PRBS inspection, if it is checked that wrong, then reporting interruption signal, show data transforming mistakes.
Second enumerator 125, the control signal that pushes on (push signal), input data, the second remaining bits depositor 1262
And the relation of the data that push on (push data) is as shown in table 2:
Table 2
From Table 2, it can be seen that through 33 clock32b clock cycle, one can be completed and takes turns 32 bits to 66 bits
Data are changed.
Data at the second asynchronous input into/output from cache 123 are popped end, and the second obstructive root canal (Hold Control) is single
The function of unit 1221 is system brings into operation when, stops the Pop operations of the second asynchronous input into/output from cache 123, allows the
Two asynchronous input into/output from caches 123 accumulate a certain amount of data, to prevent the second asynchronous input into/output from cache 123 from occurring to underflow
Go out (Underrun).After the second asynchronous input into/output from cache 123 is accumulated to a certain amount of data, at each clock66b clock
Rising edge, carry out a Pop operations, and the 66 Bit datas outputs obtained popping.Carry out according to the data that push on simultaneously
PRBS checks, the principle of PRBS31 detector is as shown in Figure 3.Makeing mistakes if PRBS checks, module can export an interrupt
Signal, shows mistake occur in data conversion.
In sum, the bit width conversion device 100 that the embodiment of the present invention provides be possible not only to realize different bit wide module it
Between bit width conversion, it is also possible to the data changed described bit width conversion device 100 by pseudo-random sequence checker 121 are carried out
Verification, above-mentioned bit width conversion device 100 can find the mistake in bit width conversion design in time, and send when there is mistake
Break signal, brings great convenience to the emulation of chip, test, improves the reliability of system.
The above, the only detailed description of the invention of the present invention, but the protection of the present invention is not limited thereto, and any familiar
Those skilled in the art, in the technology that the invention discloses, can readily occur in change or replace, should contain at this
Within bright protection.Therefore, the protection of the present invention should described be as the criterion with the protection of claim.
Claims (10)
1. a bit width conversion device, it is characterised in that be applied to the first module and the second module that data bit width differs it
Between, described device includes: bit width conversion sends sub-device and bit width conversion receives sub-device, and wherein, described bit width conversion sends
Sub-device is by the bit wide that the bit width conversion of described first module is described second module, and described bit width conversion receives sub-device by institute
State the bit wide that bit width conversion is described first module of the second module；
Described bit width conversion sends sub-device and includes pseudo-random sequence generator, selector, the first stacked control unit, first different
Step input into/output from cache, first pop control unit, the first enumerator and send control unit, described pseudo-random sequence generator
Outfan and the data output end input with described selector respectively of described first module be connected, the control of described selector
End input select signal processed is for selecting input data, and the outfan of described selector is defeated with described first asynchronous input
The stacked data terminal going out caching connects, described first stacked control unit and the stacked letter of described first asynchronous input into/output from cache
Number control end connect, described first asynchronous input into/output from cache pop data terminal with transmission control unit be connected, described first
Control unit of popping controls end with the signal of popping of described first asynchronous input into/output from cache and is connected, and described first enumerator connects
Pop between control unit and described transmission control unit in described first, described first asynchronous input into/output from cache write clock
Frequency is identical with the clock frequency of described first module, the reading clock frequency of described first asynchronous input into/output from cache and described the
The clock frequency of two modules is identical；
Described bit width conversion receive sub-device include pseudo-random sequence checker, second pop control unit, reception control unit,
Second timer, the second stacked control unit and the second asynchronous input into/output from cache, the input of described reception control unit with
The data output end of described second module connects, and the outfan of described reception control unit delays with described second asynchronous input and output
The stacked data terminal deposited connects, described second stacked control unit and the stacked signal control of described second asynchronous input into/output from cache
End processed connects, and described second timer is connected between described second stacked control unit and described reception control unit, described
Second signal of popping popping control unit and described second asynchronous input into/output from cache controls end and is connected, described second asynchronous defeated
The data output end of popping entering output caching is connected with the data input pin of described first module, described second asynchronous input and output
The data output end of popping of caching is also connected with described pseudo-random sequence checker, and described pseudo-random sequence checker is to described the
The data of the output of the data output end of popping of two asynchronous input into/output from caches verify, and described second asynchronous input and output are delayed
The reading clock frequency deposited is identical with the clock frequency of described first module, clock frequency when writing of described first asynchronous input into/output from cache
Rate is identical with the clock frequency of described second module.
2. bit width conversion device as claimed in claim 1, it is characterised in that:
The bit wide of described first module is 66 bits, and the bit wide of described second module is 32 bits.
3. bit width conversion device as claimed in claim 2, it is characterised in that:
Described first enumerator and described second enumerator carry out the cycle count of 0 to 32.
4. bit width conversion device as claimed in claim 2, it is characterised in that:
The clock frequency of writing of described first asynchronous input into/output from cache is 156.25MHz, described first asynchronous input into/output from cache
Reading clock frequency 322.265625MHz；
The clock frequency of writing of described second asynchronous input into/output from cache is 322.265625MHz, described first asynchronous input and output
The reading clock frequency of caching is 156.25MHz.
5. bit width conversion device as claimed in claim 1, it is characterised in that:
Described first module is equal with the data bandwidth of described second module.
6. bit width conversion device as claimed in claim 1, it is characterised in that described transmission control unit includes:
First remaining bits depositor, described first remaining bits depositor be used for depositing bit width conversion during remaining bit
Data.
7. bit width conversion device as claimed in claim 1, it is characterised in that: described pseudo-random sequence checker is checking occur
During mistake, export interrupt signal.
8. bit width conversion device as claimed in claim 1, it is characterised in that: the described first control unit of popping includes the first resistance
Plug controls subelement, and described first obstructive root canal subelement is for stoping the behaviour that pops of data in the first asynchronous input into/output from cache
Make.
9. bit width conversion device as claimed in claim 1, it is characterised in that: the described second control unit of popping includes the second resistance
Plug controls subelement, and described second obstructive root canal subelement is for stoping the behaviour that pops of data in the second asynchronous input into/output from cache
Make.
10. bit width conversion device as claimed in claim 1, it is characterised in that:
Described pseudo-random sequence generator, when selection signal is 1, sends pseudo-random binary sequence to described pseudo-random sequence
Checker is tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610485689.0A CN106201945B (en) | 2016-06-28 | 2016-06-28 | Bit width conversion device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610485689.0A CN106201945B (en) | 2016-06-28 | 2016-06-28 | Bit width conversion device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106201945A true CN106201945A (en) | 2016-12-07 |
| CN106201945B CN106201945B (en) | 2017-07-11 |
Family
ID=57460947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610485689.0A Active CN106201945B (en) | 2016-06-28 | 2016-06-28 | Bit width conversion device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106201945B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109002409A (en) * | 2017-06-07 | 2018-12-14 | 深圳市中兴微电子技术有限公司 | A kind of bit wide converting means and method |
| CN110221994A (en) * | 2018-03-01 | 2019-09-10 | 深圳市中兴微电子技术有限公司 | A kind of method and device of data bit width conversion, computer readable storage medium |
| US10698851B1 (en) | 2018-12-12 | 2020-06-30 | Realtek Semiconductor Corp. | Data bit width converter and system on chip thereof |
| CN111367846A (en) * | 2018-12-25 | 2020-07-03 | 瑞昱半导体股份有限公司 | Data bit width converter and system chip thereof |
| CN112054942A (en) * | 2020-09-15 | 2020-12-08 | 中电科仪器仪表有限公司 | Random data packet generation method with any length for high bit width framing error code test |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103686441A (en) * | 2013-10-10 | 2014-03-26 | 北京空间机电研究所 | Multi-format data transmission system |
| CN104022775A (en) * | 2014-06-02 | 2014-09-03 | 复旦大学 | FIFO protocol based digital interface circuit for SerDes technology |
| CN104375962A (en) * | 2014-11-10 | 2015-02-25 | 中国航天科技集团公司第九研究院第七七一研究所 | Unified bit width converting structure and method in cache and bus interface of system chip |
-
2016
- 2016-06-28 CN CN201610485689.0A patent/CN106201945B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103686441A (en) * | 2013-10-10 | 2014-03-26 | 北京空间机电研究所 | Multi-format data transmission system |
| CN104022775A (en) * | 2014-06-02 | 2014-09-03 | 复旦大学 | FIFO protocol based digital interface circuit for SerDes technology |
| CN104375962A (en) * | 2014-11-10 | 2015-02-25 | 中国航天科技集团公司第九研究院第七七一研究所 | Unified bit width converting structure and method in cache and bus interface of system chip |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109002409A (en) * | 2017-06-07 | 2018-12-14 | 深圳市中兴微电子技术有限公司 | A kind of bit wide converting means and method |
| CN110221994A (en) * | 2018-03-01 | 2019-09-10 | 深圳市中兴微电子技术有限公司 | A kind of method and device of data bit width conversion, computer readable storage medium |
| CN110221994B (en) * | 2018-03-01 | 2022-04-08 | 深圳市中兴微电子技术有限公司 | Method and device for data bit width conversion and computer readable storage medium |
| US10698851B1 (en) | 2018-12-12 | 2020-06-30 | Realtek Semiconductor Corp. | Data bit width converter and system on chip thereof |
| TWI727236B (en) * | 2018-12-12 | 2021-05-11 | 瑞昱半導體股份有限公司 | Data bit width converter and system on chip thereof |
| CN111367846A (en) * | 2018-12-25 | 2020-07-03 | 瑞昱半导体股份有限公司 | Data bit width converter and system chip thereof |
| CN111367846B (en) * | 2018-12-25 | 2022-01-11 | 瑞昱半导体股份有限公司 | Data bit width converter and system chip thereof |
| CN112054942A (en) * | 2020-09-15 | 2020-12-08 | 中电科仪器仪表有限公司 | Random data packet generation method with any length for high bit width framing error code test |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106201945B (en) | 2017-07-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106201945A (en) | Bit width conversion device | |
| KR101714630B1 (en) | Computer memory test structure | |
| US8275922B2 (en) | Implementing serial link training patterns separated by random data for training a serial link in an interconnect system | |
| US6977960B2 (en) | Self test circuit for evaluating a high-speed serial interface | |
| US8832511B2 (en) | Built-in self-test for interposer | |
| US7783935B2 (en) | Bit error rate reduction buffer | |
| US8804960B2 (en) | Implementing known scrambling relationship among multiple serial links | |
| WO2003046925A2 (en) | Built-in self-testing for double data rate input/output interface | |
| US20110299581A1 (en) | Built-in self-test circuitry | |
| US10613128B2 (en) | Testing device and testing method | |
| US7627806B1 (en) | Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device | |
| US7783954B2 (en) | System for controlling high-speed bidirectional communication | |
| US8582706B2 (en) | Training a data path for parallel data transfer | |
| US11609872B2 (en) | Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver | |
| US7721160B2 (en) | System for protecting data during high-speed bidirectional communication between a master device and a slave device | |
| US9148155B1 (en) | Clock distribution architecture for integrated circuit | |
| WO2010065290A2 (en) | Memory system with command filtering | |
| CN112073152B (en) | FPGA anti-interference processing method for improving reliability of CHSI received data | |
| US20040136462A1 (en) | Method and apparatus for ensuring receiver lock | |
| US9170869B2 (en) | Switchable per-lane bit error count | |
| US7024618B2 (en) | Transmission error checking in result forwarding | |
| JP7026154B2 (en) | Pattern synchronization circuit, error rate measuring device using it, and pattern synchronization method | |
| Mounika et al. | Design and Verification of Impedance Matcher in a High Speed Serial IO Interface in 14-nm Technology | |
| Santoro | DESIGN AND IMPLEMENTATION OF A HIGH-SPEED DATA LINK FOR A DATAFLOW SUPERCOMPUTER | |
| Nagaraju et al. | Design and Verification of High Speed IO Transmitter in 14nm Technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 412200, Liling City, Hunan Province ceramic science and Technology Industrial Park B District Applicant after: Hunan Hengmao tech Limited by Share Ltd Address before: 412200, Liling City, Hunan Province ceramic science and Technology Industrial Park B District Applicant before: Liling Hengmao Electronics Technology Co., Ltd. |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |